1 import collections
as _collections
3 import dataclasses
as _dataclasses
5 import functools
as _functools
7 import operator
as _operator
8 import pathlib
as _pathlib
13 from functools
import cached_property
15 from cached_property
import cached_property
17 from openpower
.decoder
.power_enums
import (
18 Function
as _Function
,
25 CRIn2Sel
as _CRIn2Sel
,
26 CROutSel
as _CROutSel
,
28 LDSTMode
as _LDSTMode
,
33 SVMaskSrc
as _SVMaskSrc
,
38 SVP64RMMode
as _SVP64RMMode
,
39 SVExtraRegType
as _SVExtraRegType
,
40 SVExtraReg
as _SVExtraReg
,
41 SVP64SubVL
as _SVP64SubVL
,
42 SVP64Pred
as _SVP64Pred
,
43 SVP64PredMode
as _SVP64PredMode
,
44 SVP64Width
as _SVP64Width
,
46 from openpower
.decoder
.selectable_int
import (
47 SelectableInt
as _SelectableInt
,
48 selectconcat
as _selectconcat
,
50 from openpower
.decoder
.power_fields
import (
53 DecodeFields
as _DecodeFields
,
55 from openpower
.decoder
.pseudo
.pagereader
import ISA
as _ISA
58 @_functools.total_ordering
59 class Style(_enum
.Enum
):
63 VERBOSE
= _enum
.auto()
65 def __lt__(self
, other
):
66 if not isinstance(other
, self
.__class
__):
68 return (self
.value
< other
.value
)
71 @_functools.total_ordering
72 class Priority(_enum
.Enum
):
78 def _missing_(cls
, value
):
79 if isinstance(value
, str):
84 return super()._missing
_(value
)
86 def __lt__(self
, other
):
87 if not isinstance(other
, self
.__class
__):
90 # NOTE: the order is inversed, LOW < NORMAL < HIGH
91 return (self
.value
> other
.value
)
94 def dataclass(cls
, record
, keymap
=None, typemap
=None):
98 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
100 def transform(key_value
):
101 (key
, value
) = key_value
102 key
= keymap
.get(key
, key
)
103 hook
= typemap
.get(key
, lambda value
: value
)
104 if hook
is bool and value
in ("", "0"):
110 record
= dict(map(transform
, record
.items()))
111 for key
in frozenset(record
.keys()):
112 if record
[key
] == "":
118 @_functools.total_ordering
119 @_dataclasses.dataclass(eq
=True, frozen
=True)
122 def __new__(cls
, value
):
123 if isinstance(value
, str):
124 value
= int(value
, 0)
125 if not isinstance(value
, int):
126 raise ValueError(value
)
128 if value
.bit_length() > 64:
129 raise ValueError(value
)
131 return super().__new
__(cls
, value
)
134 return self
.__repr
__()
137 return f
"{self:0{self.bit_length()}b}"
139 def bit_length(self
):
140 if super().bit_length() > 32:
144 class Value(Integer
):
153 def __lt__(self
, other
):
154 if not isinstance(other
, Opcode
):
155 return NotImplemented
156 return ((self
.value
, self
.mask
) < (other
.value
, other
.mask
))
159 def pattern(value
, mask
, bit_length
):
160 for bit
in range(bit_length
):
161 if ((mask
& (1 << (bit_length
- bit
- 1))) == 0):
163 elif (value
& (1 << (bit_length
- bit
- 1))):
168 return "".join(pattern(self
.value
, self
.mask
, self
.value
.bit_length()))
170 def match(self
, key
):
171 return ((self
.value
& self
.mask
) == (key
& self
.mask
))
174 @_functools.total_ordering
175 @_dataclasses.dataclass(eq
=True, frozen
=True)
176 class IntegerOpcode(Opcode
):
177 def __init__(self
, value
):
178 if value
.startswith("0b"):
179 mask
= int(("1" * len(value
[2:])), 2)
183 value
= Opcode
.Value(value
)
184 mask
= Opcode
.Mask(mask
)
186 return super().__init
__(value
=value
, mask
=mask
)
189 @_functools.total_ordering
190 @_dataclasses.dataclass(eq
=True, frozen
=True)
191 class PatternOpcode(Opcode
):
192 def __init__(self
, pattern
):
193 if not isinstance(pattern
, str):
194 raise ValueError(pattern
)
196 (value
, mask
) = (0, 0)
197 for symbol
in pattern
:
198 if symbol
not in {"0", "1", "-"}:
199 raise ValueError(pattern
)
200 value |
= (symbol
== "1")
201 mask |
= (symbol
!= "-")
207 value
= Opcode
.Value(value
)
208 mask
= Opcode
.Mask(mask
)
210 return super().__init
__(value
=value
, mask
=mask
)
213 @_dataclasses.dataclass(eq
=True, frozen
=True)
215 class FlagsMeta(type):
230 class Flags(tuple, metaclass
=FlagsMeta
):
231 def __new__(cls
, flags
=frozenset()):
232 flags
= frozenset(flags
)
233 diff
= (flags
- frozenset(cls
))
235 raise ValueError(flags
)
236 return super().__new
__(cls
, sorted(flags
))
240 flags
: Flags
= Flags()
242 function
: _Function
= _Function
.NONE
243 intop
: _MicrOp
= _MicrOp
.OP_ILLEGAL
244 in1
: _In1Sel
= _In1Sel
.RA
245 in2
: _In2Sel
= _In2Sel
.NONE
246 in3
: _In3Sel
= _In3Sel
.NONE
247 out
: _OutSel
= _OutSel
.NONE
248 cr_in
: _CRInSel
= _CRInSel
.NONE
249 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
250 cr_out
: _CROutSel
= _CROutSel
.NONE
251 cry_in
: _CryIn
= _CryIn
.ZERO
252 ldst_len
: _LDSTLen
= _LDSTLen
.NONE
253 upd
: _LDSTMode
= _LDSTMode
.NONE
254 Rc
: _RCOE
= _RCOE
.NONE
255 form
: _Form
= _Form
.NONE
257 unofficial
: bool = False
261 "internal op": "intop",
265 "ldst len": "ldst_len",
267 "CONDITIONS": "conditions",
270 def __lt__(self
, other
):
271 if not isinstance(other
, self
.__class
__):
272 return NotImplemented
273 lhs
= (self
.opcode
, self
.comment
)
274 rhs
= (other
.opcode
, other
.comment
)
278 def CSV(cls
, record
, opcode_cls
):
279 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
280 typemap
["opcode"] = opcode_cls
282 if record
["CR in"] == "BA_BB":
283 record
["cr_in"] = "BA"
284 record
["cr_in2"] = "BB"
288 for flag
in frozenset(PPCRecord
.Flags
):
289 if bool(record
.pop(flag
, "")):
291 record
["flags"] = PPCRecord
.Flags(flags
)
293 return dataclass(cls
, record
,
294 keymap
=PPCRecord
.__KEYMAP
,
299 return frozenset(self
.comment
.split("=")[-1].split("/"))
302 class PPCMultiRecord(tuple):
303 def __getattr__(self
, attr
):
306 raise AttributeError(attr
)
307 return getattr(self
[0], attr
)
310 @_dataclasses.dataclass(eq
=True, frozen
=True)
312 class ExtraMap(tuple):
314 @_dataclasses.dataclass(eq
=True, frozen
=True)
316 regtype
: _SVExtraRegType
= _SVExtraRegType
.NONE
317 reg
: _SVExtraReg
= _SVExtraReg
.NONE
320 return f
"{self.regtype.value}:{self.reg.name}"
322 def __new__(cls
, value
="0"):
323 if isinstance(value
, str):
324 def transform(value
):
325 (regtype
, reg
) = value
.split(":")
326 regtype
= _SVExtraRegType(regtype
)
327 reg
= _SVExtraReg(reg
)
328 return cls
.Entry(regtype
=regtype
, reg
=reg
)
333 value
= map(transform
, value
.split(";"))
335 return super().__new
__(cls
, value
)
338 return repr(list(self
))
340 def __new__(cls
, value
=tuple()):
344 return super().__new
__(cls
, map(cls
.Extra
, value
))
347 return repr({index
:self
[index
] for index
in range(0, 4)})
350 ptype
: _SVPType
= _SVPType
.NONE
351 etype
: _SVEType
= _SVEType
.NONE
352 msrc
: _SVMaskSrc
= _SVMaskSrc
.NO
# MASK_SRC is active
353 in1
: _In1Sel
= _In1Sel
.NONE
354 in2
: _In2Sel
= _In2Sel
.NONE
355 in3
: _In3Sel
= _In3Sel
.NONE
356 out
: _OutSel
= _OutSel
.NONE
357 out2
: _OutSel
= _OutSel
.NONE
358 cr_in
: _CRInSel
= _CRInSel
.NONE
359 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
360 cr_out
: _CROutSel
= _CROutSel
.NONE
361 extra
: ExtraMap
= ExtraMap()
363 mode
: _SVMode
= _SVMode
.NORMAL
367 "CONDITIONS": "conditions",
376 def CSV(cls
, record
):
377 for key
in frozenset({
378 "in1", "in2", "in3", "CR in",
379 "out", "out2", "CR out",
385 if record
["CR in"] == "BA_BB":
386 record
["cr_in"] = "BA"
387 record
["cr_in2"] = "BB"
391 for idx
in range(0, 4):
392 extra
.append(record
.pop(f
"{idx}"))
394 record
["extra"] = cls
.ExtraMap(extra
)
396 return dataclass(cls
, record
, keymap
=cls
.__KEYMAP
)
398 @_functools.lru_cache(maxsize
=None)
399 def extra_idx(self
, key
):
407 if key
not in frozenset({
408 "in1", "in2", "in3", "cr_in", "cr_in2",
409 "out", "out2", "cr_out",
413 sel
= getattr(self
, key
)
414 if sel
is _CRInSel
.BA_BB
:
415 return _SVExtra
.Idx_1_2
416 reg
= _SVExtraReg(sel
)
417 if reg
is _SVExtraReg
.NONE
:
421 _SVExtraRegType
.SRC
: {},
422 _SVExtraRegType
.DST
: {},
424 for index
in range(0, 4):
425 for entry
in self
.extra
[index
]:
426 extra_map
[entry
.regtype
][entry
.reg
] = extra_idx
[index
]
428 for regtype
in (_SVExtraRegType
.SRC
, _SVExtraRegType
.DST
):
429 extra
= extra_map
[regtype
].get(reg
, _SVExtra
.NONE
)
430 if extra
is not _SVExtra
.NONE
:
435 extra_idx_in1
= property(_functools
.partial(extra_idx
, key
="in1"))
436 extra_idx_in2
= property(_functools
.partial(extra_idx
, key
="in2"))
437 extra_idx_in3
= property(_functools
.partial(extra_idx
, key
="in3"))
438 extra_idx_out
= property(_functools
.partial(extra_idx
, key
="out"))
439 extra_idx_out2
= property(_functools
.partial(extra_idx
, key
="out2"))
440 extra_idx_cr_in
= property(_functools
.partial(extra_idx
, key
="cr_in"))
441 extra_idx_cr_in2
= property(_functools
.partial(extra_idx
, key
="cr_in2"))
442 extra_idx_cr_out
= property(_functools
.partial(extra_idx
, key
="cr_out"))
444 @_functools.lru_cache(maxsize
=None)
445 def extra_reg(self
, key
):
446 return _SVExtraReg(getattr(self
, key
))
448 extra_reg_in1
= property(_functools
.partial(extra_reg
, key
="in1"))
449 extra_reg_in2
= property(_functools
.partial(extra_reg
, key
="in2"))
450 extra_reg_in3
= property(_functools
.partial(extra_reg
, key
="in3"))
451 extra_reg_out
= property(_functools
.partial(extra_reg
, key
="out"))
452 extra_reg_out2
= property(_functools
.partial(extra_reg
, key
="out2"))
453 extra_reg_cr_in
= property(_functools
.partial(extra_reg
, key
="cr_in"))
454 extra_reg_cr_in2
= property(_functools
.partial(extra_reg
, key
="cr_in2"))
455 extra_reg_cr_out
= property(_functools
.partial(extra_reg
, key
="cr_out"))
460 for idx
in range(0, 4):
461 for entry
in self
.extra
[idx
]:
462 if entry
.regtype
is _SVExtraRegType
.DST
:
463 if extra
is not None:
464 raise ValueError(self
.svp64
)
468 if _RegType(extra
.reg
) not in (_RegType
.CR_3BIT
, _RegType
.CR_5BIT
):
469 raise ValueError(self
.svp64
)
474 def extra_CR_3bit(self
):
475 return (_RegType(self
.extra_CR
.reg
) is _RegType
.CR_3BIT
)
479 def __init__(self
, value
=(0, 32)):
480 if isinstance(value
, str):
481 (start
, end
) = map(int, value
.split(":"))
484 if start
< 0 or end
< 0 or start
>= end
:
485 raise ValueError(value
)
490 return super().__init
__()
493 return (self
.__end
- self
.__start
+ 1)
496 return f
"[{self.__start}:{self.__end}]"
499 yield from range(self
.start
, (self
.end
+ 1))
501 def __reversed__(self
):
502 return tuple(reversed(tuple(self
)))
513 @_dataclasses.dataclass(eq
=True, frozen
=True)
515 class Mode(_enum
.Enum
):
516 INTEGER
= _enum
.auto()
517 PATTERN
= _enum
.auto()
520 def _missing_(cls
, value
):
521 if isinstance(value
, str):
522 return cls
[value
.upper()]
523 return super()._missing
_(value
)
526 def __new__(cls
, value
=None):
527 if isinstance(value
, str):
528 if value
.upper() == "NONE":
531 value
= int(value
, 0)
535 return super().__new
__(cls
, value
)
541 return (bin(self
) if self
else "None")
547 opcode
: IntegerOpcode
= None
548 priority
: Priority
= Priority
.NORMAL
550 def __lt__(self
, other
):
551 if not isinstance(other
, self
.__class
__):
552 return NotImplemented
553 return (self
.priority
< other
.priority
)
556 def CSV(cls
, record
):
557 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
558 if record
["opcode"] == "NONE":
559 typemap
["opcode"] = lambda _
: None
561 return dataclass(cls
, record
, typemap
=typemap
)
565 def __init__(self
, items
):
566 if isinstance(items
, dict):
567 items
= items
.items()
570 (name
, bitrange
) = item
571 return (name
, tuple(bitrange
.values()))
573 self
.__mapping
= dict(map(transform
, items
))
575 return super().__init
__()
578 return repr(self
.__mapping
)
581 yield from self
.__mapping
.items()
583 def __contains__(self
, key
):
584 return self
.__mapping
.__contains
__(key
)
586 def __getitem__(self
, key
):
587 return self
.__mapping
.get(key
, None)
602 def __init__(self
, insn
, operands
):
604 "b": {"target_addr": TargetAddrOperandLI
},
605 "ba": {"target_addr": TargetAddrOperandLI
},
606 "bl": {"target_addr": TargetAddrOperandLI
},
607 "bla": {"target_addr": TargetAddrOperandLI
},
608 "bc": {"target_addr": TargetAddrOperandBD
},
609 "bca": {"target_addr": TargetAddrOperandBD
},
610 "bcl": {"target_addr": TargetAddrOperandBD
},
611 "bcla": {"target_addr": TargetAddrOperandBD
},
612 "addpcis": {"D": DOperandDX
},
613 "fishmv": {"D": DOperandDX
},
614 "fmvis": {"D": DOperandDX
},
616 # FIXME: these instructions are broken according to the specs.
617 # The operands in the assembly syntax are FRT,FRA,FRC,FRB.
618 # The real assembly order, however, is FRT,FRA,FRB,FRC.
619 # The legacy assembler placed operands in syntax order.
620 "ffmadds": {"FRB": FMAOperandFRB
, "FRC": FMAOperandFRC
},
621 "ffmadds.": {"FRB": FMAOperandFRB
, "FRC": FMAOperandFRC
},
622 "fdmadds": {"FRB": FMAOperandFRB
, "FRC": FMAOperandFRC
},
623 "fdmadds.": {"FRB": FMAOperandFRB
, "FRC": FMAOperandFRC
},
626 "SVi": NonZeroOperand
,
627 "SVd": NonZeroOperand
,
628 "SVxd": NonZeroOperand
,
629 "SVyd": NonZeroOperand
,
630 "SVzd": NonZeroOperand
,
632 "D": SignedImmediateOperand
,
636 "SIM": SignedOperand
,
637 "SVD": SignedOperand
,
638 "SVDS": SignedOperand
,
639 "RSp": GPRPairOperand
,
640 "RTp": GPRPairOperand
,
641 "FRAp": FPRPairOperand
,
642 "FRBp": FPRPairOperand
,
643 "FRSp": FPRPairOperand
,
644 "FRTp": FPRPairOperand
,
646 custom_immediates
= {
652 for operand
in operands
:
656 (name
, value
) = operand
.split("=")
657 mapping
[name
] = (StaticOperand
, {
663 if name
.endswith(")"):
664 name
= name
.replace("(", " ").replace(")", "")
665 (imm_name
, _
, name
) = name
.partition(" ")
669 if imm_name
is not None:
670 imm_cls
= custom_immediates
.get(imm_name
, ImmediateOperand
)
672 if insn
in custom_insns
and name
in custom_insns
[insn
]:
673 cls
= custom_insns
[insn
][name
]
674 elif name
in custom_fields
:
675 cls
= custom_fields
[name
]
676 elif name
in _SVExtraReg
.__members
__:
677 reg
= _SVExtraReg
[name
]
678 if reg
in self
.__class
__.__GPR
_PAIRS
:
680 elif reg
in self
.__class
__.__FPR
_PAIRS
:
683 regtype
= _RegType
[name
]
684 if regtype
is _RegType
.GPR
:
686 elif regtype
is _RegType
.FPR
:
688 elif regtype
is _RegType
.CR_3BIT
:
690 elif regtype
is _RegType
.CR_5BIT
:
693 if imm_name
is not None:
694 mapping
[imm_name
] = (imm_cls
, {"name": imm_name
})
695 mapping
[name
] = (cls
, {"name": name
})
699 for (name
, (cls
, kwargs
)) in mapping
.items():
700 kwargs
= dict(kwargs
)
701 kwargs
["name"] = name
702 if issubclass(cls
, StaticOperand
):
703 static
.append((cls
, kwargs
))
704 elif issubclass(cls
, DynamicOperand
):
705 dynamic
.append((cls
, kwargs
))
707 raise ValueError(name
)
709 self
.__mapping
= mapping
710 self
.__static
= tuple(static
)
711 self
.__dynamic
= tuple(dynamic
)
713 return super().__init
__()
716 for (_
, items
) in self
.__mapping
.items():
717 (cls
, kwargs
) = items
721 return self
.__mapping
.__repr
__()
723 def __contains__(self
, key
):
724 return self
.__mapping
.__contains
__(key
)
726 def __getitem__(self
, key
):
727 return self
.__mapping
.__getitem
__(key
)
735 return self
.__dynamic
738 class Arguments(tuple):
739 def __new__(cls
, record
, arguments
, operands
):
740 operands
= iter(tuple(operands
))
741 arguments
= iter(tuple(arguments
))
746 operand
= next(operands
)
747 except StopIteration:
751 argument
= next(arguments
)
752 except StopIteration:
753 raise ValueError("operands count mismatch")
755 if isinstance(operand
, ImmediateOperand
):
756 argument
= argument
.replace("(", " ").replace(")", "")
757 (imm_argument
, _
, argument
) = argument
.partition(" ")
759 (imm_operand
, operand
) = (operand
, next(operands
))
760 except StopIteration:
761 raise ValueError("operands count mismatch")
762 items
.append((imm_argument
, imm_operand
))
763 items
.append((argument
, operand
))
767 except StopIteration:
770 raise ValueError("operands count mismatch")
772 return super().__new
__(cls
, items
)
776 def __init__(self
, iterable
):
777 self
.__pcode
= tuple(iterable
)
778 return super().__init
__()
781 yield from self
.__pcode
784 return self
.__pcode
.__repr
__()
787 @_dataclasses.dataclass(eq
=True, frozen
=True)
788 class MarkdownRecord
:
793 @_functools.total_ordering
794 @_dataclasses.dataclass(eq
=True, frozen
=True)
801 svp64
: SVP64Record
= None
803 def __lt__(self
, other
):
804 if not isinstance(other
, Record
):
805 return NotImplemented
806 lhs
= (min(self
.opcodes
), self
.name
)
807 rhs
= (min(other
.opcodes
), other
.name
)
812 return (self
.static_operands
+ self
.dynamic_operands
)
815 def static_operands(self
):
817 operands
.append(POStaticOperand(record
=self
, value
=self
.PO
))
819 operands
.append(XOStaticOperand(
821 value
=ppc
.opcode
.value
,
822 span
=self
.section
.bitsel
,
824 for (cls
, kwargs
) in self
.mdwn
.operands
.static
:
825 operands
.append(cls(record
=self
, **kwargs
))
826 return tuple(operands
)
829 def dynamic_operands(self
):
831 for (cls
, kwargs
) in self
.mdwn
.operands
.dynamic
:
832 operands
.append(cls(record
=self
, **kwargs
))
833 return tuple(operands
)
838 return int("".join(str(int(mapping
[bit
])) for bit
in sorted(mapping
)), 2)
840 def PO_XO(value
, mask
, opcode
, bits
):
843 for (src
, dst
) in enumerate(reversed(bits
)):
844 value
[dst
] = ((opcode
.value
& (1 << src
)) != 0)
845 mask
[dst
] = ((opcode
.mask
& (1 << src
)) != 0)
848 def PO(value
, mask
, opcode
, bits
):
849 return PO_XO(value
=value
, mask
=mask
, opcode
=opcode
, bits
=bits
)
851 def XO(value
, mask
, opcode
, bits
):
852 (value
, mask
) = PO_XO(value
=value
, mask
=mask
, opcode
=opcode
, bits
=bits
)
853 for (op_cls
, op_kwargs
) in self
.mdwn
.operands
.static
:
854 operand
= op_cls(record
=self
, **op_kwargs
)
855 for (src
, dst
) in enumerate(reversed(operand
.span
)):
856 value
[dst
] = ((operand
.value
& (1 << src
)) != 0)
861 value
= {bit
:False for bit
in range(32)}
862 mask
= {bit
:False for bit
in range(32)}
863 if self
.section
.opcode
is not None:
864 (value
, mask
) = PO(value
=value
, mask
=mask
,
865 opcode
=self
.section
.opcode
, bits
=range(0, 6))
867 pairs
.append(XO(value
=value
, mask
=mask
,
868 opcode
=ppc
.opcode
, bits
=self
.section
.bitsel
))
871 for (value
, mask
) in pairs
:
872 value
= Opcode
.Value(binary(value
))
873 mask
= Opcode
.Mask(binary(mask
))
874 result
.append(Opcode(value
=value
, mask
=mask
))
880 opcode
= self
.section
.opcode
882 opcode
= self
.ppc
[0].opcode
883 if isinstance(opcode
, PatternOpcode
):
884 value
= int(opcode
.value
)
885 bits
= opcode
.value
.bit_length()
886 return int(_SelectableInt(value
=value
, bits
=bits
)[0:6])
888 return int(opcode
.value
)
892 return tuple(ppc
.opcode
for ppc
in self
.ppc
)
894 def match(self
, key
):
895 for opcode
in self
.opcodes
:
896 if opcode
.match(key
):
903 return self
.svp64
.mode
923 if self
.svp64
is None:
929 return self
.ppc
.cr_in
933 return self
.ppc
.cr_in2
937 return self
.ppc
.cr_out
939 ptype
= property(lambda self
: self
.svp64
.ptype
)
940 etype
= property(lambda self
: self
.svp64
.etype
)
942 def extra_idx(self
, key
):
943 return self
.svp64
.extra_idx(key
)
945 extra_idx_in1
= property(lambda self
: self
.svp64
.extra_idx_in1
)
946 extra_idx_in2
= property(lambda self
: self
.svp64
.extra_idx_in2
)
947 extra_idx_in3
= property(lambda self
: self
.svp64
.extra_idx_in3
)
948 extra_idx_out
= property(lambda self
: self
.svp64
.extra_idx_out
)
949 extra_idx_out2
= property(lambda self
: self
.svp64
.extra_idx_out2
)
950 extra_idx_cr_in
= property(lambda self
: self
.svp64
.extra_idx_cr_in
)
951 extra_idx_cr_in2
= property(lambda self
: self
.svp64
.extra_idx_cr_in2
)
952 extra_idx_cr_out
= property(lambda self
: self
.svp64
.extra_idx_cr_out
)
954 def __contains__(self
, key
):
955 return self
.mdwn
.operands
.__contains
__(key
)
957 def __getitem__(self
, key
):
958 (cls
, kwargs
) = self
.mdwn
.operands
.__getitem
__(key
)
959 return cls(record
=self
, **kwargs
)
965 return self
["Rc"].value
969 def __init__(self
, record
, name
):
970 self
.__record
= record
974 yield ("record", self
.record
)
975 yield ("name", self
.__name
)
978 return f
"{self.__class__.__name__}({self.name})"
990 return self
.record
.fields
[self
.name
]
992 def assemble(self
, insn
):
993 raise NotImplementedError()
995 def disassemble(self
, insn
,
996 style
=Style
.NORMAL
, indent
=""):
997 raise NotImplementedError()
1000 class DynamicOperand(Operand
):
1001 def assemble(self
, insn
, value
):
1003 if isinstance(value
, str):
1004 value
= int(value
, 0)
1006 raise ValueError("signed operands not allowed")
1009 def disassemble(self
, insn
,
1010 style
=Style
.NORMAL
, indent
=""):
1014 if style
>= Style
.VERBOSE
:
1015 span
= map(str, span
)
1016 yield f
"{indent}{self.name}"
1017 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1018 yield f
"{indent}{indent}{', '.join(span)}"
1020 yield str(int(value
))
1023 class SignedOperand(DynamicOperand
):
1024 def assemble(self
, insn
, value
):
1025 if isinstance(value
, str):
1026 value
= int(value
, 0)
1027 return super().assemble(value
=value
, insn
=insn
)
1029 def assemble(self
, insn
, value
):
1031 if isinstance(value
, str):
1032 value
= int(value
, 0)
1035 def disassemble(self
, insn
,
1036 style
=Style
.NORMAL
, indent
=""):
1038 value
= insn
[span
].to_signed_int()
1039 sign
= "-" if (value
< 0) else ""
1042 if style
>= Style
.VERBOSE
:
1043 span
= map(str, span
)
1044 yield f
"{indent}{self.name}"
1045 yield f
"{indent}{indent}{sign}{value}"
1046 yield f
"{indent}{indent}{', '.join(span)}"
1048 yield f
"{sign}{value}"
1051 class StaticOperand(Operand
):
1052 def __init__(self
, record
, name
, value
):
1053 self
.__value
= value
1054 return super().__init
__(record
=record
, name
=name
)
1057 yield ("value", self
.__value
)
1058 yield from super().__iter
__()
1061 return f
"{self.__class__.__name__}({self.name}, value={self.value})"
1067 def assemble(self
, insn
):
1068 insn
[self
.span
] = self
.value
1070 def disassemble(self
, insn
,
1071 style
=Style
.NORMAL
, indent
=""):
1075 if style
>= Style
.VERBOSE
:
1076 span
= map(str, span
)
1077 yield f
"{indent}{self.name}"
1078 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1079 yield f
"{indent}{indent}{', '.join(span)}"
1081 yield str(int(value
))
1084 class SpanStaticOperand(StaticOperand
):
1085 def __init__(self
, record
, name
, value
, span
):
1086 self
.__span
= tuple(span
)
1087 return super().__init
__(record
=record
, name
=name
, value
=value
)
1090 yield ("span", self
.__span
)
1091 yield from super().__iter
__()
1098 class POStaticOperand(SpanStaticOperand
):
1099 def __init__(self
, record
, value
):
1100 return super().__init
__(record
=record
, name
="PO", value
=value
, span
=range(0, 6))
1103 for (key
, value
) in super().__iter
__():
1104 if key
not in {"name", "span"}:
1108 class XOStaticOperand(SpanStaticOperand
):
1109 def __init__(self
, record
, value
, span
):
1110 if record
.name
== "ffadds":
1113 bits
= record
.section
.bitsel
1114 value
= _SelectableInt(value
=value
, bits
=len(bits
))
1115 span
= dict(zip(bits
, range(len(bits
))))
1116 span_rev
= {value
:key
for (key
, value
) in span
.items()}
1118 # This part is tricky: we cannot use record.operands,
1119 # as this code is called by record.static_operands method.
1120 for (cls
, kwargs
) in record
.mdwn
.operands
:
1121 operand
= cls(record
=record
, **kwargs
)
1122 for idx
in operand
.span
:
1123 rev
= span
.pop(idx
, None)
1125 span_rev
.pop(rev
, None)
1127 value
= int(_selectconcat(*(value
[bit
] for bit
in span
.values())))
1128 span
= tuple(span
.keys())
1130 return super().__init
__(record
=record
, name
="XO", value
=value
, span
=span
)
1133 for (key
, value
) in super().__iter
__():
1134 if key
not in {"name"}:
1138 class ImmediateOperand(DynamicOperand
):
1142 class SignedImmediateOperand(SignedOperand
, ImmediateOperand
):
1146 class NonZeroOperand(DynamicOperand
):
1147 def assemble(self
, insn
, value
):
1148 if isinstance(value
, str):
1149 value
= int(value
, 0)
1150 if not isinstance(value
, int):
1151 raise ValueError("non-integer operand")
1153 return super().assemble(value
=value
, insn
=insn
)
1155 def disassemble(self
, insn
,
1156 style
=Style
.NORMAL
, indent
=""):
1160 if style
>= Style
.VERBOSE
:
1161 span
= map(str, span
)
1162 yield f
"{indent}{self.name}"
1163 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1164 yield f
"{indent}{indent}{', '.join(span)}"
1166 yield str(int(value
) + 1)
1169 class ExtendableOperand(DynamicOperand
):
1170 def sv_spec_enter(self
, value
, span
):
1171 return (value
, span
)
1173 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1174 return (value
, span
)
1176 def spec(self
, insn
):
1180 span
= tuple(map(str, span
))
1182 if isinstance(insn
, SVP64Instruction
):
1183 (origin_value
, origin_span
) = (value
, span
)
1184 (value
, span
) = self
.sv_spec_enter(value
=value
, span
=span
)
1186 extra_idx
= self
.extra_idx
1187 if extra_idx
is _SVExtra
.NONE
:
1188 return (vector
, value
, span
)
1190 if self
.record
.etype
is _SVEType
.EXTRA3
:
1191 spec
= insn
.prefix
.rm
.extra3
[extra_idx
]
1192 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1193 spec
= insn
.prefix
.rm
.extra2
[extra_idx
]
1195 raise ValueError(self
.record
.etype
)
1198 vector
= bool(spec
[0])
1199 spec_span
= spec
.__class
__
1200 if self
.record
.etype
is _SVEType
.EXTRA3
:
1201 spec_span
= tuple(map(str, spec_span
[1, 2]))
1203 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1204 spec_span
= tuple(map(str, spec_span
[1,]))
1205 spec
= _SelectableInt(value
=spec
[1].value
, bits
=2)
1208 spec_span
= (spec_span
+ ("{0}",))
1210 spec_span
= (("{0}",) + spec_span
)
1212 raise ValueError(self
.record
.etype
)
1214 vector_shift
= (2 + (5 - value
.bits
))
1215 scalar_shift
= value
.bits
1216 spec_shift
= (5 - value
.bits
)
1218 bits
= (len(span
) + len(spec_span
))
1219 value
= _SelectableInt(value
=value
.value
, bits
=bits
)
1220 spec
= _SelectableInt(value
=spec
.value
, bits
=bits
)
1222 value
= ((value
<< vector_shift
) |
(spec
<< spec_shift
))
1223 span
= (span
+ spec_span
+ ((spec_shift
* ("{0}",))))
1225 value
= ((spec
<< scalar_shift
) | value
)
1226 span
= ((spec_shift
* ("{0}",)) + spec_span
+ span
)
1228 (value
, span
) = self
.sv_spec_leave(value
=value
, span
=span
,
1229 origin_value
=origin_value
, origin_span
=origin_span
)
1231 return (vector
, value
, span
)
1234 def extra_reg(self
):
1235 return _SVExtraReg(self
.name
)
1238 def extra_idx(self
):
1240 _SVExtraReg
.RSp
: _SVExtraReg
.RS
,
1241 _SVExtraReg
.RTp
: _SVExtraReg
.RT
,
1242 _SVExtraReg
.FRAp
: _SVExtraReg
.FRA
,
1243 _SVExtraReg
.FRBp
: _SVExtraReg
.FRB
,
1244 _SVExtraReg
.FRSp
: _SVExtraReg
.FRS
,
1245 _SVExtraReg
.FRTp
: _SVExtraReg
.FRT
,
1248 for key
in frozenset({
1249 "in1", "in2", "in3", "cr_in", "cr_in2",
1250 "out", "out2", "cr_out",
1252 extra_reg
= self
.record
.svp64
.extra_reg(key
=key
)
1253 if pairs
.get(extra_reg
, extra_reg
) is pairs
.get(self
.extra_reg
, self
.extra_reg
):
1254 return self
.record
.extra_idx(key
=key
)
1256 return _SVExtra
.NONE
1258 def remap(self
, value
, vector
):
1259 raise NotImplementedError()
1261 def assemble(self
, value
, insn
, prefix
):
1264 if isinstance(value
, str):
1265 value
= value
.lower()
1266 if value
.startswith("%"):
1268 if value
.startswith("*"):
1269 if not isinstance(insn
, SVP64Instruction
):
1270 raise ValueError(value
)
1273 if value
.startswith(prefix
):
1274 value
= value
[len(prefix
):]
1275 value
= int(value
, 0)
1277 if isinstance(insn
, SVP64Instruction
):
1278 (value
, extra
) = self
.remap(value
=value
, vector
=vector
)
1280 extra_idx
= self
.extra_idx
1281 if extra_idx
is _SVExtra
.NONE
:
1282 raise ValueError(self
.record
)
1284 if self
.record
.etype
is _SVEType
.EXTRA3
:
1285 insn
.prefix
.rm
.extra3
[extra_idx
] = extra
1286 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1287 insn
.prefix
.rm
.extra2
[extra_idx
] = extra
1289 raise ValueError(self
.record
.etype
)
1291 return super().assemble(value
=value
, insn
=insn
)
1293 def disassemble(self
, insn
,
1294 style
=Style
.NORMAL
, prefix
="", indent
=""):
1295 (vector
, value
, span
) = self
.spec(insn
=insn
)
1297 if style
>= Style
.VERBOSE
:
1298 mode
= "vector" if vector
else "scalar"
1299 yield f
"{indent}{self.name} ({mode})"
1300 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1301 yield f
"{indent}{indent}{', '.join(span)}"
1302 if isinstance(insn
, SVP64Instruction
):
1303 extra_idx
= self
.extra_idx
1304 if self
.record
.etype
is _SVEType
.NONE
:
1305 yield f
"{indent}{indent}extra[none]"
1307 etype
= repr(self
.record
.etype
).lower()
1308 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1310 vector
= "*" if vector
else ""
1311 yield f
"{vector}{prefix}{int(value)}"
1314 class SimpleRegisterOperand(ExtendableOperand
):
1315 def remap(self
, value
, vector
):
1317 extra
= (value
& 0b11)
1318 value
= (value
>> 2)
1320 extra
= (value
>> 5)
1321 value
= (value
& 0b11111)
1323 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
1324 # (and shrink to a single bit if ok)
1325 if self
.record
.etype
is _SVEType
.EXTRA2
:
1327 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
1328 assert (extra
& 0b01) == 0, \
1329 ("vector field %s cannot fit into EXTRA2" % value
)
1330 extra
= (0b10 |
(extra
>> 1))
1332 # range is r0-r63 in increments of 1
1333 assert (extra
>> 1) == 0, \
1334 ("scalar GPR %d cannot fit into EXTRA2" % value
)
1336 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1338 # EXTRA3 vector bit needs marking
1341 raise ValueError(self
.record
.etype
)
1343 return (value
, extra
)
1346 class GPROperand(SimpleRegisterOperand
):
1347 def assemble(self
, insn
, value
):
1348 return super().assemble(value
=value
, insn
=insn
, prefix
="r")
1350 def disassemble(self
, insn
,
1351 style
=Style
.NORMAL
, indent
=""):
1352 prefix
= "" if (style
<= Style
.SHORT
) else "r"
1353 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1354 style
=style
, indent
=indent
)
1357 class GPRPairOperand(GPROperand
):
1361 class FPROperand(SimpleRegisterOperand
):
1362 def assemble(self
, insn
, value
):
1363 return super().assemble(value
=value
, insn
=insn
, prefix
="f")
1365 def disassemble(self
, insn
,
1366 style
=Style
.NORMAL
, indent
=""):
1367 prefix
= "" if (style
<= Style
.SHORT
) else "f"
1368 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1369 style
=style
, indent
=indent
)
1372 class RedirectedOperand(DynamicOperand
):
1373 def __init__(self
, record
, name
, target
):
1374 self
.__target
= target
1375 return super().__init
__(record
=record
, name
=name
)
1379 print(f
"{self.record.name}: {self.name} => {self.__target}", file=_sys
.stderr
)
1380 return self
.record
.fields
[self
.__target
]
1383 class FMAOperandFRB(RedirectedOperand
, FPROperand
):
1384 def __init__(self
, record
, name
):
1385 return super().__init
__(record
=record
, name
=name
, target
="FRC")
1388 class FMAOperandFRC(RedirectedOperand
, FPROperand
):
1389 def __init__(self
, record
, name
):
1390 return super().__init
__(record
=record
, name
=name
, target
="FRB")
1393 class FPRPairOperand(FPROperand
):
1397 class ConditionRegisterFieldOperand(ExtendableOperand
):
1398 def pattern(name_pattern
):
1399 (name
, pattern
) = name_pattern
1400 return (name
, _re
.compile(f
"^{pattern}$", _re
.S
))
1409 CR
= r
"(?:CR|cr)([0-9]+)"
1411 BIT
= rf
"({'|'.join(CONDS.keys())})"
1412 LBIT
= fr
"{BIT}\s*\+\s*" # BIT+
1413 RBIT
= fr
"\s*\+\s*{BIT}" # +BIT
1414 CRN
= fr
"{CR}\s*\*\s*{N}" # CR*N
1415 NCR
= fr
"{N}\s*\*\s*{CR}" # N*CR
1416 XCR
= fr
"{CR}\.{BIT}"
1417 PATTERNS
= tuple(map(pattern
, (
1422 ("BIT+CR", (LBIT
+ CR
)),
1423 ("CR+BIT", (CR
+ RBIT
)),
1424 ("BIT+CR*N", (LBIT
+ CRN
)),
1425 ("CR*N+BIT", (CRN
+ RBIT
)),
1426 ("BIT+N*CR", (LBIT
+ NCR
)),
1427 ("N*CR+BIT", (NCR
+ RBIT
)),
1430 def remap(self
, value
, vector
, regtype
):
1431 if regtype
is _RegType
.CR_5BIT
:
1432 subvalue
= (value
& 0b11)
1436 extra
= (value
& 0b1111)
1439 extra
= (value
>> 3)
1442 if self
.record
.etype
is _SVEType
.EXTRA2
:
1444 assert (extra
& 0b111) == 0, \
1445 "vector CR cannot fit into EXTRA2"
1446 extra
= (0b10 |
(extra
>> 3))
1448 assert (extra
>> 1) == 0, \
1449 "scalar CR cannot fit into EXTRA2"
1451 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1453 assert (extra
& 0b11) == 0, \
1454 "vector CR cannot fit into EXTRA3"
1455 extra
= (0b100 |
(extra
>> 2))
1457 assert (extra
>> 2) == 0, \
1458 "scalar CR cannot fit into EXTRA3"
1461 if regtype
is _RegType
.CR_5BIT
:
1462 value
= ((value
<< 2) | subvalue
)
1464 return (value
, extra
)
1466 def assemble(self
, insn
, value
):
1467 if isinstance(value
, str):
1470 if value
.startswith("*"):
1471 if not isinstance(insn
, SVP64Instruction
):
1472 raise ValueError(value
)
1476 for (name
, pattern
) in reversed(self
.__class
__.PATTERNS
):
1477 match
= pattern
.match(value
)
1478 if match
is not None:
1479 keys
= name
.replace("+", "_").replace("*", "_").split("_")
1480 values
= match
.groups()
1481 match
= dict(zip(keys
, values
))
1482 CR
= int(match
["CR"])
1486 N
= int(match
.get("N", "1"))
1487 BIT
= self
.__class
__.CONDS
[match
.get("BIT", "lt")]
1488 value
= ((CR
* N
) + BIT
)
1495 return super().assemble(value
=value
, insn
=insn
, prefix
="cr")
1497 def disassemble(self
, insn
,
1498 style
=Style
.NORMAL
, prefix
="", indent
=""):
1499 (vector
, value
, span
) = self
.spec(insn
=insn
)
1501 if style
>= Style
.VERBOSE
:
1502 mode
= "vector" if vector
else "scalar"
1503 yield f
"{indent}{self.name} ({mode})"
1504 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1505 yield f
"{indent}{indent}{', '.join(span)}"
1506 if isinstance(insn
, SVP64Instruction
):
1507 extra_idx
= self
.extra_idx
1508 if self
.record
.etype
is _SVEType
.NONE
:
1509 yield f
"{indent}{indent}extra[none]"
1511 etype
= repr(self
.record
.etype
).lower()
1512 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1514 vector
= "*" if vector
else ""
1515 CR
= int(value
>> 2)
1517 cond
= ("lt", "gt", "eq", "so")[CC
]
1518 if style
>= Style
.NORMAL
:
1520 if isinstance(insn
, SVP64Instruction
):
1521 yield f
"{vector}cr{CR}.{cond}"
1523 yield f
"4*cr{CR}+{cond}"
1527 yield f
"{vector}{prefix}{int(value)}"
1530 class CR3Operand(ConditionRegisterFieldOperand
):
1531 def remap(self
, value
, vector
):
1532 return super().remap(value
=value
, vector
=vector
,
1533 regtype
=_RegType
.CR_3BIT
)
1536 class CR5Operand(ConditionRegisterFieldOperand
):
1537 def remap(self
, value
, vector
):
1538 return super().remap(value
=value
, vector
=vector
,
1539 regtype
=_RegType
.CR_5BIT
)
1541 def sv_spec_enter(self
, value
, span
):
1542 value
= _SelectableInt(value
=(value
.value
>> 2), bits
=3)
1543 return (value
, span
)
1545 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1546 value
= _selectconcat(value
, origin_value
[3:5])
1548 return (value
, span
)
1551 class EXTSOperand(SignedOperand
):
1552 field
: str # real name to report
1553 nz
: int = 0 # number of zeros
1554 fmt
: str = "d" # integer formatter
1556 def __init__(self
, record
, name
, field
, nz
=0, fmt
="d"):
1557 self
.__field
= field
1560 return super().__init
__(record
=record
, name
=name
)
1576 return self
.record
.fields
[self
.field
]
1578 def assemble(self
, insn
, value
):
1580 if isinstance(value
, str):
1581 value
= int(value
, 0)
1582 insn
[span
] = (value
>> self
.nz
)
1584 def disassemble(self
, insn
,
1585 style
=Style
.NORMAL
, indent
=""):
1587 value
= insn
[span
].to_signed_int()
1588 sign
= "-" if (value
< 0) else ""
1589 value
= (abs(value
) << self
.nz
)
1591 if style
>= Style
.VERBOSE
:
1592 span
= (tuple(map(str, span
)) + (("{0}",) * self
.nz
))
1593 zeros
= ("0" * self
.nz
)
1594 hint
= f
"{self.name} = EXTS({self.field} || {zeros})"
1595 yield f
"{indent * 1}{hint}"
1596 yield f
"{indent * 2}{self.field}"
1597 yield f
"{indent * 3}{sign}{value:{self.fmt}}"
1598 yield f
"{indent * 3}{', '.join(span)}"
1600 yield f
"{sign}{value:{self.fmt}}"
1603 class TargetAddrOperand(EXTSOperand
):
1604 def __init__(self
, record
, name
, field
):
1605 return super().__init
__(record
=record
, name
=name
, field
=field
, nz
=2, fmt
="#x")
1608 class TargetAddrOperandLI(TargetAddrOperand
):
1609 def __init__(self
, record
, name
):
1610 return super().__init
__(record
=record
, name
=name
, field
="LI")
1613 class TargetAddrOperandBD(TargetAddrOperand
):
1614 def __init__(self
, record
, name
):
1615 return super().__init
__(record
=record
, name
=name
, field
="BD")
1618 class EXTSOperandDS(EXTSOperand
, ImmediateOperand
):
1619 def __init__(self
, record
, name
):
1620 return super().__init
__(record
=record
, name
=name
, field
="DS", nz
=2)
1623 class EXTSOperandDQ(EXTSOperand
, ImmediateOperand
):
1624 def __init__(self
, record
, name
):
1625 return super().__init
__(record
=record
, name
=name
, field
="DQ", nz
=4)
1628 class DOperandDX(SignedOperand
):
1631 cls
= lambda name
: DynamicOperand(record
=self
.record
, name
=name
)
1632 operands
= map(cls
, ("d0", "d1", "d2"))
1633 spans
= map(lambda operand
: operand
.span
, operands
)
1634 return sum(spans
, tuple())
1636 def disassemble(self
, insn
,
1637 style
=Style
.NORMAL
, indent
=""):
1639 value
= insn
[span
].to_signed_int()
1640 sign
= "-" if (value
< 0) else ""
1643 if style
>= Style
.VERBOSE
:
1650 for (subname
, subspan
) in mapping
.items():
1651 operand
= DynamicOperand(name
=subname
)
1653 span
= map(str, span
)
1654 yield f
"{indent}{indent}{operand.name} = D{subspan}"
1655 yield f
"{indent}{indent}{indent}{sign}{value}"
1656 yield f
"{indent}{indent}{indent}{', '.join(span)}"
1658 yield f
"{sign}{value}"
1661 class Instruction(_Mapping
):
1663 def integer(cls
, value
=0, bits
=None, byteorder
="little"):
1664 if isinstance(value
, (int, bytes
)) and not isinstance(bits
, int):
1665 raise ValueError(bits
)
1667 if isinstance(value
, bytes
):
1668 if ((len(value
) * 8) != bits
):
1669 raise ValueError(f
"bit length mismatch")
1670 value
= int.from_bytes(value
, byteorder
=byteorder
)
1672 if isinstance(value
, int):
1673 value
= _SelectableInt(value
=value
, bits
=bits
)
1674 elif isinstance(value
, Instruction
):
1675 value
= value
.storage
1677 if not isinstance(value
, _SelectableInt
):
1678 raise ValueError(value
)
1681 if len(value
) != bits
:
1682 raise ValueError(value
)
1684 value
= _SelectableInt(value
=value
, bits
=bits
)
1686 return cls(storage
=value
)
1689 return hash(int(self
))
1691 def __getitem__(self
, key
):
1692 return self
.storage
.__getitem
__(key
)
1694 def __setitem__(self
, key
, value
):
1695 return self
.storage
.__setitem
__(key
, value
)
1697 def bytes(self
, byteorder
="little"):
1698 nr_bytes
= (len(self
.__class
__) // 8)
1699 return int(self
).to_bytes(nr_bytes
, byteorder
=byteorder
)
1702 def record(cls
, db
, entry
):
1705 raise KeyError(entry
)
1709 def operands(cls
, record
):
1710 yield from record
.operands
1713 def static_operands(cls
, record
):
1714 return filter(lambda operand
: isinstance(operand
, StaticOperand
),
1715 cls
.operands(record
=record
))
1718 def dynamic_operands(cls
, record
):
1719 return filter(lambda operand
: isinstance(operand
, DynamicOperand
),
1720 cls
.operands(record
=record
))
1722 def spec(self
, record
, prefix
):
1723 dynamic_operands
= tuple(map(_operator
.itemgetter(0),
1724 self
.spec_dynamic_operands(record
=record
)))
1726 static_operands
= []
1727 for (name
, value
) in self
.spec_static_operands(record
=record
):
1728 static_operands
.append(f
"{name}={value}")
1731 if dynamic_operands
:
1733 operands
+= ",".join(dynamic_operands
)
1736 operands
+= " ".join(static_operands
)
1738 return f
"{prefix}{record.name}{operands}"
1740 def spec_static_operands(self
, record
):
1741 for operand
in self
.static_operands(record
=record
):
1742 if not isinstance(operand
, (POStaticOperand
, XOStaticOperand
)):
1743 yield (operand
.name
, operand
.value
)
1745 def spec_dynamic_operands(self
, record
, style
=Style
.NORMAL
):
1749 for operand
in self
.dynamic_operands(record
=record
):
1751 value
= " ".join(operand
.disassemble(insn
=self
,
1752 style
=min(style
, Style
.NORMAL
)))
1754 name
= f
"{imm_name}({name})"
1755 value
= f
"{imm_value}({value})"
1757 if isinstance(operand
, ImmediateOperand
):
1765 def assemble(cls
, record
, arguments
=None):
1766 if arguments
is None:
1769 insn
= cls
.integer(value
=0)
1771 for operand
in cls
.static_operands(record
=record
):
1772 operand
.assemble(insn
=insn
)
1774 arguments
= Arguments(record
=record
,
1775 arguments
=arguments
, operands
=cls
.dynamic_operands(record
=record
))
1776 for (value
, operand
) in arguments
:
1777 operand
.assemble(insn
=insn
, value
=value
)
1781 def disassemble(self
, record
,
1783 style
=Style
.NORMAL
):
1784 raise NotImplementedError()
1787 class WordInstruction(Instruction
):
1788 _
: _Field
= range(0, 32)
1789 PO
: _Field
= range(0, 6)
1792 def integer(cls
, value
, byteorder
="little"):
1793 return super().integer(bits
=32, value
=value
, byteorder
=byteorder
)
1798 for idx
in range(32):
1799 bit
= int(self
[idx
])
1801 return "".join(map(str, bits
))
1803 def disassemble(self
, record
,
1805 style
=Style
.NORMAL
):
1806 if style
<= Style
.SHORT
:
1809 blob
= self
.bytes(byteorder
=byteorder
)
1810 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
1814 yield f
"{blob}.long 0x{int(self):08x}"
1818 if style
is Style
.LEGACY
:
1820 for operand
in self
.dynamic_operands(record
=record
):
1821 if isinstance(operand
, (GPRPairOperand
, FPRPairOperand
)):
1824 if style
is Style
.LEGACY
and (paired
or record
.ppc
.unofficial
):
1825 yield f
"{blob}.long 0x{int(self):08x}"
1827 operands
= tuple(map(_operator
.itemgetter(1),
1828 self
.spec_dynamic_operands(record
=record
, style
=style
)))
1830 operands
= ",".join(operands
)
1831 yield f
"{blob}{record.name} {operands}"
1833 yield f
"{blob}{record.name}"
1835 if style
>= Style
.VERBOSE
:
1837 binary
= self
.binary
1838 spec
= self
.spec(record
=record
, prefix
="")
1839 yield f
"{indent}spec"
1840 yield f
"{indent}{indent}{spec}"
1841 yield f
"{indent}pcode"
1842 for stmt
in record
.mdwn
.pcode
:
1843 yield f
"{indent}{indent}{stmt}"
1844 yield f
"{indent}binary"
1845 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
1846 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
1847 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
1848 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
1849 yield f
"{indent}opcodes"
1850 for opcode
in record
.opcodes
:
1851 yield f
"{indent}{indent}{opcode!r}"
1852 for operand
in self
.operands(record
=record
):
1853 yield from operand
.disassemble(insn
=self
,
1854 style
=style
, indent
=indent
)
1858 class PrefixedInstruction(Instruction
):
1859 class Prefix(WordInstruction
.remap(range(0, 32))):
1862 class Suffix(WordInstruction
.remap(range(32, 64))):
1865 _
: _Field
= range(64)
1871 def integer(cls
, value
, byteorder
="little"):
1872 return super().integer(bits
=64, value
=value
, byteorder
=byteorder
)
1875 def pair(cls
, prefix
=0, suffix
=0, byteorder
="little"):
1876 def transform(value
):
1877 return WordInstruction
.integer(value
=value
,
1878 byteorder
=byteorder
)[0:32]
1880 (prefix
, suffix
) = map(transform
, (prefix
, suffix
))
1881 value
= _selectconcat(prefix
, suffix
)
1883 return super().integer(bits
=64, value
=value
)
1886 class Mode(_Mapping
):
1887 _
: _Field
= range(0, 5)
1888 sel
: _Field
= (0, 1)
1891 class Extra(_Mapping
):
1892 _
: _Field
= range(0, 9)
1895 class Extra2(Extra
):
1896 idx0
: _Field
= range(0, 2)
1897 idx1
: _Field
= range(2, 4)
1898 idx2
: _Field
= range(4, 6)
1899 idx3
: _Field
= range(6, 8)
1901 def __getitem__(self
, key
):
1907 _SVExtra
.Idx0
: self
.idx0
,
1908 _SVExtra
.Idx1
: self
.idx1
,
1909 _SVExtra
.Idx2
: self
.idx2
,
1910 _SVExtra
.Idx3
: self
.idx3
,
1913 def __setitem__(self
, key
, value
):
1914 self
[key
].assign(value
)
1917 class Extra3(Extra
):
1918 idx0
: _Field
= range(0, 3)
1919 idx1
: _Field
= range(3, 6)
1920 idx2
: _Field
= range(6, 9)
1922 def __getitem__(self
, key
):
1927 _SVExtra
.Idx0
: self
.idx0
,
1928 _SVExtra
.Idx1
: self
.idx1
,
1929 _SVExtra
.Idx2
: self
.idx2
,
1932 def __setitem__(self
, key
, value
):
1933 self
[key
].assign(value
)
1936 class BaseRM(_Mapping
):
1937 _
: _Field
= range(24)
1938 mmode
: _Field
= (0,)
1939 mask
: _Field
= range(1, 4)
1940 elwidth
: _Field
= range(4, 6)
1941 ewsrc
: _Field
= range(6, 8)
1942 subvl
: _Field
= range(8, 10)
1943 mode
: Mode
.remap(range(19, 24))
1944 smask
: _Field
= range(16, 19)
1945 extra
: Extra
.remap(range(10, 19))
1946 extra2
: Extra2
.remap(range(10, 19))
1947 extra3
: Extra3
.remap(range(10, 19))
1949 def specifiers(self
, record
):
1950 subvl
= int(self
.subvl
)
1958 def disassemble(self
, style
=Style
.NORMAL
):
1959 if style
>= Style
.VERBOSE
:
1961 for (name
, span
) in self
.traverse(path
="RM"):
1962 value
= self
.storage
[span
]
1964 yield f
"{indent}{int(value):0{value.bits}b}"
1965 yield f
"{indent}{', '.join(map(str, span))}"
1968 class FFPRRc1BaseRM(BaseRM
):
1969 def specifiers(self
, record
, mode
):
1970 inv
= _SelectableInt(value
=int(self
.inv
), bits
=1)
1971 CR
= _SelectableInt(value
=int(self
.CR
), bits
=2)
1972 mask
= int(_selectconcat(CR
, inv
))
1973 predicate
= PredicateBaseRM
.predicate(True, mask
)
1974 yield f
"{mode}={predicate}"
1976 yield from super().specifiers(record
=record
)
1979 class FFPRRc0BaseRM(BaseRM
):
1980 def specifiers(self
, record
, mode
):
1982 inv
= "~" if self
.inv
else ""
1983 yield f
"{mode}={inv}RC1"
1985 yield from super().specifiers(record
=record
)
1988 class SatBaseRM(BaseRM
):
1989 def specifiers(self
, record
):
1995 yield from super().specifiers(record
=record
)
1998 class ZZBaseRM(BaseRM
):
1999 def specifiers(self
, record
):
2003 yield from super().specifiers(record
=record
)
2006 class ZZCombinedBaseRM(BaseRM
):
2007 def specifiers(self
, record
):
2008 if self
.sz
and self
.dz
:
2015 yield from super().specifiers(record
=record
)
2018 class DZBaseRM(BaseRM
):
2019 def specifiers(self
, record
):
2023 yield from super().specifiers(record
=record
)
2026 class SZBaseRM(BaseRM
):
2027 def specifiers(self
, record
):
2031 yield from super().specifiers(record
=record
)
2034 class MRBaseRM(BaseRM
):
2035 def specifiers(self
, record
):
2041 yield from super().specifiers(record
=record
)
2044 class ElsBaseRM(BaseRM
):
2045 def specifiers(self
, record
):
2049 yield from super().specifiers(record
=record
)
2052 class WidthBaseRM(BaseRM
):
2054 def width(FP
, width
):
2063 width
= ("fp" + width
)
2066 def specifiers(self
, record
):
2067 # elwidths: use "w=" if same otherwise dw/sw
2068 # FIXME this should consider FP instructions
2070 dw
= WidthBaseRM
.width(FP
, int(self
.elwidth
))
2071 sw
= WidthBaseRM
.width(FP
, int(self
.ewsrc
))
2080 yield from super().specifiers(record
=record
)
2083 class PredicateBaseRM(BaseRM
):
2085 def predicate(CR
, mask
):
2088 (False, 0b001): "1<<r3",
2089 (False, 0b010): "r3",
2090 (False, 0b011): "~r3",
2091 (False, 0b100): "r10",
2092 (False, 0b101): "~r10",
2093 (False, 0b110): "r30",
2094 (False, 0b111): "~r30",
2096 (True, 0b000): "lt",
2097 (True, 0b001): "ge",
2098 (True, 0b010): "gt",
2099 (True, 0b011): "le",
2100 (True, 0b100): "eq",
2101 (True, 0b101): "ne",
2102 (True, 0b110): "so",
2103 (True, 0b111): "ns",
2106 def specifiers(self
, record
):
2107 # predication - single and twin
2108 # use "m=" if same otherwise sm/dm
2109 CR
= (int(self
.mmode
) == 1)
2110 mask
= int(self
.mask
)
2111 sm
= dm
= PredicateBaseRM
.predicate(CR
, mask
)
2112 if record
.svp64
.ptype
is _SVPType
.P2
:
2113 smask
= int(self
.smask
)
2114 sm
= PredicateBaseRM
.predicate(CR
, smask
)
2123 yield from super().specifiers(record
=record
)
2126 class PredicateWidthBaseRM(WidthBaseRM
, PredicateBaseRM
):
2130 class SEABaseRM(BaseRM
):
2131 def specifiers(self
, record
):
2135 yield from super().specifiers(record
=record
)
2138 class VLiBaseRM(BaseRM
):
2139 def specifiers(self
, record
):
2143 yield from super().specifiers(record
=record
)
2146 class NormalBaseRM(PredicateWidthBaseRM
):
2149 https://libre-soc.org/openpower/sv/normal/
2154 class NormalSimpleRM(ZZCombinedBaseRM
, NormalBaseRM
):
2155 """normal: simple mode"""
2159 def specifiers(self
, record
):
2160 yield from super().specifiers(record
=record
)
2163 class NormalMRRM(MRBaseRM
, NormalBaseRM
):
2164 """normal: scalar reduce mode (mapreduce), SUBVL=1"""
2168 class NormalFFRc1RM(FFPRRc1BaseRM
, NormalBaseRM
):
2169 """normal: Rc=1: ffirst CR sel"""
2171 CR
: BaseRM
.mode
[3, 4]
2173 def specifiers(self
, record
):
2174 yield from super().specifiers(record
=record
, mode
="ff")
2177 class NormalFFRc0RM(FFPRRc0BaseRM
, VLiBaseRM
, NormalBaseRM
):
2178 """normal: Rc=0: ffirst z/nonz"""
2183 def specifiers(self
, record
):
2184 yield from super().specifiers(record
=record
, mode
="ff")
2187 class NormalSatRM(SatBaseRM
, ZZCombinedBaseRM
, NormalBaseRM
):
2188 """normal: sat mode: N=0/1 u/s, SUBVL=1"""
2194 class NormalPRRc1RM(FFPRRc1BaseRM
, NormalBaseRM
):
2195 """normal: Rc=1: pred-result CR sel"""
2197 CR
: BaseRM
.mode
[3, 4]
2199 def specifiers(self
, record
):
2200 yield from super().specifiers(record
=record
, mode
="pr")
2203 class NormalPRRc0RM(FFPRRc0BaseRM
, ZZBaseRM
, NormalBaseRM
):
2204 """normal: Rc=0: pred-result z/nonz"""
2211 def specifiers(self
, record
):
2212 yield from super().specifiers(record
=record
, mode
="pr")
2215 class NormalRM(NormalBaseRM
):
2216 simple
: NormalSimpleRM
2218 ffrc1
: NormalFFRc1RM
2219 ffrc0
: NormalFFRc0RM
2221 prrc1
: NormalPRRc1RM
2222 prrc0
: NormalPRRc0RM
2225 class LDSTImmBaseRM(PredicateWidthBaseRM
):
2227 LD/ST Immediate mode
2228 https://libre-soc.org/openpower/sv/ldst/
2233 class LDSTImmSimpleRM(ElsBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2234 """ld/st immediate: simple mode"""
2241 class LDSTImmPostRM(LDSTImmBaseRM
):
2242 """ld/st immediate: postinc mode (and load-fault)"""
2243 pi
: BaseRM
.mode
[3] # Post-Increment Mode
2244 lf
: BaseRM
.mode
[4] # Fault-First Mode (not *Data-Dependent* Fail-First)
2246 def specifiers(self
, record
):
2253 class LDSTImmFFRc1RM(FFPRRc1BaseRM
, LDSTImmBaseRM
):
2254 """ld/st immediate: Rc=1: ffirst CR sel"""
2256 CR
: BaseRM
.mode
[3, 4]
2258 def specifiers(self
, record
):
2259 yield from super().specifiers(record
=record
, mode
="ff")
2262 class LDSTImmFFRc0RM(FFPRRc0BaseRM
, ElsBaseRM
, LDSTImmBaseRM
):
2263 """ld/st immediate: Rc=0: ffirst z/nonz"""
2268 def specifiers(self
, record
):
2269 yield from super().specifiers(record
=record
, mode
="ff")
2272 class LDSTImmSatRM(ElsBaseRM
, SatBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2273 """ld/st immediate: sat mode: N=0/1 u/s"""
2281 class LDSTImmPRRc1RM(FFPRRc1BaseRM
, LDSTImmBaseRM
):
2282 """ld/st immediate: Rc=1: pred-result CR sel"""
2284 CR
: BaseRM
.mode
[3, 4]
2286 def specifiers(self
, record
):
2287 yield from super().specifiers(record
=record
, mode
="pr")
2290 class LDSTImmPRRc0RM(FFPRRc0BaseRM
, ElsBaseRM
, LDSTImmBaseRM
):
2291 """ld/st immediate: Rc=0: pred-result z/nonz"""
2296 def specifiers(self
, record
):
2297 yield from super().specifiers(record
=record
, mode
="pr")
2300 class LDSTImmRM(LDSTImmBaseRM
):
2301 simple
: LDSTImmSimpleRM
2303 ffrc1
: LDSTImmFFRc1RM
2304 ffrc0
: LDSTImmFFRc0RM
2306 prrc1
: LDSTImmPRRc1RM
2307 prrc0
: LDSTImmPRRc0RM
2310 class LDSTIdxBaseRM(PredicateWidthBaseRM
):
2313 https://libre-soc.org/openpower/sv/ldst/
2318 class LDSTIdxSimpleRM(SEABaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2319 """ld/st index: simple mode"""
2325 class LDSTIdxStrideRM(SEABaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2326 """ld/st index: strided (scalar only source)"""
2331 def specifiers(self
, record
):
2334 yield from super().specifiers(record
=record
)
2337 class LDSTIdxSatRM(SatBaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2338 """ld/st index: sat mode: N=0/1 u/s"""
2344 class LDSTIdxPRRc1RM(LDSTIdxBaseRM
):
2345 """ld/st index: Rc=1: pred-result CR sel"""
2347 CR
: BaseRM
.mode
[3, 4]
2349 def specifiers(self
, record
):
2350 yield from super().specifiers(record
=record
, mode
="pr")
2353 class LDSTIdxPRRc0RM(FFPRRc0BaseRM
, ZZBaseRM
, LDSTIdxBaseRM
):
2354 """ld/st index: Rc=0: pred-result z/nonz"""
2361 def specifiers(self
, record
):
2362 yield from super().specifiers(record
=record
, mode
="pr")
2365 class LDSTIdxRM(LDSTIdxBaseRM
):
2366 simple
: LDSTIdxSimpleRM
2367 stride
: LDSTIdxStrideRM
2369 prrc1
: LDSTIdxPRRc1RM
2370 prrc0
: LDSTIdxPRRc0RM
2374 class CROpBaseRM(BaseRM
):
2377 https://libre-soc.org/openpower/sv/cr_ops/
2382 class CROpSimpleRM(PredicateBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2383 """crop: simple mode"""
2388 def specifiers(self
, record
):
2390 yield "rg" # simple CR Mode reports /rg
2392 yield from super().specifiers(record
=record
)
2395 class CROpMRRM(MRBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2396 """crop: scalar reduce mode (mapreduce), SUBVL=1"""
2402 class CROpFF3RM(FFPRRc0BaseRM
, PredicateBaseRM
, VLiBaseRM
, DZBaseRM
, SZBaseRM
, CROpBaseRM
):
2403 """crop: ffirst 3-bit mode"""
2410 def specifiers(self
, record
):
2411 yield from super().specifiers(record
=record
, mode
="ff")
2414 # FIXME: almost everything in this class contradicts the specs.
2415 # However, this is the direct translation of the pysvp64asm code.
2416 # Please revisit this code; there is an inactive sketch below.
2417 class CROpFF5RM(FFPRRc1BaseRM
, PredicateBaseRM
, VLiBaseRM
, CROpBaseRM
):
2418 """cr_op: ffirst 5-bit mode"""
2425 def specifiers(self
, record
):
2426 yield from super().specifiers(record
=record
, mode
="ff")
2429 class CROpRM(CROpBaseRM
):
2430 simple
: CROpSimpleRM
2436 # ********************
2438 # https://libre-soc.org/openpower/sv/branches/
2439 class BranchBaseRM(BaseRM
):
2449 def specifiers(self
, record
):
2461 raise ValueError(self
.sz
)
2473 # Branch modes lack source mask.
2474 # Therefore a custom code is needed.
2475 CR
= (int(self
.mmode
) == 1)
2476 mask
= int(self
.mask
)
2477 m
= PredicateBaseRM
.predicate(CR
, mask
)
2481 yield from super().specifiers(record
=record
)
2484 class BranchSimpleRM(BranchBaseRM
):
2485 """branch: simple mode"""
2489 class BranchVLSRM(BranchBaseRM
):
2490 """branch: VLSET mode"""
2494 def specifiers(self
, record
):
2500 }[int(self
.VSb
), int(self
.VLi
)]
2502 yield from super().specifiers(record
=record
)
2505 class BranchCTRRM(BranchBaseRM
):
2506 """branch: CTR-test mode"""
2509 def specifiers(self
, record
):
2515 yield from super().specifiers(record
=record
)
2518 class BranchCTRVLSRM(BranchVLSRM
, BranchCTRRM
):
2519 """branch: CTR-test+VLSET mode"""
2523 class BranchRM(BranchBaseRM
):
2524 simple
: BranchSimpleRM
2527 ctrvls
: BranchCTRVLSRM
2538 @_dataclasses.dataclass(eq
=True, frozen
=True)
2543 def match(cls
, desc
, record
):
2544 raise NotImplementedError()
2546 def validate(self
, others
):
2549 def assemble(self
, insn
):
2550 raise NotImplementedError()
2553 @_dataclasses.dataclass(eq
=True, frozen
=True)
2554 class SpecifierWidth(Specifier
):
2558 def match(cls
, desc
, record
, etalon
):
2559 (mode
, _
, value
) = desc
.partition("=")
2561 value
= value
.strip()
2564 width
= _SVP64Width(value
)
2566 return cls(record
=record
, width
=width
)
2569 @_dataclasses.dataclass(eq
=True, frozen
=True)
2570 class SpecifierW(SpecifierWidth
):
2572 def match(cls
, desc
, record
):
2573 return super().match(desc
=desc
, record
=record
, etalon
="w")
2575 def assemble(self
, insn
):
2576 selector
= insn
.select(record
=self
.record
)
2577 selector
.ewsrc
= self
.width
.value
2578 selector
.elwidth
= self
.width
.value
2581 @_dataclasses.dataclass(eq
=True, frozen
=True)
2582 class SpecifierSW(SpecifierWidth
):
2584 def match(cls
, desc
, record
):
2585 return super().match(desc
=desc
, record
=record
, etalon
="sw")
2587 def assemble(self
, insn
):
2588 selector
= insn
.select(record
=self
.record
)
2589 selector
.ewsrc
= self
.width
.value
2592 @_dataclasses.dataclass(eq
=True, frozen
=True)
2593 class SpecifierDW(SpecifierWidth
):
2595 def match(cls
, desc
, record
):
2596 return super().match(desc
=desc
, record
=record
, etalon
="dw")
2598 def assemble(self
, insn
):
2599 selector
= insn
.select(record
=self
.record
)
2600 selector
.elwidth
= self
.width
.value
2603 @_dataclasses.dataclass(eq
=True, frozen
=True)
2604 class SpecifierSubVL(Specifier
):
2608 def match(cls
, desc
, record
):
2610 value
= _SVP64SubVL(desc
)
2614 return cls(record
=record
, value
=value
)
2616 def assemble(self
, insn
):
2617 selector
= insn
.select(record
=self
.record
)
2618 selector
.subvl
= int(self
.value
.value
)
2621 @_dataclasses.dataclass(eq
=True, frozen
=True)
2622 class SpecifierPredicate(Specifier
):
2627 def match(cls
, desc
, record
, mode_match
, pred_match
):
2628 (mode
, _
, pred
) = desc
.partition("=")
2631 if not mode_match(mode
):
2634 pred
= _SVP64Pred(pred
.strip())
2635 if not pred_match(pred
):
2636 raise ValueError(pred
)
2638 return cls(record
=record
, mode
=mode
, pred
=pred
)
2641 @_dataclasses.dataclass(eq
=True, frozen
=True)
2642 class SpecifierFFPR(SpecifierPredicate
):
2644 def match(cls
, desc
, record
, mode
):
2645 return super().match(desc
=desc
, record
=record
,
2646 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2647 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2652 def validate(self
, others
):
2653 if self
.record
.svp64
.mode
is _SVMode
.CROP
:
2654 if self
.mode
== "pr":
2655 raise ValueError("crop: 'pr' mode not supported")
2656 if (self
.record
.svp64
.extra_CR_3bit
and
2657 (self
.pred
.mode
is not _SVP64PredMode
.RC1
)):
2658 raise ValueError("3-bit CRs only support RC1/~RC1 BO")
2660 def assemble(self
, insn
):
2661 selector
= insn
.select(record
=self
.record
)
2662 if selector
.mode
.sel
!= 0:
2663 raise ValueError("cannot override mode")
2664 if self
.record
.svp64
.mode
is _SVMode
.CROP
:
2665 selector
.mode
.sel
= 0b10
2666 selector
.inv
= self
.pred
.inv
2667 if not self
.record
.svp64
.extra_CR_3bit
:
2668 selector
.CR
= self
.pred
.state
2670 selector
.mode
.sel
= 0b01 if self
.mode
== "ff" else 0b11
2671 selector
.inv
= self
.pred
.inv
2673 selector
.CR
= self
.pred
.state
2675 selector
.RC1
= self
.pred
.state
2678 @_dataclasses.dataclass(eq
=True, frozen
=True)
2679 class SpecifierFF(SpecifierFFPR
):
2681 def match(cls
, desc
, record
):
2682 return super().match(desc
=desc
, record
=record
, mode
="ff")
2685 @_dataclasses.dataclass(eq
=True, frozen
=True)
2686 class SpecifierPR(SpecifierFFPR
):
2688 def match(cls
, desc
, record
):
2689 return super().match(desc
=desc
, record
=record
, mode
="pr")
2692 @_dataclasses.dataclass(eq
=True, frozen
=True)
2693 class SpecifierMask(SpecifierPredicate
):
2695 def match(cls
, desc
, record
, mode
):
2696 return super().match(desc
=desc
, record
=record
,
2697 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2698 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2703 def assemble(self
, insn
):
2704 raise NotImplementedError()
2707 @_dataclasses.dataclass(eq
=True, frozen
=True)
2708 class SpecifierM(SpecifierMask
):
2710 def match(cls
, desc
, record
):
2711 return super().match(desc
=desc
, record
=record
, mode
="m")
2713 def validate(self
, others
):
2715 if isinstance(spec
, SpecifierSM
):
2716 raise ValueError("source-mask and predicate mask conflict")
2717 elif isinstance(spec
, SpecifierDM
):
2718 raise ValueError("dest-mask and predicate mask conflict")
2720 def assemble(self
, insn
):
2721 selector
= insn
.select(record
=self
.record
)
2722 selector
.mask
= int(self
.pred
)
2723 if ((self
.record
.ptype
is _SVPType
.P2
) and
2724 (self
.record
.svp64
.mode
is not _SVMode
.BRANCH
)):
2725 selector
.smask
= int(self
.pred
)
2726 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2729 @_dataclasses.dataclass(eq
=True, frozen
=True)
2730 class SpecifierSM(SpecifierMask
):
2732 def match(cls
, desc
, record
):
2733 return super().match(desc
=desc
, record
=record
, mode
="sm")
2735 def validate(self
, others
):
2736 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2737 raise ValueError("source-mask on non-twin predicate")
2739 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2742 if isinstance(spec
, SpecifierDM
):
2746 raise ValueError("missing dest-mask in CR twin predication")
2747 if self
.pred
.mode
!= twin
.pred
.mode
:
2748 raise ValueError(f
"predicate masks mismatch: {self.pred!r} vs {twin.pred!r}")
2750 def assemble(self
, insn
):
2751 selector
= insn
.select(record
=self
.record
)
2752 selector
.smask
= int(self
.pred
)
2753 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2756 @_dataclasses.dataclass(eq
=True, frozen
=True)
2757 class SpecifierDM(SpecifierMask
):
2759 def match(cls
, desc
, record
):
2760 return super().match(desc
=desc
, record
=record
, mode
="dm")
2762 def validate(self
, others
):
2763 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2764 raise ValueError("dest-mask on non-twin predicate")
2766 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2769 if isinstance(spec
, SpecifierSM
):
2773 raise ValueError("missing source-mask in CR twin predication")
2774 if self
.pred
.mode
!= twin
.pred
.mode
:
2775 raise ValueError(f
"predicate masks mismatch: {self.pred!r} vs {twin.pred!r}")
2777 def assemble(self
, insn
):
2778 selector
= insn
.select(record
=self
.record
)
2779 selector
.mask
= int(self
.pred
)
2780 selector
.mmode
= (self
.pred
.mode
is _SVP64PredMode
.CR
)
2783 @_dataclasses.dataclass(eq
=True, frozen
=True)
2784 class SpecifierZZ(Specifier
):
2786 def match(cls
, desc
, record
):
2790 return cls(record
=record
)
2792 def validate(self
, others
):
2794 # Since zz takes precedence (overrides) sz and dz,
2795 # treat them as mutually exclusive.
2796 if isinstance(spec
, (SpecifierSZ
, SpecifierDZ
)):
2797 raise ValueError("mutually exclusive predicate masks")
2799 def assemble(self
, insn
):
2800 selector
= insn
.select(record
=self
.record
)
2801 if hasattr(selector
, "zz"): # this should be done in a different way
2808 @_dataclasses.dataclass(eq
=True, frozen
=True)
2809 class SpecifierXZ(Specifier
):
2811 hint
: str = _dataclasses
.field(repr=False)
2814 def match(cls
, desc
, record
, etalon
, hint
):
2818 return cls(desc
=desc
, record
=record
, hint
=hint
)
2820 def validate(self
, others
):
2821 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2822 raise ValueError(f
"{self.hint} on non-twin predicate")
2824 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2827 if isinstance(spec
, SpecifierXZ
):
2831 raise ValueError(f
"missing {self.hint} in CR twin predication")
2832 if self
.pred
!= twin
.pred
:
2833 raise ValueError(f
"predicate masks mismatch: {self.pred!r} vs {twin.pred!r}")
2835 def assemble(self
, insn
):
2836 selector
= insn
.select(record
=self
.record
)
2837 setattr(selector
, self
.desc
, 1)
2840 @_dataclasses.dataclass(eq
=True, frozen
=True)
2841 class SpecifierSZ(SpecifierXZ
):
2843 def match(cls
, desc
, record
):
2844 return super().match(desc
=desc
, record
=record
,
2845 etalon
="sz", hint
="source-mask")
2847 def validate(self
, others
):
2849 if self
.record
.svp64
.mode
is not _SVMode
.CROP
:
2850 if isinstance(spec
, SpecifierFF
):
2851 raise ValueError("source-zero not allowed in ff mode")
2852 elif isinstance(spec
, SpecifierPR
):
2853 raise ValueError("source-zero not allowed in pr mode")
2856 @_dataclasses.dataclass(eq
=True, frozen
=True)
2857 class SpecifierDZ(SpecifierXZ
):
2859 def match(cls
, desc
, record
):
2860 return super().match(desc
=desc
, record
=record
,
2861 etalon
="dz", hint
="dest-mask")
2863 def validate(self
, others
):
2865 if ((self
.record
.svp64
.mode
is not _SVMode
.CROP
) and
2866 isinstance(spec
, (SpecifierFF
, SpecifierPR
)) and
2867 (spec
.pred
.mode
is _SVP64PredMode
.RC1
)):
2868 mode
= "ff" if isinstance(spec
, SpecifierFF
) else "pr"
2869 raise ValueError(f
"dest-zero not allowed in {mode} mode BO")
2872 @_dataclasses.dataclass(eq
=True, frozen
=True)
2873 class SpecifierEls(Specifier
):
2875 def match(cls
, desc
, record
):
2879 if record
.svp64
.mode
not in (_SVMode
.LDST_IMM
, _SVMode
.LDST_IDX
):
2880 raise ValueError("els is only valid in ld/st modes")
2882 return cls(record
=record
)
2884 def assemble(self
, insn
):
2885 if self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
: # stride mode
2886 insn
.prefix
.rm
.mode
[0] = 0
2887 insn
.prefix
.rm
.mode
[1] = 1
2889 selector
= insn
.select(record
=self
.record
)
2890 if self
.record
.svp64
.mode
is not _SVMode
.LDST_IDX
: # stride mode
2895 @_dataclasses.dataclass(eq
=True, frozen
=True)
2896 class SpecifierSEA(Specifier
):
2898 def match(cls
, desc
, record
):
2902 return cls(record
=record
)
2904 def validate(self
, others
):
2905 if self
.record
.svp64
.mode
is not _SVMode
.LDST_IDX
:
2906 raise ValueError("sea is only valid in ld/st modes")
2909 if isinstance(spec
, SpecifierFF
):
2910 raise ValueError(f
"sea cannot be used in ff mode")
2912 def assemble(self
, insn
):
2913 selector
= insn
.select(record
=self
.record
)
2914 if selector
.mode
.sel
not in (0b00, 0b01):
2915 raise ValueError("sea is only valid for normal and els modes")
2919 @_dataclasses.dataclass(eq
=True, frozen
=True)
2920 class SpecifierSat(Specifier
):
2925 def match(cls
, desc
, record
, etalon
, sign
):
2929 if record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.LDST_IMM
, _SVMode
.LDST_IDX
):
2930 raise ValueError("only normal, ld/st imm and ld/st idx modes supported")
2932 return cls(record
=record
, desc
=desc
, sign
=sign
)
2934 def assemble(self
, insn
):
2935 selector
= insn
.select(record
=self
.record
)
2936 selector
.mode
[0] = 0b1
2937 selector
.mode
[1] = 0b0
2938 selector
.N
= int(self
.sign
)
2941 @_dataclasses.dataclass(eq
=True, frozen
=True)
2942 class SpecifierSatS(SpecifierSat
):
2944 def match(cls
, desc
, record
):
2945 return super().match(desc
=desc
, record
=record
,
2946 etalon
="sats", sign
=True)
2949 @_dataclasses.dataclass(eq
=True, frozen
=True)
2950 class SpecifierSatU(SpecifierSat
):
2952 def match(cls
, desc
, record
):
2953 return super().match(desc
=desc
, record
=record
,
2954 etalon
="satu", sign
=False)
2957 @_dataclasses.dataclass(eq
=True, frozen
=True)
2958 class SpecifierMapReduce(Specifier
):
2962 def match(cls
, record
, RG
):
2963 if record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.CROP
):
2964 raise ValueError("only normal and crop modes supported")
2966 return cls(record
=record
, RG
=RG
)
2968 def assemble(self
, insn
):
2969 selector
= insn
.select(record
=self
.record
)
2970 if self
.record
.svp64
.mode
not in (_SVMode
.NORMAL
, _SVMode
.CROP
):
2971 raise ValueError("only normal and crop modes supported")
2972 selector
.mode
[0] = 0
2973 selector
.mode
[1] = 0
2974 selector
.mode
[2] = 1
2975 selector
.RG
= self
.RG
2978 @_dataclasses.dataclass(eq
=True, frozen
=True)
2979 class SpecifierMR(SpecifierMapReduce
):
2981 def match(cls
, desc
, record
):
2985 return super().match(record
=record
, RG
=False)
2988 @_dataclasses.dataclass(eq
=True, frozen
=True)
2989 class SpecifierMRR(SpecifierMapReduce
):
2991 def match(cls
, desc
, record
):
2995 return super().match(record
=record
, RG
=True)
2998 @_dataclasses.dataclass(eq
=True, frozen
=True)
2999 class SpecifierBranch(Specifier
):
3001 def match(cls
, desc
, record
, etalon
):
3005 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
3006 raise ValueError("only branch modes supported")
3008 return cls(record
=record
)
3011 @_dataclasses.dataclass(eq
=True, frozen
=True)
3012 class SpecifierAll(SpecifierBranch
):
3014 def match(cls
, desc
, record
):
3015 return super().match(desc
=desc
, record
=record
, etalon
="all")
3017 def assemble(self
, insn
):
3018 selector
= insn
.select(record
=self
.record
)
3022 @_dataclasses.dataclass(eq
=True, frozen
=True)
3023 class SpecifierSNZ(Specifier
):
3025 def match(cls
, desc
, record
):
3029 if record
.svp64
.mode
not in (_SVMode
.BRANCH
, _SVMode
.CROP
):
3030 raise ValueError("only branch and crop modes supported")
3032 return cls(record
=record
)
3034 def assemble(self
, insn
):
3035 selector
= insn
.select(record
=self
.record
)
3036 if self
.record
.svp64
.mode
in (_SVMode
.CROP
, _SVMode
.BRANCH
):
3038 if self
.record
.svp64
.mode
is _SVMode
.BRANCH
:
3041 raise ValueError("only branch and crop modes supported")
3044 @_dataclasses.dataclass(eq
=True, frozen
=True)
3045 class SpecifierSL(SpecifierBranch
):
3047 def match(cls
, desc
, record
):
3048 return super().match(desc
=desc
, record
=record
, etalon
="sl")
3050 def assemble(self
, insn
):
3051 selector
= insn
.select(record
=self
.record
)
3055 @_dataclasses.dataclass(eq
=True, frozen
=True)
3056 class SpecifierSLu(SpecifierBranch
):
3058 def match(cls
, desc
, record
):
3059 return super().match(desc
=desc
, record
=record
, etalon
="slu")
3061 def assemble(self
, insn
):
3062 selector
= insn
.select(record
=self
.record
)
3066 @_dataclasses.dataclass(eq
=True, frozen
=True)
3067 class SpecifierLRu(SpecifierBranch
):
3069 def match(cls
, desc
, record
):
3070 return super().match(desc
=desc
, record
=record
, etalon
="lru")
3072 def assemble(self
, insn
):
3073 selector
= insn
.select(record
=self
.record
)
3077 @_dataclasses.dataclass(eq
=True, frozen
=True)
3078 class SpecifierVSXX(SpecifierBranch
):
3083 def match(cls
, desc
, record
, etalon
, VSb
, VLi
):
3087 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
3088 raise ValueError("only branch modes supported")
3090 return cls(record
=record
, VSb
=VSb
, VLi
=VLi
)
3092 def assemble(self
, insn
):
3093 selector
= insn
.select(record
=self
.record
)
3095 selector
.VSb
= int(self
.VSb
)
3096 selector
.VLi
= int(self
.VLi
)
3099 @_dataclasses.dataclass(eq
=True, frozen
=True)
3100 class SpecifierVS(SpecifierVSXX
):
3102 def match(cls
, desc
, record
):
3103 return super().match(desc
=desc
, record
=record
,
3104 etalon
="vs", VSb
=False, VLi
=False)
3107 @_dataclasses.dataclass(eq
=True, frozen
=True)
3108 class SpecifierVSi(SpecifierVSXX
):
3110 def match(cls
, desc
, record
):
3111 return super().match(desc
=desc
, record
=record
,
3112 etalon
="vsi", VSb
=False, VLi
=True)
3115 @_dataclasses.dataclass(eq
=True, frozen
=True)
3116 class SpecifierVSb(SpecifierVSXX
):
3118 def match(cls
, desc
, record
):
3119 return super().match(desc
=desc
, record
=record
,
3120 etalon
="vsb", VSb
=True, VLi
=False)
3123 @_dataclasses.dataclass(eq
=True, frozen
=True)
3124 class SpecifierVSbi(SpecifierVSXX
):
3126 def match(cls
, desc
, record
):
3127 return super().match(desc
=desc
, record
=record
,
3128 etalon
="vsbi", VSb
=True, VLi
=True)
3131 @_dataclasses.dataclass(eq
=True, frozen
=True)
3132 class SpecifierCTX(Specifier
):
3136 def match(cls
, desc
, record
, etalon
, CTi
):
3140 if record
.svp64
.mode
is not _SVMode
.BRANCH
:
3141 raise ValueError("only branch modes supported")
3143 return cls(record
=record
, CTi
=CTi
)
3145 def assemble(self
, insn
):
3146 selector
= insn
.select(record
=self
.record
)
3148 selector
.CTi
= int(self
.CTi
)
3151 @_dataclasses.dataclass(eq
=True, frozen
=True)
3152 class SpecifierCTR(SpecifierCTX
):
3154 def match(cls
, desc
, record
):
3155 return super().match(desc
=desc
, record
=record
,
3156 etalon
="ctr", CTi
=False)
3159 @_dataclasses.dataclass(eq
=True, frozen
=True)
3160 class SpecifierCTi(SpecifierCTX
):
3162 def match(cls
, desc
, record
):
3163 return super().match(desc
=desc
, record
=record
,
3164 etalon
="cti", CTi
=True)
3167 @_dataclasses.dataclass(eq
=True, frozen
=True)
3168 class SpecifierPI(Specifier
):
3170 def match(cls
, desc
, record
):
3174 if record
.svp64
.mode
is not _SVMode
.LDST_IMM
:
3175 raise ValueError("only ld/st imm mode supported")
3177 return cls(record
=record
)
3179 def assemble(self
, insn
):
3180 selector
= insn
.select(record
=self
.record
)
3181 selector
.mode
[0] = 0b0
3182 selector
.mode
[1] = 0b0
3183 selector
.mode
[2] = 0b1
3187 @_dataclasses.dataclass(eq
=True, frozen
=True)
3188 class SpecifierLF(Specifier
):
3190 def match(cls
, desc
, record
):
3194 if record
.svp64
.mode
is not _SVMode
.LDST_IMM
:
3195 raise ValueError("only ld/st imm mode supported")
3197 return cls(record
=record
)
3199 def assemble(self
, insn
):
3200 selector
= insn
.select(record
=self
.record
)
3201 selector
.mode
[2] = 1
3205 @_dataclasses.dataclass(eq
=True, frozen
=True)
3206 class SpecifierVLi(Specifier
):
3208 def match(cls
, desc
, record
):
3212 return cls(record
=record
)
3214 def validate(self
, others
):
3216 if isinstance(spec
, SpecifierFF
):
3219 raise ValueError("VLi only allowed in failfirst")
3221 def assemble(self
, insn
):
3222 selector
= insn
.select(record
=self
.record
)
3226 class Specifiers(tuple):
3262 def __new__(cls
, items
, record
):
3263 def transform(item
):
3264 for spec_cls
in cls
.SPECS
:
3265 spec
= spec_cls
.match(item
, record
=record
)
3266 if spec
is not None:
3268 raise ValueError(item
)
3270 # TODO: remove this hack
3271 items
= dict.fromkeys(items
)
3275 items
= tuple(items
)
3277 specs
= tuple(map(transform
, items
))
3278 for (index
, spec
) in enumerate(specs
):
3279 head
= specs
[:index
]
3280 tail
= specs
[index
+ 1:]
3281 spec
.validate(others
=(head
+ tail
))
3283 return super().__new
__(cls
, specs
)
3286 class SVP64OperandMeta(type):
3287 class SVP64NonZeroOperand(NonZeroOperand
):
3288 def assemble(self
, insn
, value
):
3289 if isinstance(value
, str):
3290 value
= int(value
, 0)
3291 if not isinstance(value
, int):
3292 raise ValueError("non-integer operand")
3294 # FIXME: this is really weird
3295 if self
.record
.name
in ("svstep", "svstep."):
3296 value
+= 1 # compensation
3298 return super().assemble(value
=value
, insn
=insn
)
3300 class SVP64XOStaticOperand(SpanStaticOperand
):
3301 def __init__(self
, record
, value
, span
):
3302 return super().__init
__(record
=record
, name
="XO", value
=value
, span
=span
)
3305 NonZeroOperand
: SVP64NonZeroOperand
,
3306 XOStaticOperand
: SVP64XOStaticOperand
,
3309 def __new__(metacls
, name
, bases
, ns
):
3311 for (index
, base_cls
) in enumerate(bases
):
3312 bases
[index
] = metacls
.__TRANSFORM
.get(base_cls
, base_cls
)
3314 bases
= tuple(bases
)
3316 return super().__new
__(metacls
, name
, bases
, ns
)
3319 class SVP64Operand(Operand
, metaclass
=SVP64OperandMeta
):
3322 return tuple(map(lambda bit
: (bit
+ 32), super().span
))
3326 def __init__(self
, insn
, record
):
3328 self
.__record
= record
3329 return super().__init
__()
3332 return self
.rm
.__doc
__
3335 return repr(self
.rm
)
3343 return self
.__record
3347 rm
= getattr(self
.insn
.prefix
.rm
, self
.record
.svp64
.mode
.name
.lower())
3349 # The idea behind these tables is that they are now literally
3350 # in identical format to insndb.csv and minor_xx.csv and can
3351 # be done precisely as that. The only thing to watch out for
3352 # is the insertion of Rc=1 as a "mask/value" bit and likewise
3353 # regtype detection (3-bit BF/BFA, 5-bit BA/BB/BT) also inserted
3356 if self
.record
.svp64
.mode
is _SVMode
.NORMAL
:
3357 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3358 # mode Rc mask Rc member
3360 (0b000000, 0b111000, "simple"), # simple (no Rc)
3361 (0b001000, 0b111000, "mr"), # mapreduce (no Rc)
3362 (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
3363 (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
3364 (0b100000, 0b110000, "sat"), # saturation (no Rc)
3365 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
3366 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
3368 search
= ((int(self
.insn
.prefix
.rm
.normal
.mode
) << 1) | self
.record
.Rc
)
3370 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IMM
:
3371 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3372 # mode Rc mask Rc member
3373 # ironically/coincidentally this table is identical to NORMAL
3374 # mode except reserved in place of mr
3376 (0b000000, 0b111000, "simple"), # simple (no Rc)
3377 (0b001000, 0b111000, "post"), # post (no Rc)
3378 (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
3379 (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
3380 (0b100000, 0b110000, "sat"), # saturation (no Rc)
3381 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
3382 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
3384 search
= ((int(self
.insn
.prefix
.rm
.ldst_imm
.mode
) << 1) | self
.record
.Rc
)
3386 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
3387 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
3388 # mode Rc mask Rc member
3390 (0b000000, 0b110000, "simple"), # simple (no Rc)
3391 (0b010000, 0b110000, "stride"), # strided, (no Rc)
3392 (0b100000, 0b110000, "sat"), # saturation (no Rc)
3393 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
3394 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
3396 search
= ((int(self
.insn
.prefix
.rm
.ldst_idx
.mode
) << 1) | self
.record
.Rc
)
3398 elif self
.record
.svp64
.mode
is _SVMode
.CROP
:
3399 # concatenate mode 5-bit with regtype (LSB) then do mask/map search
3400 # mode 3b mask 3b member
3402 (0b000000, 0b111000, "simple"), # simple
3403 (0b001000, 0b111000, "mr"), # mapreduce
3404 (0b100001, 0b100001, "ff3"), # ffirst, 3-bit CR
3405 (0b100000, 0b100000, "ff5"), # ffirst, 5-bit CR
3407 search
= ((int(self
.insn
.prefix
.rm
.crop
.mode
) << 1) |
int(self
.record
.svp64
.extra_CR_3bit
))
3409 elif self
.record
.svp64
.mode
is _SVMode
.BRANCH
:
3413 (0b00, 0b11, "simple"), # simple
3414 (0b01, 0b11, "vls"), # VLset
3415 (0b10, 0b11, "ctr"), # CTR mode
3416 (0b11, 0b11, "ctrvls"), # CTR+VLset mode
3418 # slightly weird: doesn't have a 5-bit "mode" field like others
3419 search
= int(self
.insn
.prefix
.rm
.branch
.mode
.sel
)
3422 if table
is not None:
3423 for (value
, mask
, field
) in table
:
3424 if ((value
& mask
) == (search
& mask
)):
3425 return getattr(rm
, field
)
3429 def __getattr__(self
, key
):
3430 if key
.startswith(f
"_{self.__class__.__name__}__"):
3431 return super().__getattribute
__(key
)
3433 return getattr(self
.rm
, key
)
3435 def __setattr__(self
, key
, value
):
3436 if key
.startswith(f
"_{self.__class__.__name__}__"):
3437 return super().__setattr
__(key
, value
)
3440 if not hasattr(rm
, key
):
3441 raise AttributeError(key
)
3443 return setattr(rm
, key
, value
)
3446 class SVP64Instruction(PrefixedInstruction
):
3447 """SVP64 instruction: https://libre-soc.org/openpower/sv/svp64/"""
3448 class Prefix(PrefixedInstruction
.Prefix
):
3450 rm
: RM
.remap((6, 8) + tuple(range(10, 32)))
3454 def select(self
, record
):
3455 return RMSelector(insn
=self
, record
=record
)
3460 for idx
in range(64):
3461 bit
= int(self
[idx
])
3463 return "".join(map(str, bits
))
3466 def assemble(cls
, record
, arguments
=None, specifiers
=None):
3467 insn
= super().assemble(record
=record
, arguments
=arguments
)
3469 specifiers
= Specifiers(items
=specifiers
, record
=record
)
3470 for specifier
in specifiers
:
3471 specifier
.assemble(insn
=insn
)
3473 insn
.prefix
.PO
= 0x1
3474 insn
.prefix
.id = 0x3
3478 def disassemble(self
, record
,
3480 style
=Style
.NORMAL
):
3482 if style
<= Style
.SHORT
:
3485 blob
= insn
.bytes(byteorder
=byteorder
)
3486 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
3489 blob_prefix
= blob(self
.prefix
)
3490 blob_suffix
= blob(self
.suffix
)
3492 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
3493 yield f
"{blob_suffix}.long 0x{int(self.suffix):08x}"
3496 assert record
.svp64
is not None
3498 name
= f
"sv.{record.name}"
3500 rm
= self
.select(record
=record
)
3502 # convert specifiers to /x/y/z (sorted lexicographically)
3503 specifiers
= sorted(rm
.specifiers(record
=record
))
3504 if specifiers
: # if any add one extra to get the extra "/"
3505 specifiers
= ([""] + specifiers
)
3506 specifiers
= "/".join(specifiers
)
3508 # convert operands to " ,x,y,z"
3509 operands
= tuple(map(_operator
.itemgetter(1),
3510 self
.spec_dynamic_operands(record
=record
, style
=style
)))
3511 operands
= ",".join(operands
)
3512 if len(operands
) > 0: # if any separate with a space
3513 operands
= (" " + operands
)
3515 if style
<= Style
.LEGACY
:
3516 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
3517 suffix
= WordInstruction
.integer(value
=int(self
.suffix
))
3518 yield from suffix
.disassemble(record
=record
,
3519 byteorder
=byteorder
, style
=style
)
3521 yield f
"{blob_prefix}{name}{specifiers}{operands}"
3523 yield f
"{blob_suffix}"
3525 if style
>= Style
.VERBOSE
:
3527 binary
= self
.binary
3528 spec
= self
.spec(record
=record
, prefix
="sv.")
3530 yield f
"{indent}spec"
3531 yield f
"{indent}{indent}{spec}"
3532 yield f
"{indent}pcode"
3533 for stmt
in record
.mdwn
.pcode
:
3534 yield f
"{indent}{indent}{stmt}"
3535 yield f
"{indent}binary"
3536 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
3537 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
3538 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
3539 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
3540 yield f
"{indent}{indent}[32:40] {binary[32:40]}"
3541 yield f
"{indent}{indent}[40:48] {binary[40:48]}"
3542 yield f
"{indent}{indent}[48:56] {binary[48:56]}"
3543 yield f
"{indent}{indent}[56:64] {binary[56:64]}"
3544 yield f
"{indent}opcodes"
3545 for opcode
in record
.opcodes
:
3546 yield f
"{indent}{indent}{opcode!r}"
3547 for operand
in self
.operands(record
=record
):
3548 yield from operand
.disassemble(insn
=self
,
3549 style
=style
, indent
=indent
)
3551 yield f
"{indent}{indent}{str(rm)}"
3552 for line
in rm
.disassemble(style
=style
):
3553 yield f
"{indent}{indent}{line}"
3557 def operands(cls
, record
):
3558 for operand
in super().operands(record
=record
):
3559 parent
= operand
.__class
__
3560 name
= f
"SVP64{parent.__name__}"
3561 bases
= (SVP64Operand
, parent
)
3562 child
= type(name
, bases
, {})
3563 yield child(**dict(operand
))
3566 def parse(stream
, factory
):
3568 return ("TODO" not in frozenset(entry
.values()))
3570 lines
= filter(lambda line
: not line
.strip().startswith("#"), stream
)
3571 entries
= _csv
.DictReader(lines
)
3572 entries
= filter(match
, entries
)
3573 return tuple(map(factory
, entries
))
3576 class MarkdownDatabase
:
3579 for (name
, desc
) in _ISA():
3582 (dynamic
, *static
) = desc
.regs
3583 operands
.extend(dynamic
)
3584 operands
.extend(static
)
3585 pcode
= PCode(iterable
=desc
.pcode
)
3586 operands
= Operands(insn
=name
, operands
=operands
)
3587 db
[name
] = MarkdownRecord(pcode
=pcode
, operands
=operands
)
3589 self
.__db
= dict(sorted(db
.items()))
3591 return super().__init
__()
3594 yield from self
.__db
.items()
3596 def __contains__(self
, key
):
3597 return self
.__db
.__contains
__(key
)
3599 def __getitem__(self
, key
):
3600 return self
.__db
.__getitem
__(key
)
3603 class FieldsDatabase
:
3606 df
= _DecodeFields()
3608 for (form
, fields
) in df
.instrs
.items():
3609 if form
in {"DQE", "TX"}:
3613 db
[_Form
[form
]] = Fields(fields
)
3617 return super().__init
__()
3619 def __getitem__(self
, key
):
3620 return self
.__db
.__getitem
__(key
)
3624 def __init__(self
, root
, mdwndb
):
3625 # The code below groups the instructions by name:section.
3626 # There can be multiple names for the same instruction.
3627 # The point is to capture different opcodes for the same instruction.
3629 records
= _collections
.defaultdict(set)
3630 path
= (root
/ "insndb.csv")
3631 with
open(path
, "r", encoding
="UTF-8") as stream
:
3632 for section
in sorted(parse(stream
, Section
.CSV
)):
3633 path
= (root
/ section
.path
)
3635 section
.Mode
.INTEGER
: IntegerOpcode
,
3636 section
.Mode
.PATTERN
: PatternOpcode
,
3638 factory
= _functools
.partial(
3639 PPCRecord
.CSV
, opcode_cls
=opcode_cls
)
3640 with
open(path
, "r", encoding
="UTF-8") as stream
:
3641 for insn
in parse(stream
, factory
):
3642 for name
in insn
.names
:
3643 records
[name
].add(insn
)
3644 sections
[name
] = section
3646 items
= sorted(records
.items())
3648 for (name
, multirecord
) in items
:
3649 records
[name
] = PPCMultiRecord(sorted(multirecord
))
3651 def exact_match(name
):
3652 record
= records
.get(name
)
3658 if not name
.endswith("l"):
3660 alias
= exact_match(name
[:-1])
3663 record
= records
[alias
]
3664 if "lk" not in record
.flags
:
3665 raise ValueError(record
)
3669 if not name
.endswith("a"):
3671 alias
= LK_match(name
[:-1])
3674 record
= records
[alias
]
3675 if record
.intop
not in {_MicrOp
.OP_B
, _MicrOp
.OP_BC
}:
3676 raise ValueError(record
)
3677 if "AA" not in mdwndb
[name
].operands
:
3678 raise ValueError(record
)
3682 if not name
.endswith("."):
3684 alias
= exact_match(name
[:-1])
3687 record
= records
[alias
]
3688 if record
.Rc
is _RCOE
.NONE
:
3689 raise ValueError(record
)
3693 matches
= (exact_match
, LK_match
, AA_match
, Rc_match
)
3694 for (name
, _
) in mdwndb
:
3695 if name
.startswith("sv."):
3698 for match
in matches
:
3700 if alias
is not None:
3704 section
= sections
[alias
]
3705 record
= records
[alias
]
3706 db
[name
] = (section
, record
)
3708 self
.__db
= dict(sorted(db
.items()))
3710 return super().__init
__()
3712 @_functools.lru_cache(maxsize
=512, typed
=False)
3713 def __getitem__(self
, key
):
3714 return self
.__db
.get(key
, (None, None))
3717 class SVP64Database
:
3718 def __init__(self
, root
, ppcdb
):
3720 pattern
= _re
.compile(r
"^(?:LDST)?RM-(1P|2P)-.*?\.csv$")
3721 for (prefix
, _
, names
) in _os
.walk(root
):
3722 prefix
= _pathlib
.Path(prefix
)
3723 for name
in filter(lambda name
: pattern
.match(name
), names
):
3724 path
= (prefix
/ _pathlib
.Path(name
))
3725 with
open(path
, "r", encoding
="UTF-8") as stream
:
3726 db
.update(parse(stream
, SVP64Record
.CSV
))
3727 db
= {record
.name
:record
for record
in db
}
3729 self
.__db
= dict(sorted(db
.items()))
3730 self
.__ppcdb
= ppcdb
3732 return super().__init
__()
3734 def __getitem__(self
, key
):
3735 (_
, record
) = self
.__ppcdb
[key
]
3739 for name
in record
.names
:
3740 record
= self
.__db
.get(name
, None)
3741 if record
is not None:
3748 def __init__(self
, root
):
3749 root
= _pathlib
.Path(root
)
3750 mdwndb
= MarkdownDatabase()
3751 fieldsdb
= FieldsDatabase()
3752 ppcdb
= PPCDatabase(root
=root
, mdwndb
=mdwndb
)
3753 svp64db
= SVP64Database(root
=root
, ppcdb
=ppcdb
)
3757 opcodes
= _collections
.defaultdict(
3758 lambda: _collections
.defaultdict(set))
3760 for (name
, mdwn
) in mdwndb
:
3761 if name
.startswith("sv."):
3763 (section
, ppc
) = ppcdb
[name
]
3766 svp64
= svp64db
[name
]
3767 fields
= fieldsdb
[ppc
.form
]
3768 record
= Record(name
=name
,
3769 section
=section
, ppc
=ppc
, svp64
=svp64
,
3770 mdwn
=mdwn
, fields
=fields
)
3772 names
[record
.name
] = record
3773 opcodes
[section
][record
.PO
].add(record
)
3775 self
.__db
= sorted(db
)
3776 self
.__names
= dict(sorted(names
.items()))
3777 self
.__opcodes
= dict(sorted(opcodes
.items()))
3779 return super().__init
__()
3782 return repr(self
.__db
)
3785 yield from self
.__db
3787 @_functools.lru_cache(maxsize
=None)
3788 def __contains__(self
, key
):
3789 return self
.__getitem
__(key
) is not None
3791 @_functools.lru_cache(maxsize
=None)
3792 def __getitem__(self
, key
):
3793 if isinstance(key
, SVP64Instruction
):
3796 if isinstance(key
, Instruction
):
3799 sections
= sorted(self
.__opcodes
)
3800 for section
in sections
:
3801 group
= self
.__opcodes
[section
]
3802 for record
in group
[PO
]:
3803 if record
.match(key
=key
):
3808 elif isinstance(key
, str):
3809 return self
.__names
.get(key
)
3811 raise ValueError("instruction or name expected")