1 import collections
as _collections
3 import dataclasses
as _dataclasses
5 import functools
as _functools
6 import itertools
as _itertools
8 import operator
as _operator
9 import pathlib
as _pathlib
13 from functools
import cached_property
15 from cached_property
import cached_property
17 from openpower
.decoder
.power_enums
import (
18 Function
as _Function
,
25 CRIn2Sel
as _CRIn2Sel
,
26 CROutSel
as _CROutSel
,
28 LDSTMode
as _LDSTMode
,
33 SVMaskSrc
as _SVMaskSrc
,
38 SVP64RMMode
as _SVP64RMMode
,
39 SVExtraRegType
as _SVExtraRegType
,
40 SVExtraReg
as _SVExtraReg
,
41 SVP64SubVL
as _SVP64SubVL
,
42 SVP64Pred
as _SVP64Pred
,
43 SVP64PredMode
as _SVP64PredMode
,
44 SVP64Width
as _SVP64Width
,
46 from openpower
.decoder
.selectable_int
import (
47 SelectableInt
as _SelectableInt
,
48 selectconcat
as _selectconcat
,
50 from openpower
.decoder
.power_fields
import (
53 DecodeFields
as _DecodeFields
,
55 from openpower
.decoder
.pseudo
.pagereader
import ISA
as _ISA
58 @_functools.total_ordering
59 class Verbosity(_enum
.Enum
):
62 VERBOSE
= _enum
.auto()
64 def __lt__(self
, other
):
65 if not isinstance(other
, self
.__class
__):
67 return (self
.value
< other
.value
)
70 @_functools.total_ordering
71 class Priority(_enum
.Enum
):
77 def _missing_(cls
, value
):
78 if isinstance(value
, str):
83 return super()._missing
_(value
)
85 def __lt__(self
, other
):
86 if not isinstance(other
, self
.__class
__):
89 # NOTE: the order is inversed, LOW < NORMAL < HIGH
90 return (self
.value
> other
.value
)
93 def dataclass(cls
, record
, keymap
=None, typemap
=None):
97 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
99 def transform(key_value
):
100 (key
, value
) = key_value
101 key
= keymap
.get(key
, key
)
102 hook
= typemap
.get(key
, lambda value
: value
)
103 if hook
is bool and value
in ("", "0"):
109 record
= dict(map(transform
, record
.items()))
110 for key
in frozenset(record
.keys()):
111 if record
[key
] == "":
117 @_functools.total_ordering
118 @_dataclasses.dataclass(eq
=True, frozen
=True)
121 def __new__(cls
, value
):
122 if isinstance(value
, str):
123 value
= int(value
, 0)
124 if not isinstance(value
, int):
125 raise ValueError(value
)
127 if value
.bit_length() > 64:
128 raise ValueError(value
)
130 return super().__new
__(cls
, value
)
133 return self
.__repr
__()
136 return f
"{self:0{self.bit_length()}b}"
138 def bit_length(self
):
139 if super().bit_length() > 32:
143 class Value(Integer
):
152 def __lt__(self
, other
):
153 if not isinstance(other
, Opcode
):
154 return NotImplemented
155 return ((self
.value
, self
.mask
) < (other
.value
, other
.mask
))
158 def pattern(value
, mask
, bit_length
):
159 for bit
in range(bit_length
):
160 if ((mask
& (1 << (bit_length
- bit
- 1))) == 0):
162 elif (value
& (1 << (bit_length
- bit
- 1))):
167 return "".join(pattern(self
.value
, self
.mask
, self
.value
.bit_length()))
169 def match(self
, key
):
170 return ((self
.value
& self
.mask
) == (key
& self
.mask
))
173 class IntegerOpcode(Opcode
):
174 def __init__(self
, value
):
175 if value
.startswith("0b"):
176 mask
= int(("1" * len(value
[2:])), 2)
180 value
= Opcode
.Value(value
)
181 mask
= Opcode
.Mask(mask
)
183 return super().__init
__(value
=value
, mask
=mask
)
186 class PatternOpcode(Opcode
):
187 def __init__(self
, pattern
):
188 if not isinstance(pattern
, str):
189 raise ValueError(pattern
)
191 (value
, mask
) = (0, 0)
192 for symbol
in pattern
:
193 if symbol
not in {"0", "1", "-"}:
194 raise ValueError(pattern
)
195 value |
= (symbol
== "1")
196 mask |
= (symbol
!= "-")
202 value
= Opcode
.Value(value
)
203 mask
= Opcode
.Mask(mask
)
205 return super().__init
__(value
=value
, mask
=mask
)
208 @_dataclasses.dataclass(eq
=True, frozen
=True)
210 class FlagsMeta(type):
225 class Flags(frozenset, metaclass
=FlagsMeta
):
226 def __new__(cls
, flags
=frozenset()):
227 flags
= frozenset(flags
)
228 diff
= (flags
- frozenset(cls
))
230 raise ValueError(flags
)
231 return super().__new
__(cls
, flags
)
235 flags
: Flags
= Flags()
237 function
: _Function
= _Function
.NONE
238 intop
: _MicrOp
= _MicrOp
.OP_ILLEGAL
239 in1
: _In1Sel
= _In1Sel
.RA
240 in2
: _In2Sel
= _In2Sel
.NONE
241 in3
: _In3Sel
= _In3Sel
.NONE
242 out
: _OutSel
= _OutSel
.NONE
243 cr_in
: _CRInSel
= _CRInSel
.NONE
244 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
245 cr_out
: _CROutSel
= _CROutSel
.NONE
246 cry_in
: _CryIn
= _CryIn
.ZERO
247 ldst_len
: _LDSTLen
= _LDSTLen
.NONE
248 upd
: _LDSTMode
= _LDSTMode
.NONE
249 Rc
: _RCOE
= _RCOE
.NONE
250 form
: _Form
= _Form
.NONE
252 unofficial
: bool = False
256 "internal op": "intop",
260 "ldst len": "ldst_len",
262 "CONDITIONS": "conditions",
265 def __lt__(self
, other
):
266 if not isinstance(other
, self
.__class
__):
267 return NotImplemented
268 lhs
= (self
.opcode
, self
.comment
)
269 rhs
= (other
.opcode
, other
.comment
)
273 def CSV(cls
, record
, opcode_cls
):
274 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
275 typemap
["opcode"] = opcode_cls
277 if record
["CR in"] == "BA_BB":
278 record
["cr_in"] = "BA"
279 record
["cr_in2"] = "BB"
283 for flag
in frozenset(PPCRecord
.Flags
):
284 if bool(record
.pop(flag
, "")):
286 record
["flags"] = PPCRecord
.Flags(flags
)
288 return dataclass(cls
, record
,
289 keymap
=PPCRecord
.__KEYMAP
,
294 return frozenset(self
.comment
.split("=")[-1].split("/"))
297 class PPCMultiRecord(tuple):
298 def __getattr__(self
, attr
):
300 raise AttributeError(attr
)
301 return getattr(self
[0], attr
)
304 @_dataclasses.dataclass(eq
=True, frozen
=True)
306 class ExtraMap(tuple):
308 @_dataclasses.dataclass(eq
=True, frozen
=True)
310 regtype
: _SVExtraRegType
= _SVExtraRegType
.NONE
311 reg
: _SVExtraReg
= _SVExtraReg
.NONE
314 return f
"{self.regtype.value}:{self.reg.name}"
316 def __new__(cls
, value
="0"):
317 if isinstance(value
, str):
318 def transform(value
):
319 (regtype
, reg
) = value
.split(":")
320 regtype
= _SVExtraRegType(regtype
)
321 reg
= _SVExtraReg(reg
)
322 return cls
.Entry(regtype
=regtype
, reg
=reg
)
327 value
= map(transform
, value
.split(";"))
329 return super().__new
__(cls
, value
)
332 return repr(list(self
))
334 def __new__(cls
, value
=tuple()):
338 return super().__new
__(cls
, map(cls
.Extra
, value
))
341 return repr({index
:self
[index
] for index
in range(0, 4)})
344 ptype
: _SVPType
= _SVPType
.NONE
345 etype
: _SVEType
= _SVEType
.NONE
346 msrc
: _SVMaskSrc
= _SVMaskSrc
.NO
# MASK_SRC is active
347 in1
: _In1Sel
= _In1Sel
.NONE
348 in2
: _In2Sel
= _In2Sel
.NONE
349 in3
: _In3Sel
= _In3Sel
.NONE
350 out
: _OutSel
= _OutSel
.NONE
351 out2
: _OutSel
= _OutSel
.NONE
352 cr_in
: _CRInSel
= _CRInSel
.NONE
353 cr_in2
: _CRIn2Sel
= _CRIn2Sel
.NONE
354 cr_out
: _CROutSel
= _CROutSel
.NONE
355 extra
: ExtraMap
= ExtraMap()
357 mode
: _SVMode
= _SVMode
.NORMAL
361 "CONDITIONS": "conditions",
370 def CSV(cls
, record
):
371 for key
in frozenset({
372 "in1", "in2", "in3", "CR in",
373 "out", "out2", "CR out",
379 if record
["CR in"] == "BA_BB":
380 record
["cr_in"] = "BA"
381 record
["cr_in2"] = "BB"
385 for idx
in range(0, 4):
386 extra
.append(record
.pop(f
"{idx}"))
388 record
["extra"] = cls
.ExtraMap(extra
)
390 return dataclass(cls
, record
, keymap
=cls
.__KEYMAP
)
392 @_functools.lru_cache(maxsize
=None)
393 def extra_idx(self
, key
):
401 if key
not in frozenset({
402 "in1", "in2", "in3", "cr_in", "cr_in2",
403 "out", "out2", "cr_out",
407 sel
= getattr(self
, key
)
408 if sel
is _CRInSel
.BA_BB
:
409 return _SVExtra
.Idx_1_2
410 reg
= _SVExtraReg(sel
)
411 if reg
is _SVExtraReg
.NONE
:
415 _SVExtraRegType
.SRC
: {},
416 _SVExtraRegType
.DST
: {},
418 for index
in range(0, 4):
419 for entry
in self
.extra
[index
]:
420 extra_map
[entry
.regtype
][entry
.reg
] = extra_idx
[index
]
422 for regtype
in (_SVExtraRegType
.SRC
, _SVExtraRegType
.DST
):
423 extra
= extra_map
[regtype
].get(reg
, _SVExtra
.NONE
)
424 if extra
is not _SVExtra
.NONE
:
429 extra_idx_in1
= property(_functools
.partial(extra_idx
, key
="in1"))
430 extra_idx_in2
= property(_functools
.partial(extra_idx
, key
="in2"))
431 extra_idx_in3
= property(_functools
.partial(extra_idx
, key
="in3"))
432 extra_idx_out
= property(_functools
.partial(extra_idx
, key
="out"))
433 extra_idx_out2
= property(_functools
.partial(extra_idx
, key
="out2"))
434 extra_idx_cr_in
= property(_functools
.partial(extra_idx
, key
="cr_in"))
435 extra_idx_cr_in2
= property(_functools
.partial(extra_idx
, key
="cr_in2"))
436 extra_idx_cr_out
= property(_functools
.partial(extra_idx
, key
="cr_out"))
438 @_functools.lru_cache(maxsize
=None)
439 def extra_reg(self
, key
):
440 return _SVExtraReg(getattr(self
, key
))
442 extra_reg_in1
= property(_functools
.partial(extra_reg
, key
="in1"))
443 extra_reg_in2
= property(_functools
.partial(extra_reg
, key
="in2"))
444 extra_reg_in3
= property(_functools
.partial(extra_reg
, key
="in3"))
445 extra_reg_out
= property(_functools
.partial(extra_reg
, key
="out"))
446 extra_reg_out2
= property(_functools
.partial(extra_reg
, key
="out2"))
447 extra_reg_cr_in
= property(_functools
.partial(extra_reg
, key
="cr_in"))
448 extra_reg_cr_in2
= property(_functools
.partial(extra_reg
, key
="cr_in2"))
449 extra_reg_cr_out
= property(_functools
.partial(extra_reg
, key
="cr_out"))
454 for idx
in range(0, 4):
455 for entry
in self
.svp64
.extra
[idx
]:
456 if entry
.regtype
is _SVExtraRegType
.DST
:
457 if regtype
is not None:
458 raise ValueError(self
.svp64
)
459 regtype
= _RegType(entry
.reg
)
460 if regtype
not in (_RegType
.CR_5BIT
, _RegType
.CR_3BIT
):
461 raise ValueError(self
.svp64
)
462 return (regtype
is _RegType
.CR_3BIT
)
466 def __init__(self
, value
=(0, 32)):
467 if isinstance(value
, str):
468 (start
, end
) = map(int, value
.split(":"))
471 if start
< 0 or end
< 0 or start
>= end
:
472 raise ValueError(value
)
477 return super().__init
__()
480 return (self
.__end
- self
.__start
+ 1)
483 return f
"[{self.__start}:{self.__end}]"
486 yield from range(self
.start
, (self
.end
+ 1))
488 def __reversed__(self
):
489 return tuple(reversed(tuple(self
)))
500 @_dataclasses.dataclass(eq
=True, frozen
=True)
502 class Mode(_enum
.Enum
):
503 INTEGER
= _enum
.auto()
504 PATTERN
= _enum
.auto()
507 def _missing_(cls
, value
):
508 if isinstance(value
, str):
509 return cls
[value
.upper()]
510 return super()._missing
_(value
)
513 def __new__(cls
, value
=None):
514 if isinstance(value
, str):
515 if value
.upper() == "NONE":
518 value
= int(value
, 0)
522 return super().__new
__(cls
, value
)
528 return (bin(self
) if self
else "None")
534 opcode
: IntegerOpcode
= None
535 priority
: Priority
= Priority
.NORMAL
537 def __lt__(self
, other
):
538 if not isinstance(other
, self
.__class
__):
539 return NotImplemented
540 return (self
.priority
< other
.priority
)
543 def CSV(cls
, record
):
544 typemap
= {field
.name
:field
.type for field
in _dataclasses
.fields(cls
)}
545 if record
["opcode"] == "NONE":
546 typemap
["opcode"] = lambda _
: None
548 return dataclass(cls
, record
, typemap
=typemap
)
552 def __init__(self
, items
):
553 if isinstance(items
, dict):
554 items
= items
.items()
557 (name
, bitrange
) = item
558 return (name
, tuple(bitrange
.values()))
560 self
.__mapping
= dict(map(transform
, items
))
562 return super().__init
__()
565 return repr(self
.__mapping
)
568 yield from self
.__mapping
.items()
570 def __contains__(self
, key
):
571 return self
.__mapping
.__contains
__(key
)
573 def __getitem__(self
, key
):
574 return self
.__mapping
.get(key
, None)
578 def __init__(self
, insn
, iterable
):
580 "b": {"target_addr": TargetAddrOperandLI
},
581 "ba": {"target_addr": TargetAddrOperandLI
},
582 "bl": {"target_addr": TargetAddrOperandLI
},
583 "bla": {"target_addr": TargetAddrOperandLI
},
584 "bc": {"target_addr": TargetAddrOperandBD
},
585 "bca": {"target_addr": TargetAddrOperandBD
},
586 "bcl": {"target_addr": TargetAddrOperandBD
},
587 "bcla": {"target_addr": TargetAddrOperandBD
},
588 "addpcis": {"D": DOperandDX
},
589 "fishmv": {"D": DOperandDX
},
590 "fmvis": {"D": DOperandDX
},
593 "SVi": NonZeroOperand
,
594 "SVd": NonZeroOperand
,
595 "SVxd": NonZeroOperand
,
596 "SVyd": NonZeroOperand
,
597 "SVzd": NonZeroOperand
,
599 "D": SignedImmediateOperand
,
603 "SIM": SignedOperand
,
604 "SVD": SignedOperand
,
605 "SVDS": SignedOperand
,
607 custom_immediates
= {
613 for operand
in iterable
:
617 (name
, value
) = operand
.split("=")
618 mapping
[name
] = (StaticOperand
, {
624 if name
.endswith(")"):
625 name
= name
.replace("(", " ").replace(")", "")
626 (immediate
, _
, name
) = name
.partition(" ")
630 if immediate
is not None:
631 cls
= custom_immediates
.get(immediate
, ImmediateOperand
)
633 if insn
in custom_insns
and name
in custom_insns
[insn
]:
634 cls
= custom_insns
[insn
][name
]
635 elif name
in custom_fields
:
636 cls
= custom_fields
[name
]
638 if name
in _RegType
.__members
__:
639 regtype
= _RegType
[name
]
640 if regtype
is _RegType
.GPR
:
642 elif regtype
is _RegType
.FPR
:
644 if regtype
is _RegType
.CR_5BIT
:
646 if regtype
is _RegType
.CR_3BIT
:
649 mapping
[name
] = (cls
, {"name": name
})
653 for (name
, (cls
, kwargs
)) in mapping
.items():
654 kwargs
= dict(kwargs
)
655 kwargs
["name"] = name
656 if issubclass(cls
, StaticOperand
):
657 static
.append((cls
, kwargs
))
658 elif issubclass(cls
, DynamicOperand
):
659 dynamic
.append((cls
, kwargs
))
661 raise ValueError(name
)
663 self
.__mapping
= mapping
664 self
.__static
= tuple(static
)
665 self
.__dynamic
= tuple(dynamic
)
667 return super().__init
__()
670 for (_
, items
) in self
.__mapping
.items():
671 (cls
, kwargs
) = items
675 return self
.__mapping
.__repr
__()
677 def __contains__(self
, key
):
678 return self
.__mapping
.__contains
__(key
)
680 def __getitem__(self
, key
):
681 return self
.__mapping
.__getitem
__(key
)
689 return self
.__dynamic
693 def __init__(self
, iterable
):
694 self
.__pcode
= tuple(iterable
)
695 return super().__init
__()
698 yield from self
.__pcode
701 return self
.__pcode
.__repr
__()
704 @_dataclasses.dataclass(eq
=True, frozen
=True)
705 class MarkdownRecord
:
710 @_functools.total_ordering
711 @_dataclasses.dataclass(eq
=True, frozen
=True)
718 svp64
: SVP64Record
= None
720 def __lt__(self
, other
):
721 if not isinstance(other
, Record
):
722 return NotImplemented
723 lhs
= (min(self
.opcodes
), self
.name
)
724 rhs
= (min(other
.opcodes
), other
.name
)
729 PO
= self
.section
.opcode
731 assert len(self
.ppc
) == 1
732 PO
= self
.ppc
[0].opcode
734 return POStaticOperand(record
=self
,
735 name
="PO", value
=int(PO
.value
), mask
=int(PO
.mask
))
741 PO
= self
.section
.opcode
747 return XOStaticOperand(record
=self
,
748 name
="XO", value
=0, mask
=0)
750 return XOStaticOperand(record
=self
,
751 name
="XO", value
=int(XO
.value
), mask
=int(XO
.mask
))
753 return tuple(dict.fromkeys(map(XO
, self
.ppc
)))
756 def static_operands(self
):
759 operands
.append(self
.PO
)
760 operands
.extend(self
.XO
)
762 for (cls
, kwargs
) in self
.mdwn
.operands
.static
:
763 operands
.append(cls(record
=self
, **kwargs
))
765 return tuple(operands
)
768 def dynamic_operands(self
):
771 for (cls
, kwargs
) in self
.mdwn
.operands
.dynamic
:
772 operands
.append(cls(record
=self
, **kwargs
))
774 return tuple(operands
)
779 if self
.svp64
is not None:
781 origin_value
= ([0] * bits
)
782 origin_mask
= ([0] * bits
)
784 for operand
in ((self
.PO
,) + tuple(self
.static_operands
)):
785 for (src
, dst
) in enumerate(reversed(operand
.span
)):
786 origin_value
[dst
] = int((operand
.value
& (1 << src
)) != 0)
790 value
= list(origin_value
)
791 mask
= list(origin_mask
)
792 for (src
, dst
) in enumerate(reversed(XO
.span
)):
793 value
[dst
] = int((XO
.value
& (1 << src
)) != 0)
796 value
= Opcode
.Value(int(("".join(map(str, value
))), 2))
797 mask
= Opcode
.Mask(int(("".join(map(str, mask
))), 2))
799 return Opcode(value
=value
, mask
=mask
)
801 return tuple(dict.fromkeys(map(opcode
, self
.XO
)))
803 def match(self
, key
):
804 for opcode
in self
.opcodes
:
805 if opcode
.match(key
):
812 return self
.svp64
.mode
832 if self
.svp64
is None:
838 return self
.ppc
.cr_in
842 return self
.ppc
.cr_in2
846 return self
.ppc
.cr_out
848 ptype
= property(lambda self
: self
.svp64
.ptype
)
849 etype
= property(lambda self
: self
.svp64
.etype
)
851 def extra_idx(self
, key
):
852 return self
.svp64
.extra_idx(key
)
854 extra_idx_in1
= property(lambda self
: self
.svp64
.extra_idx_in1
)
855 extra_idx_in2
= property(lambda self
: self
.svp64
.extra_idx_in2
)
856 extra_idx_in3
= property(lambda self
: self
.svp64
.extra_idx_in3
)
857 extra_idx_out
= property(lambda self
: self
.svp64
.extra_idx_out
)
858 extra_idx_out2
= property(lambda self
: self
.svp64
.extra_idx_out2
)
859 extra_idx_cr_in
= property(lambda self
: self
.svp64
.extra_idx_cr_in
)
860 extra_idx_cr_in2
= property(lambda self
: self
.svp64
.extra_idx_cr_in2
)
861 extra_idx_cr_out
= property(lambda self
: self
.svp64
.extra_idx_cr_out
)
863 def __contains__(self
, key
):
864 return self
.mdwn
.operands
.__contains
__(key
)
866 def __getitem__(self
, key
):
867 (cls
, kwargs
) = self
.mdwn
.operands
.__getitem
__(key
)
868 return cls(record
=self
, **kwargs
)
874 return self
["Rc"].value
877 @_dataclasses.dataclass(eq
=True, frozen
=True)
880 record
: Record
= _dataclasses
.field(repr=False)
882 def __post_init__(self
):
887 span
= self
.record
.fields
[self
.name
]
888 if self
.record
.svp64
is not None:
889 span
= tuple(map(lambda bit
: (bit
+ 32), span
))
892 def assemble(self
, value
, insn
):
894 if isinstance(value
, str):
895 value
= int(value
, 0)
897 raise ValueError("signed operands not allowed")
900 def disassemble(self
, insn
,
901 verbosity
=Verbosity
.NORMAL
, indent
=""):
902 raise NotImplementedError
905 @_dataclasses.dataclass(eq
=True, frozen
=True)
906 class DynamicOperand(Operand
):
907 def disassemble(self
, insn
,
908 verbosity
=Verbosity
.NORMAL
, indent
=""):
912 if verbosity
>= Verbosity
.VERBOSE
:
913 span
= map(str, span
)
914 yield f
"{indent}{self.name}"
915 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
916 yield f
"{indent}{indent}{', '.join(span)}"
918 yield str(int(value
))
921 @_dataclasses.dataclass(eq
=True, frozen
=True)
922 class SignedOperand(DynamicOperand
):
923 def assemble(self
, value
, insn
):
924 if isinstance(value
, str):
925 value
= int(value
, 0)
926 return super().assemble(value
=value
, insn
=insn
)
928 def disassemble(self
, insn
,
929 verbosity
=Verbosity
.NORMAL
, indent
=""):
933 if verbosity
>= Verbosity
.VERBOSE
:
934 span
= map(str, span
)
935 yield f
"{indent}{self.name}"
936 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
937 yield f
"{indent}{indent}{', '.join(span)}"
939 yield str(value
.to_signed_int())
942 @_dataclasses.dataclass(eq
=True, frozen
=True)
943 class StaticOperand(Operand
):
946 def assemble(self
, insn
):
947 return super().assemble(value
=self
.value
, insn
=insn
)
949 def disassemble(self
, insn
,
950 verbosity
=Verbosity
.NORMAL
, indent
=""):
954 if verbosity
>= Verbosity
.VERBOSE
:
955 span
= map(str, span
)
956 yield f
"{indent}{self.name}"
957 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
958 yield f
"{indent}{indent}{', '.join(span)}"
960 yield str(int(value
))
963 @_dataclasses.dataclass(eq
=True, frozen
=True)
964 class POStaticOperand(StaticOperand
):
969 span
= tuple(range(0, 6))
970 if self
.record
.svp64
is not None:
971 span
= tuple(map(lambda bit
: (bit
+ 32), span
))
975 @_dataclasses.dataclass(eq
=True, frozen
=True)
976 class XOStaticOperand(StaticOperand
):
979 def __post_init__(self
):
980 if self
.record
.section
.opcode
is None:
981 assert self
.value
== 0
982 assert self
.mask
== 0
983 object.__setattr
__(self
, "span", ())
986 bits
= self
.record
.section
.bitsel
987 value
= _SelectableInt(value
=self
.value
, bits
=len(bits
))
988 span
= dict(zip(bits
, range(len(bits
))))
989 span_rev
= {value
:key
for (key
, value
) in span
.items()}
991 # This part is tricky: we could have used self.record.static_operands,
992 # but this would cause an infinite recursion, since this code is called
993 # from the self.record.static_operands method already.
995 operands
.extend(self
.record
.mdwn
.operands
.static
)
996 operands
.extend(self
.record
.mdwn
.operands
.dynamic
)
997 for (cls
, kwargs
) in operands
:
998 operand
= cls(record
=self
.record
, **kwargs
)
999 for idx
in operand
.span
:
1000 rev
= span
.pop(idx
, None)
1002 span_rev
.pop(rev
, None)
1004 # This part is simpler: we drop bits which are not in the mask.
1005 for bit
in tuple(span
.values()):
1006 rev
= (len(bits
) - bit
- 1)
1007 if ((self
.mask
& (1 << bit
)) == 0):
1008 idx
= span_rev
.pop(rev
, None)
1012 value
= int(_selectconcat(*(value
[bit
] for bit
in span
.values())))
1013 span
= tuple(span
.keys())
1014 if self
.record
.svp64
is not None:
1015 span
= tuple(map(lambda bit
: (bit
+ 32), span
))
1017 object.__setattr
__(self
, "value", value
)
1018 object.__setattr
__(self
, "span", span
)
1020 return super().__post
_init
__()
1023 @_dataclasses.dataclass(eq
=True, frozen
=True)
1024 class ImmediateOperand(DynamicOperand
):
1028 @_dataclasses.dataclass(eq
=True, frozen
=True)
1029 class SignedImmediateOperand(SignedOperand
, ImmediateOperand
):
1033 @_dataclasses.dataclass(eq
=True, frozen
=True)
1034 class NonZeroOperand(DynamicOperand
):
1035 def assemble(self
, value
, insn
):
1036 if isinstance(value
, str):
1037 value
= int(value
, 0)
1038 if not isinstance(value
, int):
1039 raise ValueError("non-integer operand")
1041 return super().assemble(value
=value
, insn
=insn
)
1043 def disassemble(self
, insn
,
1044 verbosity
=Verbosity
.NORMAL
, indent
=""):
1048 if verbosity
>= Verbosity
.VERBOSE
:
1049 span
= map(str, span
)
1050 yield f
"{indent}{self.name}"
1051 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1052 yield f
"{indent}{indent}{', '.join(span)}"
1054 yield str(int(value
) + 1)
1057 @_dataclasses.dataclass(eq
=True, frozen
=True)
1058 class ExtendableOperand(DynamicOperand
):
1059 def sv_spec_enter(self
, value
, span
):
1060 return (value
, span
)
1062 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1063 return (value
, span
)
1065 def spec(self
, insn
):
1069 span
= tuple(map(str, span
))
1071 if isinstance(insn
, SVP64Instruction
):
1072 (origin_value
, origin_span
) = (value
, span
)
1073 (value
, span
) = self
.sv_spec_enter(value
=value
, span
=span
)
1075 extra_idx
= self
.extra_idx
1076 if extra_idx
is _SVExtra
.NONE
:
1077 return (vector
, value
, span
)
1079 if self
.record
.etype
is _SVEType
.EXTRA3
:
1080 spec
= insn
.prefix
.rm
.extra3
[extra_idx
]
1081 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1082 spec
= insn
.prefix
.rm
.extra2
[extra_idx
]
1084 raise ValueError(self
.record
.etype
)
1087 vector
= bool(spec
[0])
1088 spec_span
= spec
.__class
__
1089 if self
.record
.etype
is _SVEType
.EXTRA3
:
1090 spec_span
= tuple(map(str, spec_span
[1, 2]))
1092 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1093 spec_span
= tuple(map(str, spec_span
[1,]))
1094 spec
= _SelectableInt(value
=spec
[1].value
, bits
=2)
1097 spec_span
= (spec_span
+ ("{0}",))
1099 spec_span
= (("{0}",) + spec_span
)
1101 raise ValueError(self
.record
.etype
)
1103 vector_shift
= (2 + (5 - value
.bits
))
1104 scalar_shift
= value
.bits
1105 spec_shift
= (5 - value
.bits
)
1107 bits
= (len(span
) + len(spec_span
))
1108 value
= _SelectableInt(value
=value
.value
, bits
=bits
)
1109 spec
= _SelectableInt(value
=spec
.value
, bits
=bits
)
1111 value
= ((value
<< vector_shift
) |
(spec
<< spec_shift
))
1112 span
= (span
+ spec_span
+ ((spec_shift
* ("{0}",))))
1114 value
= ((spec
<< scalar_shift
) | value
)
1115 span
= ((spec_shift
* ("{0}",)) + spec_span
+ span
)
1117 (value
, span
) = self
.sv_spec_leave(value
=value
, span
=span
,
1118 origin_value
=origin_value
, origin_span
=origin_span
)
1120 return (vector
, value
, span
)
1123 def extra_reg(self
):
1124 return _SVExtraReg(self
.name
)
1127 def extra_idx(self
):
1128 for key
in frozenset({
1129 "in1", "in2", "in3", "cr_in", "cr_in2",
1130 "out", "out2", "cr_out",
1132 extra_reg
= self
.record
.svp64
.extra_reg(key
=key
)
1133 if extra_reg
is self
.extra_reg
:
1134 return self
.record
.extra_idx(key
=key
)
1136 return _SVExtra
.NONE
1138 def remap(self
, value
, vector
):
1139 raise NotImplementedError
1141 def assemble(self
, value
, insn
, prefix
):
1144 if isinstance(value
, str):
1145 value
= value
.lower()
1146 if value
.startswith("%"):
1148 if value
.startswith("*"):
1149 if not isinstance(insn
, SVP64Instruction
):
1150 raise ValueError(value
)
1153 if value
.startswith(prefix
):
1154 value
= value
[len(prefix
):]
1155 value
= int(value
, 0)
1157 if isinstance(insn
, SVP64Instruction
):
1158 (value
, extra
) = self
.remap(value
=value
, vector
=vector
)
1160 extra_idx
= self
.extra_idx
1161 if extra_idx
is _SVExtra
.NONE
:
1162 raise ValueError(self
.record
)
1164 if self
.record
.etype
is _SVEType
.EXTRA3
:
1165 insn
.prefix
.rm
.extra3
[extra_idx
] = extra
1166 elif self
.record
.etype
is _SVEType
.EXTRA2
:
1167 insn
.prefix
.rm
.extra2
[extra_idx
] = extra
1169 raise ValueError(self
.record
.etype
)
1171 return super().assemble(value
=value
, insn
=insn
)
1173 return super().assemble(value
=value
, insn
=insn
)
1175 def disassemble(self
, insn
,
1176 verbosity
=Verbosity
.NORMAL
, prefix
="", indent
=""):
1177 (vector
, value
, span
) = self
.spec(insn
=insn
)
1179 if verbosity
>= Verbosity
.VERBOSE
:
1180 mode
= "vector" if vector
else "scalar"
1181 yield f
"{indent}{self.name} ({mode})"
1182 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1183 yield f
"{indent}{indent}{', '.join(span)}"
1184 if isinstance(insn
, SVP64Instruction
):
1185 extra_idx
= self
.extra_idx
1186 if self
.record
.etype
is _SVEType
.NONE
:
1187 yield f
"{indent}{indent}extra[none]"
1189 etype
= repr(self
.record
.etype
).lower()
1190 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1192 vector
= "*" if vector
else ""
1193 yield f
"{vector}{prefix}{int(value)}"
1196 @_dataclasses.dataclass(eq
=True, frozen
=True)
1197 class SimpleRegisterOperand(ExtendableOperand
):
1198 def remap(self
, value
, vector
):
1200 extra
= (value
& 0b11)
1201 value
= (value
>> 2)
1203 extra
= (value
>> 5)
1204 value
= (value
& 0b11111)
1206 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
1207 # (and shrink to a single bit if ok)
1208 if self
.record
.etype
is _SVEType
.EXTRA2
:
1210 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
1211 assert (extra
& 0b01) == 0, \
1212 ("vector field %s cannot fit into EXTRA2" % value
)
1213 extra
= (0b10 |
(extra
>> 1))
1215 # range is r0-r63 in increments of 1
1216 assert (extra
>> 1) == 0, \
1217 ("scalar GPR %d cannot fit into EXTRA2" % value
)
1219 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1221 # EXTRA3 vector bit needs marking
1224 raise ValueError(self
.record
.etype
)
1226 return (value
, extra
)
1229 @_dataclasses.dataclass(eq
=True, frozen
=True)
1230 class GPROperand(SimpleRegisterOperand
):
1231 def assemble(self
, value
, insn
):
1232 return super().assemble(value
=value
, insn
=insn
, prefix
="r")
1234 def disassemble(self
, insn
,
1235 verbosity
=Verbosity
.NORMAL
, indent
=""):
1236 prefix
= "" if (verbosity
<= Verbosity
.SHORT
) else "r"
1237 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1238 verbosity
=verbosity
, indent
=indent
)
1241 @_dataclasses.dataclass(eq
=True, frozen
=True)
1242 class FPROperand(SimpleRegisterOperand
):
1243 def assemble(self
, value
, insn
):
1244 return super().assemble(value
=value
, insn
=insn
, prefix
="f")
1246 def disassemble(self
, insn
,
1247 verbosity
=Verbosity
.NORMAL
, indent
=""):
1248 prefix
= "" if (verbosity
<= Verbosity
.SHORT
) else "f"
1249 yield from super().disassemble(prefix
=prefix
, insn
=insn
,
1250 verbosity
=verbosity
, indent
=indent
)
1253 @_dataclasses.dataclass(eq
=True, frozen
=True)
1254 class ConditionRegisterFieldOperand(ExtendableOperand
):
1255 def pattern(name_pattern
):
1256 (name
, pattern
) = name_pattern
1257 return (name
, _re
.compile(f
"^{pattern}$", _re
.S
))
1266 CR
= r
"(?:CR|cr)([0-9]+)"
1268 BIT
= rf
"({'|'.join(CONDS.keys())})"
1269 LBIT
= fr
"{BIT}\s*\+\s*" # BIT+
1270 RBIT
= fr
"\s*\+\s*{BIT}" # +BIT
1271 CRN
= fr
"{CR}\s*\*\s*{N}" # CR*N
1272 NCR
= fr
"{N}\s*\*\s*{CR}" # N*CR
1273 XCR
= fr
"{CR}\.{BIT}"
1274 PATTERNS
= tuple(map(pattern
, (
1279 ("BIT+CR", (LBIT
+ CR
)),
1280 ("CR+BIT", (CR
+ RBIT
)),
1281 ("BIT+CR*N", (LBIT
+ CRN
)),
1282 ("CR*N+BIT", (CRN
+ RBIT
)),
1283 ("BIT+N*CR", (LBIT
+ NCR
)),
1284 ("N*CR+BIT", (NCR
+ RBIT
)),
1287 def remap(self
, value
, vector
, regtype
):
1288 if regtype
is _RegType
.CR_5BIT
:
1289 subvalue
= (value
& 0x3)
1293 extra
= (value
& 0xf)
1296 extra
= (value
>> 3)
1299 if self
.record
.etype
is _SVEType
.EXTRA2
:
1301 assert (extra
& 0x7) == 0, \
1302 "vector CR cannot fit into EXTRA2"
1303 extra
= (0x2 |
(extra
>> 3))
1305 assert (extra
>> 1) == 0, \
1306 "scalar CR cannot fit into EXTRA2"
1308 elif self
.record
.etype
is _SVEType
.EXTRA3
:
1310 assert (extra
& 0x3) == 0, \
1311 "vector CR cannot fit into EXTRA3"
1312 extra
= (0x4 |
(extra
>> 2))
1314 assert (extra
>> 2) == 0, \
1315 "scalar CR cannot fit into EXTRA3"
1318 if regtype
is _RegType
.CR_5BIT
:
1319 value
= ((value
<< 2) | subvalue
)
1321 return (value
, extra
)
1323 def assemble(self
, value
, insn
):
1324 if isinstance(value
, str):
1327 if value
.startswith("*"):
1328 if not isinstance(insn
, SVP64Instruction
):
1329 raise ValueError(value
)
1333 for (name
, pattern
) in reversed(self
.__class
__.PATTERNS
):
1334 match
= pattern
.match(value
)
1335 if match
is not None:
1336 keys
= name
.replace("+", "_").replace("*", "_").split("_")
1337 values
= match
.groups()
1338 match
= dict(zip(keys
, values
))
1339 CR
= int(match
["CR"])
1343 N
= int(match
.get("N", "1"))
1344 BIT
= self
.__class
__.CONDS
[match
.get("BIT", "lt")]
1345 value
= ((CR
* N
) + BIT
)
1348 return super().assemble(value
=value
, insn
=insn
, prefix
="cr")
1350 def disassemble(self
, insn
,
1351 verbosity
=Verbosity
.NORMAL
, prefix
="", indent
=""):
1352 (vector
, value
, span
) = self
.spec(insn
=insn
)
1354 if verbosity
>= Verbosity
.VERBOSE
:
1355 mode
= "vector" if vector
else "scalar"
1356 yield f
"{indent}{self.name} ({mode})"
1357 yield f
"{indent}{indent}{int(value):0{value.bits}b}"
1358 yield f
"{indent}{indent}{', '.join(span)}"
1359 if isinstance(insn
, SVP64Instruction
):
1360 extra_idx
= self
.extra_idx
1361 if self
.record
.etype
is _SVEType
.NONE
:
1362 yield f
"{indent}{indent}extra[none]"
1364 etype
= repr(self
.record
.etype
).lower()
1365 yield f
"{indent}{indent}{etype}{extra_idx!r}"
1367 vector
= "*" if vector
else ""
1368 cr
= int(value
>> 2)
1370 cond
= ("lt", "gt", "eq", "so")[cc
]
1371 if verbosity
>= Verbosity
.NORMAL
:
1373 if isinstance(insn
, SVP64Instruction
):
1374 yield f
"{vector}cr{cr}.{cond}"
1376 yield f
"4*cr{cr}+{cond}"
1380 yield f
"{vector}{prefix}{int(value)}"
1383 @_dataclasses.dataclass(eq
=True, frozen
=True)
1384 class CR3Operand(ConditionRegisterFieldOperand
):
1385 def remap(self
, value
, vector
):
1386 return super().remap(value
=value
, vector
=vector
,
1387 regtype
=_RegType
.CR_3BIT
)
1390 @_dataclasses.dataclass(eq
=True, frozen
=True)
1391 class CR5Operand(ConditionRegisterFieldOperand
):
1392 def remap(self
, value
, vector
):
1393 return super().remap(value
=value
, vector
=vector
,
1394 regtype
=_RegType
.CR_5BIT
)
1396 def sv_spec_enter(self
, value
, span
):
1397 value
= _SelectableInt(value
=(value
.value
>> 2), bits
=3)
1398 return (value
, span
)
1400 def sv_spec_leave(self
, value
, span
, origin_value
, origin_span
):
1401 value
= _selectconcat(value
, origin_value
[3:5])
1403 return (value
, span
)
1406 @_dataclasses.dataclass(eq
=True, frozen
=True)
1407 class EXTSOperand(DynamicOperand
):
1408 field
: str # real name to report
1409 nz
: int = 0 # number of zeros
1410 fmt
: str = "d" # integer formatter
1412 def __post_init__(self
):
1414 object.__setattr
__(self
, "field", self
.name
)
1418 span
= self
.record
.fields
[self
.field
]
1419 if self
.record
.svp64
is not None:
1420 span
= tuple(map(lambda bit
: (bit
+ 32), span
))
1423 def disassemble(self
, insn
,
1424 verbosity
=Verbosity
.NORMAL
, indent
=""):
1428 if verbosity
>= Verbosity
.VERBOSE
:
1429 span
= (tuple(map(str, span
)) + (("{0}",) * self
.nz
))
1430 zeros
= ("0" * self
.nz
)
1431 hint
= f
"{self.name} = EXTS({self.field} || {zeros})"
1432 yield f
"{indent * 1}{hint}"
1433 yield f
"{indent * 2}{self.field}"
1434 yield f
"{indent * 3}{int(value):0{value.bits}b}{zeros}"
1435 yield f
"{indent * 3}{', '.join(span)}"
1437 value
= _selectconcat(value
,
1438 _SelectableInt(value
=0, bits
=self
.nz
)).to_signed_int()
1439 yield f
"{value:{self.fmt}}"
1442 @_dataclasses.dataclass(eq
=True, frozen
=True)
1443 class TargetAddrOperand(EXTSOperand
):
1448 @_dataclasses.dataclass(eq
=True, frozen
=True)
1449 class TargetAddrOperandLI(TargetAddrOperand
):
1453 @_dataclasses.dataclass(eq
=True, frozen
=True)
1454 class TargetAddrOperandBD(TargetAddrOperand
):
1458 @_dataclasses.dataclass(eq
=True, frozen
=True)
1459 class EXTSOperandDS(EXTSOperand
, ImmediateOperand
):
1464 @_dataclasses.dataclass(eq
=True, frozen
=True)
1465 class EXTSOperandDQ(EXTSOperand
, ImmediateOperand
):
1470 @_dataclasses.dataclass(eq
=True, frozen
=True)
1471 class DOperandDX(SignedOperand
):
1474 cls
= lambda name
: DynamicOperand(record
=self
.record
, name
=name
)
1475 operands
= map(cls
, ("d0", "d1", "d2"))
1476 spans
= map(lambda operand
: operand
.span
, operands
)
1477 span
= sum(spans
, tuple())
1478 if self
.record
.svp64
is not None:
1479 span
= tuple(map(lambda bit
: (bit
+ 32), span
))
1482 def disassemble(self
, insn
,
1483 verbosity
=Verbosity
.NORMAL
, indent
=""):
1487 if verbosity
>= Verbosity
.VERBOSE
:
1494 for (subname
, subspan
) in mapping
.items():
1495 operand
= DynamicOperand(name
=subname
)
1498 span
= map(str, span
)
1499 yield f
"{indent}{indent}{operand.name} = D{subspan}"
1500 yield f
"{indent}{indent}{indent}{int(value):0{value.bits}b}"
1501 yield f
"{indent}{indent}{indent}{', '.join(span)}"
1503 yield str(value
.to_signed_int())
1506 class Instruction(_Mapping
):
1508 def integer(cls
, value
=0, bits
=None, byteorder
="little"):
1509 if isinstance(value
, (int, bytes
)) and not isinstance(bits
, int):
1510 raise ValueError(bits
)
1512 if isinstance(value
, bytes
):
1513 if ((len(value
) * 8) != bits
):
1514 raise ValueError(f
"bit length mismatch")
1515 value
= int.from_bytes(value
, byteorder
=byteorder
)
1517 if isinstance(value
, int):
1518 value
= _SelectableInt(value
=value
, bits
=bits
)
1519 elif isinstance(value
, Instruction
):
1520 value
= value
.storage
1522 if not isinstance(value
, _SelectableInt
):
1523 raise ValueError(value
)
1526 if len(value
) != bits
:
1527 raise ValueError(value
)
1529 value
= _SelectableInt(value
=value
, bits
=bits
)
1531 return cls(storage
=value
)
1534 return hash(int(self
))
1536 def __getitem__(self
, key
):
1537 return self
.storage
.__getitem
__(key
)
1539 def __setitem__(self
, key
, value
):
1540 return self
.storage
.__setitem
__(key
, value
)
1542 def bytes(self
, byteorder
="little"):
1543 nr_bytes
= (len(self
.__class
__) // 8)
1544 return int(self
).to_bytes(nr_bytes
, byteorder
=byteorder
)
1546 def record(self
, db
):
1549 raise KeyError(self
)
1552 def spec(self
, db
, prefix
):
1553 record
= self
.record(db
=db
)
1555 dynamic_operands
= tuple(map(_operator
.itemgetter(0),
1556 self
.dynamic_operands(db
=db
)))
1558 static_operands
= []
1559 for (name
, value
) in self
.static_operands(db
=db
):
1560 static_operands
.append(f
"{name}={value}")
1563 if dynamic_operands
:
1565 operands
+= ",".join(dynamic_operands
)
1568 operands
+= " ".join(static_operands
)
1570 return f
"{prefix}{record.name}{operands}"
1572 def dynamic_operands(self
, db
, verbosity
=Verbosity
.NORMAL
):
1573 record
= self
.record(db
=db
)
1578 for operand
in record
.dynamic_operands
:
1580 value
= " ".join(operand
.disassemble(insn
=self
,
1581 verbosity
=min(verbosity
, Verbosity
.NORMAL
)))
1583 name
= f
"{imm_name}({name})"
1584 value
= f
"{imm_value}({value})"
1586 if isinstance(operand
, ImmediateOperand
):
1593 def static_operands(self
, db
):
1594 record
= self
.record(db
=db
)
1595 for operand
in record
.static_operands
:
1596 yield (operand
.name
, operand
.value
)
1599 def assemble(cls
, db
, opcode
, arguments
=None):
1600 raise NotImplementedError(f
"{cls.__name__}.assemble")
1602 def disassemble(self
, db
,
1604 verbosity
=Verbosity
.NORMAL
):
1605 raise NotImplementedError
1608 class WordInstruction(Instruction
):
1609 _
: _Field
= range(0, 32)
1610 PO
: _Field
= range(0, 6)
1613 def integer(cls
, value
, byteorder
="little"):
1614 return super().integer(bits
=32, value
=value
, byteorder
=byteorder
)
1619 for idx
in range(32):
1620 bit
= int(self
[idx
])
1622 return "".join(map(str, bits
))
1625 def assemble(cls
, db
, opcode
, arguments
=None):
1626 if arguments
is None:
1630 insn
= cls
.integer(value
=0)
1631 for operand
in record
.static_operands
:
1632 operand
.assemble(insn
=insn
)
1634 dynamic_operands
= tuple(record
.dynamic_operands
)
1635 if len(dynamic_operands
) != len(arguments
):
1636 raise ValueError("operands count mismatch")
1637 for (value
, operand
) in zip(arguments
, dynamic_operands
):
1638 operand
.assemble(value
=value
, insn
=insn
)
1642 def disassemble(self
, db
,
1644 verbosity
=Verbosity
.NORMAL
):
1645 if verbosity
<= Verbosity
.SHORT
:
1648 blob
= self
.bytes(byteorder
=byteorder
)
1649 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
1654 yield f
"{blob}.long 0x{int(self):08x}"
1657 operands
= tuple(map(_operator
.itemgetter(1),
1658 self
.dynamic_operands(db
=db
, verbosity
=verbosity
)))
1660 operands
= ",".join(operands
)
1661 yield f
"{blob}{record.name} {operands}"
1663 yield f
"{blob}{record.name}"
1665 if verbosity
>= Verbosity
.VERBOSE
:
1667 binary
= self
.binary
1668 spec
= self
.spec(db
=db
, prefix
="")
1669 yield f
"{indent}spec"
1670 yield f
"{indent}{indent}{spec}"
1671 yield f
"{indent}pcode"
1672 for stmt
in record
.mdwn
.pcode
:
1673 yield f
"{indent}{indent}{stmt}"
1674 yield f
"{indent}binary"
1675 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
1676 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
1677 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
1678 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
1679 yield f
"{indent}opcodes"
1680 for opcode
in record
.opcodes
:
1681 yield f
"{indent}{indent}{opcode!r}"
1682 for (cls
, kwargs
) in record
.mdwn
.operands
:
1683 operand
= cls(record
=record
, **kwargs
)
1684 yield from operand
.disassemble(insn
=self
,
1685 verbosity
=verbosity
, indent
=indent
)
1689 class PrefixedInstruction(Instruction
):
1690 class Prefix(WordInstruction
.remap(range(0, 32))):
1693 class Suffix(WordInstruction
.remap(range(32, 64))):
1696 _
: _Field
= range(64)
1702 def integer(cls
, value
, byteorder
="little"):
1703 return super().integer(bits
=64, value
=value
, byteorder
=byteorder
)
1706 def pair(cls
, prefix
=0, suffix
=0, byteorder
="little"):
1707 def transform(value
):
1708 return WordInstruction
.integer(value
=value
,
1709 byteorder
=byteorder
)[0:32]
1711 (prefix
, suffix
) = map(transform
, (prefix
, suffix
))
1712 value
= _selectconcat(prefix
, suffix
)
1714 return super().integer(bits
=64, value
=value
)
1717 class Mode(_Mapping
):
1718 _
: _Field
= range(0, 5)
1719 sel
: _Field
= (0, 1)
1722 class Extra(_Mapping
):
1723 _
: _Field
= range(0, 9)
1726 class Extra2(Extra
):
1727 idx0
: _Field
= range(0, 2)
1728 idx1
: _Field
= range(2, 4)
1729 idx2
: _Field
= range(4, 6)
1730 idx3
: _Field
= range(6, 8)
1732 def __getitem__(self
, key
):
1738 _SVExtra
.Idx0
: self
.idx0
,
1739 _SVExtra
.Idx1
: self
.idx1
,
1740 _SVExtra
.Idx2
: self
.idx2
,
1741 _SVExtra
.Idx3
: self
.idx3
,
1744 def __setitem__(self
, key
, value
):
1745 self
[key
].assign(value
)
1748 class Extra3(Extra
):
1749 idx0
: _Field
= range(0, 3)
1750 idx1
: _Field
= range(3, 6)
1751 idx2
: _Field
= range(6, 9)
1753 def __getitem__(self
, key
):
1758 _SVExtra
.Idx0
: self
.idx0
,
1759 _SVExtra
.Idx1
: self
.idx1
,
1760 _SVExtra
.Idx2
: self
.idx2
,
1763 def __setitem__(self
, key
, value
):
1764 self
[key
].assign(value
)
1767 class BaseRM(_Mapping
):
1768 _
: _Field
= range(24)
1769 mmode
: _Field
= (0,)
1770 mask
: _Field
= range(1, 4)
1771 elwidth
: _Field
= range(4, 6)
1772 ewsrc
: _Field
= range(6, 8)
1773 subvl
: _Field
= range(8, 10)
1774 mode
: Mode
.remap(range(19, 24))
1775 smask
: _Field
= range(16, 19)
1776 extra
: Extra
.remap(range(10, 19))
1777 extra2
: Extra2
.remap(range(10, 19))
1778 extra3
: Extra3
.remap(range(10, 19))
1780 def specifiers(self
, record
):
1781 subvl
= int(self
.subvl
)
1789 def disassemble(self
, verbosity
=Verbosity
.NORMAL
):
1790 if verbosity
>= Verbosity
.VERBOSE
:
1792 for (name
, span
) in self
.traverse(path
="RM"):
1793 value
= self
.storage
[span
]
1795 yield f
"{indent}{int(value):0{value.bits}b}"
1796 yield f
"{indent}{', '.join(map(str, span))}"
1799 class FFPRRc1BaseRM(BaseRM
):
1800 def specifiers(self
, record
, mode
):
1801 inv
= _SelectableInt(value
=int(self
.inv
), bits
=1)
1802 CR
= _SelectableInt(value
=int(self
.CR
), bits
=2)
1803 mask
= int(_selectconcat(CR
, inv
))
1804 predicate
= PredicateBaseRM
.predicate(True, mask
)
1805 yield f
"{mode}={predicate}"
1807 yield from super().specifiers(record
=record
)
1810 class FFPRRc0BaseRM(BaseRM
):
1811 def specifiers(self
, record
, mode
):
1813 inv
= "~" if self
.inv
else ""
1814 yield f
"{mode}={inv}RC1"
1816 yield from super().specifiers(record
=record
)
1819 class SatBaseRM(BaseRM
):
1820 def specifiers(self
, record
):
1826 yield from super().specifiers(record
=record
)
1829 class ZZBaseRM(BaseRM
):
1830 def specifiers(self
, record
):
1834 yield from super().specifiers(record
=record
)
1837 class ZZCombinedBaseRM(BaseRM
):
1838 def specifiers(self
, record
):
1839 if self
.sz
and self
.dz
:
1846 yield from super().specifiers(record
=record
)
1849 class DZBaseRM(BaseRM
):
1850 def specifiers(self
, record
):
1854 yield from super().specifiers(record
=record
)
1857 class SZBaseRM(BaseRM
):
1858 def specifiers(self
, record
):
1862 yield from super().specifiers(record
=record
)
1865 class MRBaseRM(BaseRM
):
1866 def specifiers(self
, record
):
1872 yield from super().specifiers(record
=record
)
1875 class ElsBaseRM(BaseRM
):
1876 def specifiers(self
, record
):
1880 yield from super().specifiers(record
=record
)
1883 class WidthBaseRM(BaseRM
):
1885 def width(FP
, width
):
1894 width
= ("fp" + width
)
1897 def specifiers(self
, record
):
1898 # elwidths: use "w=" if same otherwise dw/sw
1899 # FIXME this should consider FP instructions
1901 dw
= WidthBaseRM
.width(FP
, int(self
.elwidth
))
1902 sw
= WidthBaseRM
.width(FP
, int(self
.ewsrc
))
1911 yield from super().specifiers(record
=record
)
1914 class PredicateBaseRM(BaseRM
):
1916 def predicate(CR
, mask
):
1919 (False, 0b001): "1<<r3",
1920 (False, 0b010): "r3",
1921 (False, 0b011): "~r3",
1922 (False, 0b100): "r10",
1923 (False, 0b101): "~r10",
1924 (False, 0b110): "r30",
1925 (False, 0b111): "~r30",
1927 (True, 0b000): "lt",
1928 (True, 0b001): "ge",
1929 (True, 0b010): "gt",
1930 (True, 0b011): "le",
1931 (True, 0b100): "eq",
1932 (True, 0b101): "ne",
1933 (True, 0b110): "so",
1934 (True, 0b111): "ns",
1937 def specifiers(self
, record
):
1938 # predication - single and twin
1939 # use "m=" if same otherwise sm/dm
1940 CR
= (int(self
.mmode
) == 1)
1941 mask
= int(self
.mask
)
1942 sm
= dm
= PredicateBaseRM
.predicate(CR
, mask
)
1943 if record
.svp64
.ptype
is _SVPType
.P2
:
1944 smask
= int(self
.smask
)
1945 sm
= PredicateBaseRM
.predicate(CR
, smask
)
1954 yield from super().specifiers(record
=record
)
1957 class PredicateWidthBaseRM(WidthBaseRM
, PredicateBaseRM
):
1961 class SEABaseRM(BaseRM
):
1962 def specifiers(self
, record
):
1966 yield from super().specifiers(record
=record
)
1969 class VLiBaseRM(BaseRM
):
1970 def specifiers(self
, record
):
1974 yield from super().specifiers(record
=record
)
1977 class NormalBaseRM(PredicateWidthBaseRM
):
1980 https://libre-soc.org/openpower/sv/normal/
1985 class NormalSimpleRM(ZZCombinedBaseRM
, NormalBaseRM
):
1986 """normal: simple mode"""
1990 def specifiers(self
, record
):
1991 yield from super().specifiers(record
=record
)
1994 class NormalMRRM(MRBaseRM
, NormalBaseRM
):
1995 """normal: scalar reduce mode (mapreduce), SUBVL=1"""
1999 class NormalFFRc1RM(FFPRRc1BaseRM
, NormalBaseRM
):
2000 """normal: Rc=1: ffirst CR sel"""
2002 CR
: BaseRM
.mode
[3, 4]
2004 def specifiers(self
, record
):
2005 yield from super().specifiers(record
=record
, mode
="ff")
2008 class NormalFFRc0RM(FFPRRc0BaseRM
, VLiBaseRM
, NormalBaseRM
):
2009 """normal: Rc=0: ffirst z/nonz"""
2014 def specifiers(self
, record
):
2015 yield from super().specifiers(record
=record
, mode
="ff")
2018 class NormalSatRM(SatBaseRM
, ZZCombinedBaseRM
, NormalBaseRM
):
2019 """normal: sat mode: N=0/1 u/s, SUBVL=1"""
2025 class NormalPRRc1RM(FFPRRc1BaseRM
, NormalBaseRM
):
2026 """normal: Rc=1: pred-result CR sel"""
2028 CR
: BaseRM
.mode
[3, 4]
2030 def specifiers(self
, record
):
2031 yield from super().specifiers(record
=record
, mode
="pr")
2034 class NormalPRRc0RM(FFPRRc0BaseRM
, ZZBaseRM
, NormalBaseRM
):
2035 """normal: Rc=0: pred-result z/nonz"""
2042 def specifiers(self
, record
):
2043 yield from super().specifiers(record
=record
, mode
="pr")
2046 class NormalRM(NormalBaseRM
):
2047 simple
: NormalSimpleRM
2049 ffrc1
: NormalFFRc1RM
2050 ffrc0
: NormalFFRc0RM
2052 prrc1
: NormalPRRc1RM
2053 prrc0
: NormalPRRc0RM
2056 class LDSTImmBaseRM(PredicateWidthBaseRM
):
2058 LD/ST Immediate mode
2059 https://libre-soc.org/openpower/sv/ldst/
2064 class LDSTImmSimpleRM(ElsBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2065 """ld/st immediate: simple mode"""
2072 class LDSTImmPostRM(LDSTImmBaseRM
):
2073 """ld/st immediate: postinc mode (and load-fault)"""
2074 pi
: BaseRM
.mode
[3] # Post-Increment Mode
2075 lf
: BaseRM
.mode
[4] # Fault-First Mode (not *Data-Dependent* Fail-First)
2077 def specifiers(self
, record
):
2084 class LDSTImmFFRc1RM(FFPRRc1BaseRM
, LDSTImmBaseRM
):
2085 """ld/st immediate: Rc=1: ffirst CR sel"""
2087 CR
: BaseRM
.mode
[3, 4]
2089 def specifiers(self
, record
):
2090 yield from super().specifiers(record
=record
, mode
="ff")
2093 class LDSTImmFFRc0RM(FFPRRc0BaseRM
, ElsBaseRM
, LDSTImmBaseRM
):
2094 """ld/st immediate: Rc=0: ffirst z/nonz"""
2099 def specifiers(self
, record
):
2100 yield from super().specifiers(record
=record
, mode
="ff")
2103 class LDSTImmSatRM(ElsBaseRM
, SatBaseRM
, ZZBaseRM
, LDSTImmBaseRM
):
2104 """ld/st immediate: sat mode: N=0/1 u/s"""
2112 class LDSTImmPRRc1RM(FFPRRc1BaseRM
, LDSTImmBaseRM
):
2113 """ld/st immediate: Rc=1: pred-result CR sel"""
2115 CR
: BaseRM
.mode
[3, 4]
2117 def specifiers(self
, record
):
2118 yield from super().specifiers(record
=record
, mode
="pr")
2121 class LDSTImmPRRc0RM(FFPRRc0BaseRM
, ElsBaseRM
, LDSTImmBaseRM
):
2122 """ld/st immediate: Rc=0: pred-result z/nonz"""
2127 def specifiers(self
, record
):
2128 yield from super().specifiers(record
=record
, mode
="pr")
2131 class LDSTImmRM(LDSTImmBaseRM
):
2132 simple
: LDSTImmSimpleRM
2134 ffrc1
: LDSTImmFFRc1RM
2135 ffrc0
: LDSTImmFFRc0RM
2137 prrc1
: LDSTImmPRRc1RM
2138 prrc0
: LDSTImmPRRc0RM
2141 class LDSTIdxBaseRM(PredicateWidthBaseRM
):
2144 https://libre-soc.org/openpower/sv/ldst/
2149 class LDSTIdxSimpleRM(SEABaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2150 """ld/st index: simple mode"""
2156 class LDSTIdxStrideRM(SEABaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2157 """ld/st index: strided (scalar only source)"""
2162 def specifiers(self
, record
):
2165 yield from super().specifiers(record
=record
)
2168 class LDSTIdxSatRM(SatBaseRM
, ZZCombinedBaseRM
, LDSTIdxBaseRM
):
2169 """ld/st index: sat mode: N=0/1 u/s"""
2175 class LDSTIdxPRRc1RM(LDSTIdxBaseRM
):
2176 """ld/st index: Rc=1: pred-result CR sel"""
2178 CR
: BaseRM
.mode
[3, 4]
2180 def specifiers(self
, record
):
2181 yield from super().specifiers(record
=record
, mode
="pr")
2184 class LDSTIdxPRRc0RM(FFPRRc0BaseRM
, ZZBaseRM
, LDSTIdxBaseRM
):
2185 """ld/st index: Rc=0: pred-result z/nonz"""
2192 def specifiers(self
, record
):
2193 yield from super().specifiers(record
=record
, mode
="pr")
2196 class LDSTIdxRM(LDSTIdxBaseRM
):
2197 simple
: LDSTIdxSimpleRM
2198 stride
: LDSTIdxStrideRM
2200 prrc1
: LDSTIdxPRRc1RM
2201 prrc0
: LDSTIdxPRRc0RM
2205 class CROpBaseRM(BaseRM
):
2208 https://libre-soc.org/openpower/sv/cr_ops/
2213 class CROpSimpleRM(PredicateBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2214 """cr_op: simple mode"""
2219 def specifiers(self
, record
):
2221 yield "rg" # simple CR Mode reports /rg
2223 yield from super().specifiers(record
=record
)
2225 class CROpMRRM(MRBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2226 """cr_op: scalar reduce mode (mapreduce), SUBVL=1"""
2232 class CROpFF3RM(FFPRRc1BaseRM
, VLiBaseRM
, ZZBaseRM
, PredicateBaseRM
, CROpBaseRM
):
2233 """cr_op: ffirst 3-bit mode"""
2241 def specifiers(self
, record
):
2242 yield from super().specifiers(record
=record
, mode
="ff")
2245 class CROpFF5RM(FFPRRc0BaseRM
, PredicateBaseRM
,
2246 VLiBaseRM
, ZZCombinedBaseRM
, CROpBaseRM
):
2247 """cr_op: ffirst 5-bit mode"""
2250 RC1
: BaseRM
[19] # cheat: set RC=1 based on ffirst mode being set
2254 def specifiers(self
, record
):
2255 yield from super().specifiers(record
=record
, mode
="ff")
2258 class CROpRM(CROpBaseRM
):
2259 simple
: CROpSimpleRM
2265 # ********************
2267 # https://libre-soc.org/openpower/sv/branches/
2268 class BranchBaseRM(BaseRM
):
2278 def specifiers(self
, record
):
2290 raise ValueError(self
.sz
)
2302 # Branch modes lack source mask.
2303 # Therefore a custom code is needed.
2304 CR
= (int(self
.mmode
) == 1)
2305 mask
= int(self
.mask
)
2306 m
= PredicateBaseRM
.predicate(CR
, mask
)
2310 yield from super().specifiers(record
=record
)
2313 class BranchSimpleRM(BranchBaseRM
):
2314 """branch: simple mode"""
2318 class BranchVLSRM(BranchBaseRM
):
2319 """branch: VLSET mode"""
2323 def specifiers(self
, record
):
2329 }[int(self
.VSb
), int(self
.VLi
)]
2331 yield from super().specifiers(record
=record
)
2334 class BranchCTRRM(BranchBaseRM
):
2335 """branch: CTR-test mode"""
2338 def specifiers(self
, record
):
2344 yield from super().specifiers(record
=record
)
2347 class BranchCTRVLSRM(BranchVLSRM
, BranchCTRRM
):
2348 """branch: CTR-test+VLSET mode"""
2352 class BranchRM(BranchBaseRM
):
2353 simple
: BranchSimpleRM
2356 ctrvls
: BranchCTRVLSRM
2366 def select(self
, record
):
2370 # the idea behind these tables is that they are now literally
2371 # in identical format to insndb.csv and minor_xx.csv and can
2372 # be done precisely as that. the only thing to watch out for
2373 # is the insertion of Rc=1 as a "mask/value" bit and likewise
2374 # regtype detection (3-bit BF/BFA, 5-bit BA/BB/BT) also inserted
2377 if record
.svp64
.mode
is _SVMode
.NORMAL
:
2378 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
2379 # mode Rc mask Rc member
2381 (0b000000, 0b111000, "simple"), # simple (no Rc)
2382 (0b001000, 0b111000, "mr"), # mapreduce (no Rc)
2383 (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
2384 (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
2385 (0b100000, 0b110000, "sat"), # saturation (no Rc)
2386 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
2387 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
2390 search
= ((int(rm
.mode
) << 1) | Rc
)
2392 elif record
.svp64
.mode
is _SVMode
.LDST_IMM
:
2393 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
2394 # mode Rc mask Rc member
2395 # ironically/coincidentally this table is identical to NORMAL
2396 # mode except reserved in place of mr
2398 (0b000000, 0b111000, "simple"), # simple (no Rc)
2399 (0b001000, 0b111000, "post"), # post (no Rc)
2400 (0b010001, 0b110001, "ffrc1"), # ffirst, Rc=1
2401 (0b010000, 0b110001, "ffrc0"), # ffirst, Rc=0
2402 (0b100000, 0b110000, "sat"), # saturation (no Rc)
2403 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
2404 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
2407 search
= ((int(rm
.mode
) << 1) | Rc
)
2409 elif record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2410 # concatenate mode 5-bit with Rc (LSB) then do a mask/map search
2411 # mode Rc mask Rc member
2413 (0b000000, 0b110000, "simple"), # simple (no Rc)
2414 (0b010000, 0b110000, "stride"), # strided, (no Rc)
2415 (0b100000, 0b110000, "sat"), # saturation (no Rc)
2416 (0b110001, 0b110001, "prrc1"), # predicate, Rc=1
2417 (0b110000, 0b110001, "prrc0"), # predicate, Rc=0
2420 search
= ((int(rm
.mode
) << 1) | Rc
)
2422 elif record
.svp64
.mode
is _SVMode
.CROP
:
2423 # concatenate mode 5-bit with regtype (LSB) then do mask/map search
2424 # mode 3b mask 3b member
2426 (0b000000, 0b111000, "simple"), # simple
2427 (0b001000, 0b111000, "mr"), # mapreduce
2428 (0b100001, 0b100001, "ff3"), # ffirst, 3-bit CR
2429 (0b100000, 0b100000, "ff5"), # ffirst, 5-bit CR
2432 search
= ((int(rm
.mode
) << 1) |
int(record
.svp64
.cr_3bit
))
2434 elif record
.svp64
.mode
is _SVMode
.BRANCH
:
2438 (0b00, 0b11, "simple"), # simple
2439 (0b01, 0b11, "vls"), # VLset
2440 (0b10, 0b11, "ctr"), # CTR mode
2441 (0b11, 0b11, "ctrvls"), # CTR+VLset mode
2443 # slightly weird: doesn't have a 5-bit "mode" field like others
2445 search
= int(rm
.mode
.sel
)
2448 if table
is not None:
2449 for (value
, mask
, member
) in table
:
2450 if ((value
& mask
) == (search
& mask
)):
2451 rm
= getattr(rm
, member
)
2454 if rm
.__class
__ is self
.__class
__:
2455 raise ValueError(self
)
2460 @_dataclasses.dataclass(eq
=True, frozen
=True)
2465 def match(cls
, desc
, record
):
2466 raise NotImplementedError
2468 def validate(self
, others
):
2471 def assemble(self
, insn
):
2472 raise NotImplementedError
2475 @_dataclasses.dataclass(eq
=True, frozen
=True)
2476 class SpecifierWidth(Specifier
):
2480 def match(cls
, desc
, record
, etalon
):
2481 (mode
, _
, value
) = desc
.partition("=")
2483 value
= value
.strip()
2486 value
= _SVP64Width(value
)
2488 return cls(record
=record
, mode
=mode
, value
=value
)
2491 @_dataclasses.dataclass(eq
=True, frozen
=True)
2492 class SpecifierW(SpecifierWidth
):
2494 def match(cls
, desc
, record
):
2495 return super().match(desc
=desc
, record
=record
, etalon
="w")
2497 def assemble(self
, insn
):
2498 insn
.prefix
.rm
.ewsrc
= int(self
.value
)
2499 insn
.prefix
.rm
.elwidth
= int(self
.value
)
2502 @_dataclasses.dataclass(eq
=True, frozen
=True)
2503 class SpecifierSW(SpecifierWidth
):
2505 def match(cls
, desc
, record
):
2506 return super().match(desc
=desc
, record
=record
, etalon
="sw")
2508 def assemble(self
, insn
):
2509 insn
.prefix
.rm
.ewsrc
= int(self
.value
)
2512 @_dataclasses.dataclass(eq
=True, frozen
=True)
2513 class SpecifierDW(SpecifierWidth
):
2515 def match(cls
, desc
, record
):
2516 return super().match(desc
=desc
, record
=record
, etalon
="dw")
2518 def assemble(self
, insn
):
2519 insn
.prefix
.rm
.elwidth
= int(self
.value
)
2522 @_dataclasses.dataclass(eq
=True, frozen
=True)
2523 class SpecifierSubVL(Specifier
):
2527 def match(cls
, desc
, record
):
2529 value
= _SVP64SubVL(desc
)
2533 return cls(record
=record
, value
=value
)
2535 def assemble(self
, insn
):
2536 insn
.prefix
.rm
.subvl
= int(self
.value
.value
)
2539 @_dataclasses.dataclass(eq
=True, frozen
=True)
2540 class SpecifierPredicate(Specifier
):
2545 def match(cls
, desc
, record
, mode_match
, pred_match
):
2546 (mode
, _
, pred
) = desc
.partition("=")
2549 if not mode_match(mode
):
2552 pred
= _SVP64Pred(pred
.strip())
2553 if not pred_match(pred
):
2554 raise ValueError(pred
)
2556 return cls(record
=record
, mode
=mode
, pred
=pred
)
2559 @_dataclasses.dataclass(eq
=True, frozen
=True)
2560 class SpecifierFFPR(SpecifierPredicate
):
2562 def match(cls
, desc
, record
, mode
):
2563 return super().match(desc
=desc
, record
=record
,
2564 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2565 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2570 def assemble(self
, insn
):
2572 if rm
.mode
.sel
!= 0:
2573 raise ValueError("cannot override mode")
2575 if self
.record
.svp64
.mode
is _SVMode
.CROP
:
2576 if self
.mode
== "pr":
2577 raise ValueError("crop: 'pr' mode not supported")
2579 if self
.record
.svp64
.cr_3bit
:
2584 if self
.record
.svp64
.mode
is _SVMode
.NORMAL
:
2586 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IMM
:
2588 elif self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2590 if self
.mode
== "ff":
2591 raise ValueError("ld/st idx: 'ff' mode not supported")
2593 raise ValueError(f
"{self.mode!r} not supported")
2595 # These 2-bit values should have bits swapped
2597 return (((value
& 0b10) >> 1) |
((value
& 0b01) << 1))
2600 "ff": bitswap(_SVP64RMMode
.FFIRST
.value
),
2601 "pr": bitswap(_SVP64RMMode
.PREDRES
.value
),
2604 Rc
= int(self
.record
.Rc
)
2605 rm
= getattr(rm
, f
"{self.mode}rc{Rc}")
2606 rm
.inv
= self
.pred
.inv
2608 rm
.CR
= self
.pred
.state
2610 rm
.RC1
= self
.pred
.state
2613 @_dataclasses.dataclass(eq
=True, frozen
=True)
2614 class SpecifierFF(SpecifierFFPR
):
2616 def match(cls
, desc
, record
):
2617 return super().match(desc
=desc
, record
=record
, mode
="ff")
2620 @_dataclasses.dataclass(eq
=True, frozen
=True)
2621 class SpecifierPR(SpecifierFFPR
):
2623 def match(cls
, desc
, record
):
2624 return super().match(desc
=desc
, record
=record
, mode
="pr")
2627 @_dataclasses.dataclass(eq
=True, frozen
=True)
2628 class SpecifierMask(SpecifierPredicate
):
2630 def match(cls
, desc
, record
, mode
):
2631 return super().match(desc
=desc
, record
=record
,
2632 mode_match
=lambda mode_arg
: mode_arg
== mode
,
2633 pred_match
=lambda pred_arg
: pred_arg
.mode
in (
2638 def assemble(self
, insn
):
2639 raise NotImplementedError
2642 @_dataclasses.dataclass(eq
=True, frozen
=True)
2643 class SpecifierM(SpecifierMask
):
2645 def match(cls
, desc
, record
):
2646 return super().match(desc
=desc
, record
=record
, mode
="m")
2648 def validate(self
, others
):
2650 if isinstance(spec
, SpecifierSM
):
2651 raise ValueError("source-mask and predicate mask conflict")
2652 elif isinstance(spec
, SpecifierDM
):
2653 raise ValueError("dest-mask and predicate mask conflict")
2655 def assemble(self
, insn
):
2656 insn
.prefix
.rm
.mask
= int(self
.pred
)
2659 @_dataclasses.dataclass(eq
=True, frozen
=True)
2660 class SpecifierSM(SpecifierMask
):
2662 def match(cls
, desc
, record
):
2663 return super().match(desc
=desc
, record
=record
, mode
="sm")
2665 def validate(self
, others
):
2666 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2667 raise ValueError("source-mask on non-twin predicate")
2669 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2672 if isinstance(spec
, SpecifierDM
):
2676 raise ValueError("missing dest-mask in CR twin predication")
2677 if self
.pred
!= twin
.pred
:
2678 raise ValueError(f
"predicate masks mismatch: {self!r} vs {twin!r}")
2680 def assemble(self
, insn
):
2681 insn
.prefix
.rm
.smask
= int(self
.pred
)
2684 @_dataclasses.dataclass(eq
=True, frozen
=True)
2685 class SpecifierDM(SpecifierMask
):
2687 def match(cls
, desc
, record
):
2688 return super().match(desc
=desc
, record
=record
, mode
="dm")
2690 def validate(self
, others
):
2691 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2692 raise ValueError("dest-mask on non-twin predicate")
2694 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2697 if isinstance(spec
, SpecifierSM
):
2701 raise ValueError("missing source-mask in CR twin predication")
2702 if self
.pred
!= twin
.pred
:
2703 raise ValueError(f
"predicate masks mismatch: {self!r} vs {twin!r}")
2705 def assemble(self
, insn
):
2706 insn
.prefix
.rm
.mask
= int(self
.pred
)
2710 @_dataclasses.dataclass(eq
=True, frozen
=True)
2711 class SpecifierZZ(Specifier
):
2713 def match(cls
, desc
, record
):
2717 return cls(record
=record
)
2719 def validate(self
, others
):
2721 # Since m=xx takes precedence (overrides) sm=xx and dm=xx,
2722 # treat them as mutually exclusive.
2723 if isinstance(spec
, (SpecifierSZ
, SpecifierDZ
)):
2724 raise ValueError("mutually exclusive predicate masks")
2726 def assemble(self
, insn
):
2727 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2728 if hasattr(rm
, "zz"):
2735 @_dataclasses.dataclass(eq
=True, frozen
=True)
2736 class SpecifierXZ(Specifier
):
2738 hint
: str = _dataclasses
.field(repr=False)
2741 def match(cls
, desc
, record
, etalon
, hint
):
2742 if not desc
!= etalon
:
2745 return cls(desc
=desc
, record
=record
, hint
=hint
)
2747 def validate(self
, others
):
2748 if self
.record
.svp64
.ptype
is _SVPType
.P1
:
2749 raise ValueError(f
"{self.hint} on non-twin predicate")
2751 if self
.pred
.mode
is _SVP64PredMode
.CR
:
2754 if isinstance(spec
, SpecifierSM
):
2758 raise ValueError(f
"missing {self.hint} in CR twin predication")
2759 if self
.pred
!= twin
.pred
:
2760 raise ValueError(f
"predicate masks mismatch: {self!r} vs {twin!r}")
2762 def assemble(self
, insn
):
2763 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2764 setattr(rm
, self
.desc
, 1)
2767 @_dataclasses.dataclass(eq
=True, frozen
=True)
2768 class SpecifierSZ(SpecifierXZ
):
2770 def match(cls
, desc
, record
):
2771 return super().match(desc
=desc
, record
=record
,
2772 etalon
="sz", hint
="source-mask")
2774 def validate(self
, others
):
2776 if isinstance(spec
, SpecifierFF
):
2777 raise ValueError("source-zero not allowed in ff mode")
2778 elif isinstance(spec
, SpecifierPR
):
2779 raise ValueError("source-zero not allowed in pr mode")
2782 @_dataclasses.dataclass(eq
=True, frozen
=True)
2783 class SpecifierDZ(SpecifierXZ
):
2785 def match(cls
, desc
, record
):
2786 return super().match(desc
=desc
, record
=record
,
2787 etalon
="dz", hint
="dest-mask")
2789 def validate(self
, others
):
2791 if (isinstance(spec
, (SpecifierFF
, SpecifierPR
)) and
2792 (spec
.pred
.mode
is _SVP64PredMode
.RC1
)):
2793 mode
= "ff" if isinstance(spec
, SpecifierFF
) else "pr"
2794 raise ValueError(f
"dest-zero not allowed in {mode} mode BO")
2797 @_dataclasses.dataclass(eq
=True, frozen
=True)
2798 class SpecifierEls(Specifier
):
2800 def match(cls
, desc
, record
):
2804 return cls(record
=record
)
2806 def assemble(self
, insn
):
2807 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2809 if self
.record
.svp64
.mode
is _SVMode
.LDST_IDX
:
2813 @_dataclasses.dataclass(eq
=True, frozen
=True)
2814 class SpecifierSEA(Specifier
):
2816 def match(cls
, desc
, record
):
2820 return cls(record
=record
)
2822 def validate(self
, others
):
2823 if self
.record
.svp64
.mode
is not _SVMode
.LDST_IDX
:
2824 raise ValueError("sea is only valid in ld/st modes")
2827 if isinstance(spec
, SpecifierFF
):
2828 raise ValueError(f
"sea cannot be used in ff mode")
2830 def assemble(self
, insn
):
2831 rm
= insn
.prefix
.rm
.select(record
=self
.record
)
2832 if rm
.mode
.sel
not in (0b00, 0b01):
2833 raise ValueError("sea is only valid for normal and els modes")
2837 class Specifiers(tuple):
2854 def __new__(cls
, items
, record
):
2855 def transform(item
):
2856 for spec_cls
in cls
.SPECS
:
2857 spec
= spec_cls
.match(item
, record
=record
)
2858 if spec
is not None:
2860 raise ValueError(item
)
2862 specs
= tuple(map(transform
, items
))
2863 for (index
, spec
) in enumerate(specs
):
2864 head
= specs
[:index
]
2865 tail
= specs
[index
+ 1:]
2866 spec
.validate(others
=(head
+ tail
))
2868 return super().__new
__(cls
, specs
)
2871 class SVP64Instruction(PrefixedInstruction
):
2872 """SVP64 instruction: https://libre-soc.org/openpower/sv/svp64/"""
2873 class Prefix(PrefixedInstruction
.Prefix
):
2875 rm
: RM
.remap((6, 8) + tuple(range(10, 32)))
2879 def record(self
, db
):
2880 record
= db
[self
.suffix
]
2882 raise KeyError(self
)
2888 for idx
in range(64):
2889 bit
= int(self
[idx
])
2891 return "".join(map(str, bits
))
2894 def assemble(cls
, db
, opcode
, arguments
=None, specifiers
=None):
2895 if arguments
is None:
2897 if specifiers
is None:
2901 insn
= cls
.integer(value
=0)
2903 specifiers
= Specifiers(items
=specifiers
, record
=record
)
2904 for specifier
in specifiers
:
2905 specifier
.assemble(insn
=insn
)
2907 for operand
in record
.static_operands
:
2908 operand
.assemble(insn
=insn
)
2910 dynamic_operands
= tuple(record
.dynamic_operands
)
2911 if len(dynamic_operands
) != len(arguments
):
2912 raise ValueError("operands count mismatch")
2913 for (value
, operand
) in zip(arguments
, dynamic_operands
):
2914 operand
.assemble(value
=value
, insn
=insn
)
2916 insn
.prefix
.PO
= 0x1
2917 insn
.prefix
.id = 0x3
2921 def disassemble(self
, db
,
2923 verbosity
=Verbosity
.NORMAL
):
2925 if verbosity
<= Verbosity
.SHORT
:
2928 blob
= insn
.bytes(byteorder
=byteorder
)
2929 blob
= " ".join(map(lambda byte
: f
"{byte:02x}", blob
))
2932 record
= self
.record(db
=db
)
2933 blob_prefix
= blob(self
.prefix
)
2934 blob_suffix
= blob(self
.suffix
)
2935 if record
is None or record
.svp64
is None:
2936 yield f
"{blob_prefix}.long 0x{int(self.prefix):08x}"
2937 yield f
"{blob_suffix}.long 0x{int(self.suffix):08x}"
2940 name
= f
"sv.{record.name}"
2942 rm
= self
.prefix
.rm
.select(record
=record
)
2944 # convert specifiers to /x/y/z (sorted lexicographically)
2945 specifiers
= sorted(rm
.specifiers(record
=record
))
2946 if specifiers
: # if any add one extra to get the extra "/"
2947 specifiers
= ([""] + specifiers
)
2948 specifiers
= "/".join(specifiers
)
2950 # convert operands to " ,x,y,z"
2951 operands
= tuple(map(_operator
.itemgetter(1),
2952 self
.dynamic_operands(db
=db
, verbosity
=verbosity
)))
2953 operands
= ",".join(operands
)
2954 if len(operands
) > 0: # if any separate with a space
2955 operands
= (" " + operands
)
2957 yield f
"{blob_prefix}{name}{specifiers}{operands}"
2959 yield f
"{blob_suffix}"
2961 if verbosity
>= Verbosity
.VERBOSE
:
2963 binary
= self
.binary
2964 spec
= self
.spec(db
=db
, prefix
="sv.")
2966 yield f
"{indent}spec"
2967 yield f
"{indent}{indent}{spec}"
2968 yield f
"{indent}pcode"
2969 for stmt
in record
.mdwn
.pcode
:
2970 yield f
"{indent}{indent}{stmt}"
2971 yield f
"{indent}binary"
2972 yield f
"{indent}{indent}[0:8] {binary[0:8]}"
2973 yield f
"{indent}{indent}[8:16] {binary[8:16]}"
2974 yield f
"{indent}{indent}[16:24] {binary[16:24]}"
2975 yield f
"{indent}{indent}[24:32] {binary[24:32]}"
2976 yield f
"{indent}{indent}[32:40] {binary[32:40]}"
2977 yield f
"{indent}{indent}[40:48] {binary[40:48]}"
2978 yield f
"{indent}{indent}[48:56] {binary[48:56]}"
2979 yield f
"{indent}{indent}[56:64] {binary[56:64]}"
2980 yield f
"{indent}opcodes"
2981 for opcode
in record
.opcodes
:
2982 yield f
"{indent}{indent}{opcode!r}"
2983 for (cls
, kwargs
) in record
.mdwn
.operands
:
2984 operand
= cls(record
=record
, **kwargs
)
2985 yield from operand
.disassemble(insn
=self
,
2986 verbosity
=verbosity
, indent
=indent
)
2988 yield f
"{indent}{indent}{rm.__doc__}"
2989 for line
in rm
.disassemble(verbosity
=verbosity
):
2990 yield f
"{indent}{indent}{line}"
2994 def parse(stream
, factory
):
2996 return ("TODO" not in frozenset(entry
.values()))
2998 lines
= filter(lambda line
: not line
.strip().startswith("#"), stream
)
2999 entries
= _csv
.DictReader(lines
)
3000 entries
= filter(match
, entries
)
3001 return tuple(map(factory
, entries
))
3004 class MarkdownDatabase
:
3007 for (name
, desc
) in _ISA():
3010 (dynamic
, *static
) = desc
.regs
3011 operands
.extend(dynamic
)
3012 operands
.extend(static
)
3013 pcode
= PCode(iterable
=desc
.pcode
)
3014 operands
= Operands(insn
=name
, iterable
=operands
)
3015 db
[name
] = MarkdownRecord(pcode
=pcode
, operands
=operands
)
3017 self
.__db
= dict(sorted(db
.items()))
3019 return super().__init
__()
3022 yield from self
.__db
.items()
3024 def __contains__(self
, key
):
3025 return self
.__db
.__contains
__(key
)
3027 def __getitem__(self
, key
):
3028 return self
.__db
.__getitem
__(key
)
3031 class FieldsDatabase
:
3034 df
= _DecodeFields()
3036 for (form
, fields
) in df
.instrs
.items():
3037 if form
in {"DQE", "TX"}:
3041 db
[_Form
[form
]] = Fields(fields
)
3045 return super().__init
__()
3047 def __getitem__(self
, key
):
3048 return self
.__db
.__getitem
__(key
)
3052 def __init__(self
, root
, mdwndb
):
3053 # The code below groups the instructions by name:section.
3054 # There can be multiple names for the same instruction.
3055 # The point is to capture different opcodes for the same instruction.
3056 dd
= _collections
.defaultdict
3058 records
= _collections
.defaultdict(set)
3059 path
= (root
/ "insndb.csv")
3060 with
open(path
, "r", encoding
="UTF-8") as stream
:
3061 for section
in sorted(parse(stream
, Section
.CSV
)):
3062 path
= (root
/ section
.path
)
3064 section
.Mode
.INTEGER
: IntegerOpcode
,
3065 section
.Mode
.PATTERN
: PatternOpcode
,
3067 factory
= _functools
.partial(
3068 PPCRecord
.CSV
, opcode_cls
=opcode_cls
)
3069 with
open(path
, "r", encoding
="UTF-8") as stream
:
3070 for insn
in parse(stream
, factory
):
3071 for name
in insn
.names
:
3072 records
[name
].add(insn
)
3073 sections
[name
] = section
3075 items
= sorted(records
.items())
3077 for (name
, multirecord
) in items
:
3078 records
[name
] = PPCMultiRecord(sorted(multirecord
))
3080 def exact_match(name
):
3081 record
= records
.get(name
)
3087 if not name
.endswith("l"):
3089 alias
= exact_match(name
[:-1])
3092 record
= records
[alias
]
3093 if "lk" not in record
.flags
:
3094 raise ValueError(record
)
3098 if not name
.endswith("a"):
3100 alias
= LK_match(name
[:-1])
3103 record
= records
[alias
]
3104 if record
.intop
not in {_MicrOp
.OP_B
, _MicrOp
.OP_BC
}:
3105 raise ValueError(record
)
3106 if "AA" not in mdwndb
[name
].operands
:
3107 raise ValueError(record
)
3111 if not name
.endswith("."):
3113 alias
= exact_match(name
[:-1])
3116 record
= records
[alias
]
3117 if record
.Rc
is _RCOE
.NONE
:
3118 raise ValueError(record
)
3122 matches
= (exact_match
, LK_match
, AA_match
, Rc_match
)
3123 for (name
, _
) in mdwndb
:
3124 if name
.startswith("sv."):
3127 for match
in matches
:
3129 if alias
is not None:
3133 section
= sections
[alias
]
3134 record
= records
[alias
]
3135 db
[name
] = (section
, record
)
3137 self
.__db
= dict(sorted(db
.items()))
3139 return super().__init
__()
3141 @_functools.lru_cache(maxsize
=512, typed
=False)
3142 def __getitem__(self
, key
):
3143 return self
.__db
.get(key
, (None, None))
3146 class SVP64Database
:
3147 def __init__(self
, root
, ppcdb
):
3149 pattern
= _re
.compile(r
"^(?:LDST)?RM-(1P|2P)-.*?\.csv$")
3150 for (prefix
, _
, names
) in _os
.walk(root
):
3151 prefix
= _pathlib
.Path(prefix
)
3152 for name
in filter(lambda name
: pattern
.match(name
), names
):
3153 path
= (prefix
/ _pathlib
.Path(name
))
3154 with
open(path
, "r", encoding
="UTF-8") as stream
:
3155 db
.update(parse(stream
, SVP64Record
.CSV
))
3156 db
= {record
.name
:record
for record
in db
}
3158 self
.__db
= dict(sorted(db
.items()))
3159 self
.__ppcdb
= ppcdb
3161 return super().__init
__()
3163 def __getitem__(self
, key
):
3164 (_
, record
) = self
.__ppcdb
[key
]
3168 for name
in record
.names
:
3169 record
= self
.__db
.get(name
, None)
3170 if record
is not None:
3177 def __init__(self
, root
):
3178 root
= _pathlib
.Path(root
)
3179 mdwndb
= MarkdownDatabase()
3180 fieldsdb
= FieldsDatabase()
3181 ppcdb
= PPCDatabase(root
=root
, mdwndb
=mdwndb
)
3182 svp64db
= SVP64Database(root
=root
, ppcdb
=ppcdb
)
3186 opcodes
= _collections
.defaultdict(
3187 lambda: _collections
.defaultdict(set))
3189 for (name
, mdwn
) in mdwndb
:
3190 if name
.startswith("sv."):
3192 (section
, ppc
) = ppcdb
[name
]
3195 svp64
= svp64db
[name
]
3196 fields
= fieldsdb
[ppc
.form
]
3197 record
= Record(name
=name
,
3198 section
=section
, ppc
=ppc
, svp64
=svp64
,
3199 mdwn
=mdwn
, fields
=fields
)
3201 names
[record
.name
] = record
3205 opcodes
[section
][PO
.value
].add(record
)
3207 self
.__db
= sorted(db
)
3208 self
.__names
= dict(sorted(names
.items()))
3209 self
.__opcodes
= dict(sorted(opcodes
.items()))
3211 return super().__init
__()
3214 return repr(self
.__db
)
3217 yield from self
.__db
3219 @_functools.lru_cache(maxsize
=None)
3220 def __contains__(self
, key
):
3221 return self
.__getitem
__(key
) is not None
3223 @_functools.lru_cache(maxsize
=None)
3224 def __getitem__(self
, key
):
3225 if isinstance(key
, Instruction
):
3228 for (section
, group
) in self
.__opcodes
.items():
3229 for record
in group
[PO
]:
3230 if record
.match(key
=key
):
3235 elif isinstance(key
, str):
3236 return self
.__names
.get(key
)
3238 raise ValueError("instruction or name expected")