0fa44901d9b119d04fe7c0a3f956619d68fdffe7
[openpower-isa.git] / src / openpower / decoder / power_svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 from openpower.decoder.power_enums import get_csv, find_wiki_dir
6 import os
7
8 # identifies register by type
9 def is_CR_3bit(regname):
10 return regname in ['BF', 'BFA']
11
12 def is_CR_5bit(regname):
13 return regname in ['BA', 'BB', 'BC', 'BI', 'BT']
14
15 def is_GPR(regname):
16 return regname in ['RA', 'RB', 'RC', 'RS', 'RT']
17
18 def is_FPR(regname):
19 return regname in ['FRA', 'FRB', 'FRC', 'FRS', 'FRT']
20
21 def get_regtype(regname):
22 if is_CR_3bit(regname):
23 return "CR_3bit"
24 if is_CR_5bit(regname):
25 return "CR_5bit"
26 if is_GPR(regname):
27 return "GPR"
28 if is_FPR(regname):
29 return "FPR"
30
31
32 def decode_extra(rm, prefix=''):
33 # first turn the svp64 rm into a "by name" dict, recording
34 # which position in the RM EXTRA it goes into
35 # also: record if the src or dest was a CR, for sanity-checking
36 # (elwidth overrides on CRs are banned)
37 dest_reg_cr, src_reg_cr = False, False
38 svp64_srcreg_byname = {}
39 svp64_destreg_byname = {}
40 for i in range(4):
41 print (rm)
42 rfield = rm[prefix+str(i)]
43 if not rfield or rfield == '0':
44 continue
45 print ("EXTRA field", i, rfield)
46 rfield = rfield.split(";") # s:RA;d:CR1 etc.
47 for r in rfield:
48 rtype = r[0]
49 # TODO: ignoring s/d makes it impossible to do
50 # LD/ST-with-update.
51 r = r[2:] # ignore s: and d:
52 if rtype == 'd':
53 svp64_destreg_byname[r] = i # dest reg in EXTRA position 0-3
54 else:
55 svp64_srcreg_byname[r] = i # src reg in EXTRA position 0-3
56 # check the regtype (if CR, record that)
57 regtype = get_regtype(r)
58 if regtype in ['CR_3bit', 'CR_5bit']:
59 if rtype == 'd':
60 dest_reg_cr = True
61 if rtype == 's':
62 src_reg_cr = True
63
64 return dest_reg_cr, src_reg_cr, svp64_srcreg_byname, svp64_destreg_byname
65
66
67 # gets SVP64 ReMap information
68 class SVP64RM:
69 def __init__(self, microwatt_format=False):
70 """SVP64RM: gets micro-opcode information
71
72 microwatt_format: moves RS to in1 (to match decode1.vhdl)
73 """
74 self.instrs = {}
75 self.svp64_instrs = {}
76 pth = find_wiki_dir()
77 for fname in os.listdir(pth):
78 if fname.startswith("RM") or fname.startswith("LDSTRM"):
79 for entry in get_csv(fname):
80 if microwatt_format:
81 # move RS from position 1 to position 3, to match
82 # microwatt decode1.vhdl format
83 if entry['in1'] == 'RS' and entry['in3'] == 'NONE':
84 entry['in1'] = 'NONE'
85 entry['in3'] = 'RS'
86 self.instrs[entry['insn']] = entry
87
88
89 def get_svp64_csv(self, fname):
90 # first get the v3.0B entries
91 v30b = get_csv(fname)
92
93 # now add the RM fields (for each instruction)
94 for entry in v30b:
95 # *sigh* create extra field "out2" based on LD/ST update
96 # KEEP TRACK HERE https://bugs.libre-soc.org/show_bug.cgi?id=619
97 entry['out2'] = 'NONE'
98 if entry['upd'] == '1':
99 entry['out2'] = 'RA'
100
101 # dummy (blank) fields, first
102 entry.update({'EXTRA0': '0', 'EXTRA1': '0', 'EXTRA2': '0',
103 'EXTRA3': '0',
104 'SV_Ptype': 'NONE', 'SV_Etype': 'NONE',
105 'sv_cr_in': 'NONE', 'sv_cr_out': 'NONE'})
106 for fname in ['in1', 'in2', 'in3', 'out', 'out2']:
107 entry['sv_%s' % fname] = 'NONE'
108
109 # is this SVP64-augmented?
110 asmcode = entry['comment']
111 if asmcode not in self.instrs:
112 continue
113
114 # start updating the fields, merge relevant info
115 svp64 = self.instrs[asmcode]
116 for k, v in {'EXTRA0': '0', 'EXTRA1': '1', 'EXTRA2': '2',
117 'EXTRA3': '3',
118 'SV_Ptype': 'Ptype', 'SV_Etype': 'Etype'}.items():
119 entry[k] = svp64[v]
120
121 # hmm, we need something more useful: a cross-association
122 # of the in1/2/3 and CR in/out with the EXTRA0-3 fields
123 decode = decode_extra(entry, "EXTRA")
124 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
125
126 # now examine in1/2/3/out, create sv_in1/2/3/out
127 for fname in ['in1', 'in2', 'in3', 'out', 'out2']:
128 regfield = entry[fname]
129 extra_index = None
130 if regfield == 'RA_OR_ZERO':
131 regfield = 'RA'
132 print (asmcode, regfield, fname, svp64_dest, svp64_src)
133 # find the reg in the SVP64 extra map
134 if (fname in ['out', 'out2'] and regfield in svp64_dest):
135 extra_index = svp64_dest[regfield]
136 if (fname not in ['out', 'out2'] and regfield in svp64_src):
137 extra_index = svp64_src[regfield]
138 # ta-daa, we know in1/2/3/out's bit-offset
139 if extra_index is not None:
140 entry['sv_%s' % fname] = "Idx"+str(extra_index)
141
142 # TODO: CRs a little tricky, the power_enums.CRInSel is a bit odd.
143 # ignore WHOLE_REG for now
144 cr_in = entry['CR in']
145 extra_index = 'NONE'
146 if cr_in in svp64_src:
147 entry['sv_cr_in'] = "Idx"+str(svp64_src[cr_in])
148 elif cr_in == 'BA_BB':
149 index1 = svp64_src.get('BA', None)
150 index2 = svp64_src.get('BB', None)
151 entry['sv_cr_in'] = "Idx_%d_%d" % (index1, index2)
152
153 # CRout a lot easier. ignore WHOLE_REG for now
154 cr_out = entry['CR out']
155 extra_index = svp64_dest.get(cr_out, None)
156 if extra_index is not None:
157 entry['sv_cr_out'] = 'Idx%d' % extra_index
158
159 # more enum-friendly Ptype names. should have done this in
160 # sv_analysis.py, oh well
161 if entry['SV_Ptype'] == '1P':
162 entry['SV_Ptype'] = 'P1'
163 if entry['SV_Ptype'] == '2P':
164 entry['SV_Ptype'] = 'P2'
165 self.svp64_instrs[asmcode] = entry
166
167 return v30b
168
169 if __name__ == '__main__':
170 isa = SVP64RM()
171 minor_31 = isa.get_svp64_csv("minor_31.csv")
172 for entry in minor_31:
173 if entry['comment'].startswith('ldu'):
174 print ("entry", entry)
175 minor_19 = isa.get_svp64_csv("minor_19.csv")
176 for entry in minor_19:
177 if entry['comment'].startswith('cr'):
178 print (entry)
179 minor_31 = isa.get_svp64_csv("minor_31.csv")
180 for entry in minor_31:
181 print (entry)