dad6853b69a4e58833392f8d13af0d9fe565a6bd
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4 """SVP64 RM (Remap) Record.
6 https://libre-soc.org/openpower/sv/svp64/
8 | Field Name | Field bits | Description |
9 |-------------|------------|----------------------------------------|
10 | MASKMODE | `0` | Execution (predication) Mask Kind |
11 | MASK | `1:3` | Execution Mask |
12 | ELWIDTH | `4:5` | Element Width |
13 | ELWIDTH_SRC | `6:7` | Element Width for Source |
14 | SUBVL | `8:9` | Sub-vector length |
15 | EXTRA | `10:18` | context-dependent extra |
16 | MODE | `19:23` | changes Vector behaviour |
19 from nmigen
import Elaboratable
, Module
, Signal
, Const
20 from openpower
.decoder
.power_enums
import (SVP64RMMode
, Function
, SVPtype
,
21 SVP64PredMode
, SVP64sat
, SVP64LDSTmode
)
22 from openpower
.consts
import EXTRA3
, SVP64MODE
23 from openpower
.sv
.svp64
import SVP64Rec
24 from nmutil
.util
import sel
26 # a list of fields which need to be added to input records in order
27 # pass on vital information needed by each pipeline.
28 # make sure to keep these the same as SVP64RMModeDecode, in fact,
29 # TODO, make SVP64RMModeDecode *use* this as a Record!
30 sv_input_record_layout
= [
31 ('sv_pred_sz', 1), # predicate source zeroing
32 ('sv_pred_dz', 1), # predicate dest zeroing
33 ('sv_saturate', SVP64sat
),
34 ('sv_ldstmode', SVP64LDSTmode
),
35 ('SV_Ptype', SVPtype
),
40 there are three Mode variants, two for LD/ST and one for everything else
41 https://libre-soc.org/openpower/sv/svp64/
42 https://libre-soc.org/openpower/sv/ldst/
45 00 els sz dz normal mode
46 01 inv CR-bit Rc=1: ffirst CR sel
47 01 inv els RC1 Rc=0: ffirst z/nonz
48 10 N dz els sat mode: N=0/1 u/s
49 11 inv CR-bit Rc=1: pred-result CR sel
50 11 inv els RC1 Rc=0: pred-result z/nonz
53 00 0 sz dz normal mode
55 01 inv CR-bit Rc=1: ffirst CR sel
56 01 inv dz RC1 Rc=0: ffirst z/nonz
57 10 N sz dz sat mode: N=0/1 u/s
58 11 inv CR-bit Rc=1: pred-result CR sel
59 11 inv dz RC1 Rc=0: pred-result z/nonz
62 00 0 sz dz normal mode
63 00 1 dz CRM reduce mode (mapreduce), SUBVL=1
64 00 1 SVM CRM subvector reduce mode, SUBVL>1
65 01 inv CR-bit Rc=1: ffirst CR sel
66 01 inv dz RC1 Rc=0: ffirst z/nonz
67 10 N sz dz sat mode: N=0/1 u/s
68 11 inv CR-bit Rc=1: pred-result CR sel
69 11 inv dz RC1 Rc=0: pred-result z/nonz
72 class SVP64RMModeDecode(Elaboratable
):
73 def __init__(self
, name
=None):
75 self
.rm_in
= SVP64Rec(name
=name
)
76 self
.fn_in
= Signal(Function
) # LD/ST is different
77 self
.ptype_in
= Signal(SVPtype
)
79 self
.ldst_ra_vec
= Signal() # set when RA is vec, indicate Index mode
80 self
.ldst_imz_in
= Signal() # set when LD/ST immediate is zero
84 # main mode (normal, reduce, saturate, ffirst, pred-result)
85 self
.mode
= Signal(SVP64RMMode
)
88 self
.predmode
= Signal(SVP64PredMode
)
89 self
.srcpred
= Signal(3) # source predicate
90 self
.dstpred
= Signal(3) # destination predicate
91 self
.pred_sz
= Signal(1) # predicate source zeroing
92 self
.pred_dz
= Signal(1) # predicate dest zeroing
94 self
.saturate
= Signal(SVP64sat
)
96 self
.cr_sel
= Signal(2) # bit of CR to test (index 0-3)
97 self
.inv
= Signal(1) # and whether it's inverted (like branch BO)
98 self
.map_evm
= Signal(1)
99 self
.map_crm
= Signal(1)
100 self
.ldstmode
= Signal(SVP64LDSTmode
) # LD/ST Mode (strided type)
102 def elaborate(self
, platform
):
105 mode
= self
.rm_in
.mode
107 # decode pieces of mode
109 comb
+= is_ldst
.eq(self
.fn_in
== Function
.LDST
)
110 mode2
= sel(m
, mode
, SVP64MODE
.MOD2
)
111 with m
.Switch(mode2
):
112 with m
.Case(0): # needs further decoding (LDST no mapreduce)
114 comb
+= self
.mode
.eq(SVP64RMMode
.NORMAL
)
115 with m
.Elif(mode
[SVP64MODE
.REDUCE
]):
116 comb
+= self
.mode
.eq(SVP64RMMode
.MAPREDUCE
)
118 comb
+= self
.mode
.eq(SVP64RMMode
.NORMAL
)
120 comb
+= self
.mode
.eq(SVP64RMMode
.FFIRST
) # fail-first
122 comb
+= self
.mode
.eq(SVP64RMMode
.SATURATE
) # saturate
124 comb
+= self
.mode
.eq(SVP64RMMode
.PREDRES
) # predicate result
127 with m
.Switch(mode2
):
128 with m
.Case(0): # needs further decoding (LDST no mapreduce)
130 comb
+= self
.pred_sz
.eq(mode
[SVP64MODE
.SZ
])
131 comb
+= self
.pred_dz
.eq(mode
[SVP64MODE
.DZ
])
132 with m
.Elif(mode
[SVP64MODE
.REDUCE
]):
133 with m
.If(self
.rm_in
.subvl
== Const(0, 2)): # no SUBVL
134 comb
+= self
.pred_dz
.eq(mode
[SVP64MODE
.DZ
])
136 comb
+= self
.pred_sz
.eq(mode
[SVP64MODE
.SZ
])
137 comb
+= self
.pred_dz
.eq(mode
[SVP64MODE
.DZ
])
140 with m
.If(~self
.ldst_ra_vec
):
141 comb
+= self
.pred_dz
.eq(mode
[SVP64MODE
.DZ
])
142 with m
.Elif(self
.rc_in
):
143 comb
+= self
.pred_dz
.eq(mode
[SVP64MODE
.DZ
])
145 with m
.If(is_ldst
& ~self
.ldst_ra_vec
):
146 comb
+= self
.pred_dz
.eq(mode
[SVP64MODE
.DZ
])
148 comb
+= self
.pred_sz
.eq(mode
[SVP64MODE
.SZ
])
149 comb
+= self
.pred_dz
.eq(mode
[SVP64MODE
.DZ
])
152 with m
.Switch(mode2
):
154 with m
.If(mode
[SVP64MODE
.N
]):
155 comb
+= self
.saturate
.eq(SVP64sat
.UNSIGNED
)
157 comb
+= self
.saturate
.eq(SVP64sat
.SIGNED
)
159 comb
+= self
.saturate
.eq(SVP64sat
.NONE
)
161 # extract els (element strided mode bit)
162 # see https://libre-soc.org/openpower/sv/ldst/
165 with m
.Switch(mode2
):
167 comb
+= els
.eq(mode
[SVP64MODE
.ELS_NORMAL
])
169 comb
+= els
.eq(mode
[SVP64MODE
.ELS_SAT
])
171 with m
.If(self
.rc_in
):
172 comb
+= els
.eq(mode
[SVP64MODE
.ELS_FFIRST_PRED
])
175 with m
.If(self
.ldst_ra_vec
):
176 comb
+= self
.ldstmode
.eq(SVP64LDSTmode
.INDEXED
)
177 # not element-strided, therefore unit...
179 comb
+= self
.ldstmode
.eq(SVP64LDSTmode
.UNITSTRIDE
)
180 # but if the LD/ST immediate is zero, allow cache-inhibited
181 # loads from same location, therefore don't do element-striding
182 with m
.Elif(~self
.ldst_imz_in
):
183 comb
+= self
.ldstmode
.eq(SVP64LDSTmode
.ELSTRIDE
)
185 # extract src/dest predicate. use EXTRA3.MASK because EXTRA2.MASK
186 # is in exactly the same bits
187 srcmask
= sel(m
, self
.rm_in
.extra
, EXTRA3
.MASK
)
188 dstmask
= self
.rm_in
.mask
189 with m
.If(self
.ptype_in
== SVPtype
.P2
):
190 comb
+= self
.srcpred
.eq(srcmask
)
192 comb
+= self
.srcpred
.eq(dstmask
)
193 comb
+= self
.dstpred
.eq(dstmask
)
195 # identify predicate mode
196 with m
.If(self
.rm_in
.mmode
== 1):
197 comb
+= self
.predmode
.eq(SVP64PredMode
.CR
) # CR Predicate
198 with m
.Elif((self
.srcpred
== 0) & (self
.dstpred
== 0)):
199 comb
+= self
.predmode
.eq(SVP64PredMode
.ALWAYS
) # No predicate
201 comb
+= self
.predmode
.eq(SVP64PredMode
.INT
) # non-zero src: INT
203 # TODO: detect zeroing mode, saturation mode, a few more.