src/openpower/decoder/test/test_power_decoder.py

   1 from nmigen import Module, Signal
   2
   3 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
   4 # Also, check out the cxxsim nmigen branch, and latest yosys from git
   5 from nmutil.sim_tmp_alternative import Simulator, Delay
   6
   7 from nmutil.formaltest import FHDLTestCase
   8 from nmigen.cli import rtlil
   9 import os
  10 import unittest
  11 from soc.decoder.power_decoder import (create_pdecode)
  12 from soc.decoder.power_enums import (Function, MicrOp,
  13                                      In1Sel, In2Sel, In3Sel,
  14                                      CRInSel, CROutSel,
  15                                      OutSel, RC, LdstLen, CryIn,
  16                                      single_bit_flags,
  17                                      get_signal_name, get_csv)
  18
  19
  20 class DecoderTestCase(FHDLTestCase):
  21
  22     def run_tst(self, bitsel, csvname, minor=None, suffix=None, opint=True):
  23         m = Module()
  24         comb = m.d.comb
  25         opcode = Signal(32)
  26         function_unit = Signal(Function)
  27         internal_op = Signal(MicrOp)
  28         in1_sel = Signal(In1Sel)
  29         in2_sel = Signal(In2Sel)
  30         in3_sel = Signal(In3Sel)
  31         out_sel = Signal(OutSel)
  32         cr_in = Signal(CRInSel)
  33         cr_out = Signal(CROutSel)
  34         rc_sel = Signal(RC)
  35         ldst_len = Signal(LdstLen)
  36         cry_in = Signal(CryIn)
  37         bigendian = Signal()
  38         comb += bigendian.eq(1)
  39
  40         # opcodes = get_csv(csvname)
  41         m.submodules.dut = dut = create_pdecode()
  42         comb += [dut.raw_opcode_in.eq(opcode),
  43                  dut.bigendian.eq(bigendian),
  44                  function_unit.eq(dut.op.function_unit),
  45                  in1_sel.eq(dut.op.in1_sel),
  46                  in2_sel.eq(dut.op.in2_sel),
  47                  in3_sel.eq(dut.op.in3_sel),
  48                  out_sel.eq(dut.op.out_sel),
  49                  cr_in.eq(dut.op.cr_in),
  50                  cr_out.eq(dut.op.cr_out),
  51                  rc_sel.eq(dut.op.rc_sel),
  52                  ldst_len.eq(dut.op.ldst_len),
  53                  cry_in.eq(dut.op.cry_in),
  54                  internal_op.eq(dut.op.internal_op)]
  55
  56         sim = Simulator(m)
  57         opcodes = get_csv(csvname)
  58
  59         def process():
  60             for row in opcodes:
  61                 if not row['unit']:
  62                     continue
  63                 op = row['opcode']
  64                 if not opint:  # HACK: convert 001---10 to 0b00100010
  65                     op = "0b" + op.replace('-', '0')
  66                 print("opint", opint, row['opcode'], op)
  67                 print(row)
  68                 yield opcode.eq(0)
  69                 yield opcode[bitsel[0]:bitsel[1]].eq(int(op, 0))
  70                 if minor:
  71                     print(minor)
  72                     minorbits = minor[1]
  73                     yield opcode[minorbits[0]:minorbits[1]].eq(minor[0])
  74                 else:
  75                     # OR 0, 0, 0  ; 0x60000000 is decoded as a NOP
  76                     # If we're testing the OR instruction, make sure
  77                     # that the instruction is not 0x60000000
  78                     if int(op, 0) == 24:
  79                         yield opcode[24:25].eq(0b11)
  80
  81                 yield Delay(1e-6)
  82                 signals = [(function_unit, Function, 'unit'),
  83                            (internal_op, MicrOp, 'internal op'),
  84                            (in1_sel, In1Sel, 'in1'),
  85                            (in2_sel, In2Sel, 'in2'),
  86                            (in3_sel, In3Sel, 'in3'),
  87                            (out_sel, OutSel, 'out'),
  88                            (cr_in, CRInSel, 'CR in'),
  89                            (cr_out, CROutSel, 'CR out'),
  90                            (rc_sel, RC, 'rc'),
  91                            (cry_in, CryIn, 'cry in'),
  92                            (ldst_len, LdstLen, 'ldst len')]
  93                 for sig, enm, name in signals:
  94                     result = yield sig
  95                     expected = enm[row[name]]
  96                     msg = f"{sig.name} == {enm(result)}, expected: {expected}"
  97                     self.assertEqual(enm(result), expected, msg)
  98                 for bit in single_bit_flags:
  99                     sig = getattr(dut.op, get_signal_name(bit))
 100                     result = yield sig
 101                     expected = int(row[bit])
 102                     msg = f"{sig.name} == {result}, expected: {expected}"
 103                     self.assertEqual(expected, result, msg)
 104         sim.add_process(process)
 105         prefix = os.path.splitext(csvname)[0]
 106         with sim.write_vcd("%s.vcd" % prefix, "%s.gtkw" % prefix, traces=[
 107                 opcode, function_unit, internal_op,
 108                 in1_sel, in2_sel]):
 109             sim.run()
 110
 111     def generate_ilang(self):
 112         pdecode = create_pdecode()
 113         vl = rtlil.convert(pdecode, ports=pdecode.ports())
 114         with open("decoder.il", "w") as f:
 115             f.write(vl)
 116
 117     def test_major(self):
 118         self.run_tst((26, 32), "major.csv")
 119         self.generate_ilang()
 120
 121     def test_minor_19(self):
 122         self.run_tst((1, 11), "minor_19.csv", minor=(19, (26, 32)),
 123                      suffix=(0, 5))
 124
 125     # def test_minor_19_00000(self):
 126     #     self.run_tst((1, 11), "minor_19_00000.csv")
 127
 128     def test_minor_30(self):
 129         self.run_tst((1, 5), "minor_30.csv", minor=(30, (26, 32)))
 130
 131     def test_minor_31(self):
 132         self.run_tst((1, 11), "minor_31.csv", minor=(31, (26, 32)))
 133
 134     def test_minor_58(self):
 135         self.run_tst((0, 2), "minor_58.csv", minor=(58, (26, 32)))
 136
 137     def test_minor_62(self):
 138         self.run_tst((0, 2), "minor_62.csv", minor=(62, (26, 32)))
 139
 140     # #def test_minor_31_prefix(self):
 141     # #    self.run_tst(10, "minor_31.csv", suffix=(5, 10))
 142
 143     # def test_extra(self):
 144     #     self.run_tst(32, "extra.csv", opint=False)
 145     #     self.generate_ilang(32, "extra.csv", opint=False)
 146
 147
 148 if __name__ == "__main__":
 149     unittest.main()