df1692ffbfc480ca976e663ce765d6b02a22f4f7
2 from nmutil
.formaltest
import FHDLTestCase
3 from openpower
.simulator
.program
import Program
4 from openpower
.simulator
.qemu
import run_program
5 from openpower
.test
.common
import TestCase
6 from openpower
.simulator
.test_sim
import DecoderBase
7 from openpower
.endian
import bigendian
11 class MulTestCases(FHDLTestCase
):
14 def __init__(self
, name
="div"):
15 super().__init
__(name
)
19 lst
= ["addi 1, 0, 0x5678",
22 self
.run_tst_program(Program(lst
, bigendian
), [3])
24 def test_mullwo(self
):
25 lst
= ["addi 1, 0, 0x5678",
30 self
.run_tst_program(Program(lst
, bigendian
), [3])
32 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None,
34 initial_regs
= [0] * 32
35 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
, 0,
37 self
.test_data
.append(tc
)
40 class MulDecoderTestCase(DecoderBase
, MulTestCases
):
44 if __name__
== "__main__":