e1642105e4cee51f3df366a1bd8c34b89031197c
1 from nmigen
import Module
, Signal
2 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
3 from nmutil
.formaltest
import FHDLTestCase
5 from soc
.decoder
.power_decoder
import (create_pdecode
)
6 from soc
.decoder
.power_enums
import (Function
, MicrOp
,
7 In1Sel
, In2Sel
, In3Sel
,
8 OutSel
, RC
, LdstLen
, CryIn
,
9 single_bit_flags
, Form
, SPR
,
10 get_signal_name
, get_csv
)
11 from soc
.decoder
.power_decoder2
import (PowerDecode2
)
12 from soc
.simulator
.program
import Program
13 from soc
.simulator
.qemu
import run_program
14 from soc
.decoder
.isa
.all
import ISA
15 from soc
.fu
.test
.common
import TestCase
16 from soc
.simulator
.test_sim
import DecoderBase
17 from soc
.config
.endian
import bigendian
21 class MulTestCases(FHDLTestCase
):
24 def __init__(self
, name
="div"):
25 super().__init
__(name
)
28 def test_1_extswsli(self
):
29 lst
= ["addi 1, 0, 0x5678",
31 self
.run_tst_program(Program(lst
, bigendian
), [3])
33 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None,
35 initial_regs
= [0] * 32
36 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
, 0,
38 self
.test_data
.append(tc
)
41 class MulDecoderTestCase(DecoderBase
, MulTestCases
):
45 if __name__
== "__main__":