03d7d8290a8da80e8346d386d790276d5062e066
2 from nmigen
import Module
3 from nmigen
.back
.pysim
import Simulator
, Delay
, Settle
4 from nmutil
.formaltest
import FHDLTestCase
5 from openpower
.decoder
.power_decoder
import create_pdecode
6 from openpower
.decoder
.power_decoder2
import (PowerDecode2
)
7 from openpower
.simulator
.program
import Program
8 from openpower
.simulator
.qemu
import run_program
9 from openpower
.decoder
.isa
.all
import ISA
10 from openpower
.test
.common
import TestCase
11 from openpower
.endian
import bigendian
14 class AttnTestCase(FHDLTestCase
):
17 def __init__(self
, name
="general"):
18 super().__init
__(name
)
21 def test_0_attn(self
):
22 """simple test of attn. program is 4 long: should halt at 2nd op
24 lst
= ["addi 6, 0, 0x10",
29 with
Program(lst
, bigendian
) as program
:
30 self
.run_tst_program(program
, [1])
32 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None,
34 initial_regs
= [0] * 32
35 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
, 0,
37 self
.test_data
.append(tc
)
40 class GeneralTestCases(FHDLTestCase
):
43 def __init__(self
, name
="general"):
44 super().__init
__(name
)
47 @unittest.skip("disable")
48 def test_0_litex_bios_ctr_loop(self
):
50 32a4: ff ff 63 38 addi r3,r3,-1
51 32a8: 20 00 63 78 clrldi r3,r3,32
52 32ac: 01 00 23 39 addi r9,r3,1
53 32b0: a6 03 29 7d mtctr r9
55 32b8: fc ff 00 42 bdnz 32b4 <cdelay+0x10>
58 notes on converting pseudo-assembler to actual:
60 * bdnz target (equivalent to: bc 16,0,target)
61 * Clear left immediate clrldi ra,rs,n (n < 64) rldicl ra,rs,0,n
62 * CTR mtctr Rx mtspr 9,Rx
66 @unittest.skip("disable")
67 def test_0_litex_bios_cmp(self
):
68 """litex bios cmp test
70 lst
= [ "addis 26, 0, 21845",
80 with
Program(lst
, bigendian
) as program
:
81 self
.run_tst_program(program
, [5,6,7,26], initial_mem
={})
83 @unittest.skip("disable")
84 def test_0_litex_bios_r1(self
):
85 """litex bios IMM64 macro test
87 lst
= [ "addis 1,0,0",
93 with
Program(lst
, bigendian
) as program
:
94 self
.run_tst_program(program
, [1], initial_mem
={})
96 @unittest.skip("disable")
97 def test_0_litex_trampoline(self
):
98 lst
= ["tdi 0,0,0x48",
108 with
Program(lst
, bigendian
) as program
:
109 self
.run_tst_program(program
, [], initial_mem
={})
111 @unittest.skip("disable")
112 def test_0_cmp(self
):
113 lst
= ["addi 6, 0, 0x10",
118 with
Program(lst
, bigendian
) as program
:
119 self
.run_tst_program(program
, [1])
121 @unittest.skip("disable")
122 def test_example(self
):
123 lst
= ["addi 1, 0, 0x5678",
127 with
Program(lst
, bigendian
) as program
:
128 self
.run_tst_program(program
, [1, 2, 3, 4])
130 @unittest.skip("disable")
132 lst
= ["addi 1, 0, 0x5678",
137 initial_mem
= {0x1230: (0x5432123412345678, 8),
138 0x1238: (0xabcdef0187654321, 8),
140 with
Program(lst
, bigendian
) as program
:
141 self
.run_tst_program(program
,
145 @unittest.skip("disable")
146 def test_ldst_update(self
):
147 lst
= ["addi 1, 0, 0x5678",
152 initial_mem
= {0x1230: (0x5432123412345678, 8),
153 0x1238: (0xabcdef0187654321, 8),
155 with
Program(lst
, bigendian
) as program
:
156 self
.run_tst_program(program
,
160 @unittest.skip("disable")
161 def test_ld_rev_ext(self
):
162 lst
= ["addi 1, 0, 0x5678",
167 with
Program(lst
, bigendian
) as program
:
168 self
.run_tst_program(program
, [1, 2, 3])
170 @unittest.skip("disable")
171 def test_st_rev_ext(self
):
172 lst
= ["addi 1, 0, 0x5678",
177 with
Program(lst
, bigendian
) as program
:
178 self
.run_tst_program(program
, [1, 2, 3])
180 @unittest.skip("disable")
181 def test_ldst_extended(self
):
182 lst
= ["addi 1, 0, 0x5678",
187 with
Program(lst
, bigendian
) as program
:
188 self
.run_tst_program(program
, [1, 2, 3])
190 @unittest.skip("disable")
191 def test_0_ldst_widths(self
):
192 lst
= ["addis 1, 0, 0xdead",
202 with
Program(lst
, bigendian
) as program
:
203 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
205 @unittest.skip("disable")
207 lst
= ["addi 1, 0, 0x1234",
210 "subfic 4, 1, 0x1337",
212 with
Program(lst
, bigendian
) as program
:
213 self
.run_tst_program(program
, [1, 2, 3, 4, 5])
215 @unittest.skip("disable")
216 def test_add_with_carry(self
):
217 lst
= ["addi 1, 0, 5",
224 with
Program(lst
, bigendian
) as program
:
225 self
.run_tst_program(program
, [1, 2, 3])
227 @unittest.skip("disable")
228 def test_addis(self
):
229 lst
= ["addi 1, 0, 0x0FFF",
232 with
Program(lst
, bigendian
) as program
:
233 self
.run_tst_program(program
, [1])
235 @unittest.skip("broken")
236 def test_mulli(self
):
237 lst
= ["addi 1, 0, 3",
240 with
Program(lst
, bigendian
) as program
:
241 self
.run_tst_program(program
, [1])
243 #@unittest.skip("disable")
244 def test_crxor(self
):
245 lst
= ["addi 1, 0, 0x1004",
248 "mtcrf 0b1111111, 3",
252 initial_regs
= [0] * 32
253 initial_regs
[1] = 0x1004
254 initial_regs
[2] = 0x1008
255 initial_regs
[3] = 0x01ee
256 with
Program(lst
, bigendian
) as program
:
257 self
.run_tst_program(program
, [3, 4])
259 #@unittest.skip("disable")
260 def test_crxor_2(self
):
261 lst
= ["addi 1, 0, 0x1004",
264 "mtcrf 0b1111111, 3",
268 initial_regs
= [0] * 32
269 initial_regs
[1] = 0x1004
270 initial_regs
[2] = 0x1008
271 initial_regs
[3] = 0x01ee
272 with
Program(lst
, bigendian
) as program
:
273 self
.run_tst_program(program
, [3, 4])
275 #@unittest.skip("disable")
276 def test_crnand(self
):
277 lst
= ["addi 1, 0, 0x1004",
280 "mtcrf 0b1111111, 3",
284 initial_regs
= [0] * 32
285 initial_regs
[1] = 0x1004
286 initial_regs
[2] = 0x1008
287 initial_regs
[3] = 0x01ee
288 with
Program(lst
, bigendian
) as program
:
289 self
.run_tst_program(program
, [3, 4])
291 #@unittest.skip("disable")
292 def test_crnand_2(self
):
293 lst
= ["addi 1, 0, 0x1004",
296 "mtcrf 0b1111111, 3",
300 initial_regs
= [0] * 32
301 initial_regs
[1] = 0x1004
302 initial_regs
[2] = 0x1008
303 initial_regs
[3] = 0x01ee
304 with
Program(lst
, bigendian
) as program
:
305 self
.run_tst_program(program
, [3, 4])
307 @unittest.skip("disable")
308 def test_isel_1(self
):
309 lst
= ["addi 1, 0, 0x1004",
312 "mtcrf 0b1111111, 3",
315 initial_regs
= [0] * 32
316 initial_regs
[1] = 0x1004
317 initial_regs
[2] = 0x1008
318 initial_regs
[3] = 0x00ee
319 with
Program(lst
, bigendian
) as program
:
320 self
.run_tst_program(program
, [3, 4])
322 #@unittest.skip("disable")
323 def test_isel_2(self
):
324 lst
= ["addi 1, 0, 0x1004",
327 "mtcrf 0b1111111, 3",
330 initial_regs
= [0] * 32
331 initial_regs
[1] = 0x1004
332 initial_regs
[2] = 0x1008
333 initial_regs
[3] = 0x00ee
334 with
Program(lst
, bigendian
) as program
:
335 self
.run_tst_program(program
, [3, 4])
337 @unittest.skip("disable")
338 def test_isel_3(self
):
339 lst
= ["addi 1, 0, 0x1004",
342 "mtcrf 0b1111111, 3",
345 initial_regs
= [0] * 32
346 initial_regs
[1] = 0x1004
347 initial_regs
[2] = 0x1008
348 initial_regs
[3] = 0x00ee
349 with
Program(lst
, bigendian
) as program
:
350 self
.run_tst_program(program
, [3, 4])
352 @unittest.skip("disable")
353 def test_2_load_store(self
):
354 lst
= ["addi 1, 0, 0x1004",
360 initial_regs
= [0] * 32
361 initial_regs
[1] = 0x1004
362 initial_regs
[2] = 0x1008
363 initial_regs
[3] = 0x00ee
364 initial_mem
= {0x1000: (0x5432123412345678, 8),
365 0x1008: (0xabcdef0187654321, 8),
366 0x1020: (0x1828384822324252, 8),
368 with
Program(lst
, bigendian
) as program
:
369 self
.run_tst_program(program
, [3, 4], initial_mem
)
371 @unittest.skip("disable")
372 def test_3_load_store(self
):
373 lst
= ["addi 1, 0, 0x1004",
378 initial_regs
= [0] * 32
379 initial_regs
[1] = 0x1004
380 initial_regs
[2] = 0x1002
381 initial_regs
[3] = 0x15eb
382 initial_mem
= {0x1000: (0x5432123412345678, 8),
383 0x1008: (0xabcdef0187654321, 8),
384 0x1020: (0x1828384822324252, 8),
386 with
Program(lst
, bigendian
) as program
:
387 self
.run_tst_program(program
, [1, 2, 3, 4], initial_mem
)
389 @unittest.skip("disable")
391 lst
= ["addi 1, 0, 0x1004",
392 "ori 0,0,0", # "preferred" form of nop
395 initial_regs
= [0] * 32
396 with
Program(lst
, bigendian
) as program
:
397 self
.run_tst_program(program
, [1, 3])
399 @unittest.skip("disable")
400 def test_zero_illegal(self
):
401 lst
= bytes([0x10,0x00,0x20,0x39,
404 disassembly
= ["addi 9, 0, 0x10",
407 initial_regs
= [0] * 32
408 with
Program(lst
, bigendian
) as program
:
409 program
.assembly
= '\n'.join(disassembly
) + '\n' # XXX HACK!
410 self
.run_tst_program(program
, [1, 3])
415 register unsigned long i asm ("r9");
423 lst
= ["addi 9, 0, 0x10", # i = 16
424 "addi 9,9,-1", # i = i - 1
425 "cmpi 2,1,9,12", # compare 9 to value 12, store in CR2
426 "bc 4,10,-8" # branch if CR2 "test was != 12"
428 with
Program(lst
, bigendian
) as program
:
429 self
.run_tst_program(program
, [9], initial_mem
={})
431 @unittest.skip("disable")
432 def test_30_addis(self
):
433 lst
= [ # "addi 0, 0, 5",
436 with
Program(lst
, bigendian
) as program
:
437 self
.run_tst_program(program
, [12])
439 @unittest.skip("disable")
440 def test_31_addis(self
):
441 """tests for zero not in register zero
443 lst
= [ "rldicr 0, 0, 32, 31",
448 "rldicr 1, 1, 32, 31",
453 with
Program(lst
, bigendian
) as program
:
454 self
.run_tst_program(program
, [0, 1, 2])
456 def run_tst_program(self
, prog
, initial_regs
=None, initial_sprs
=None,
458 initial_regs
= [0] * 32
459 tc
= TestCase(prog
, self
.test_name
, initial_regs
, initial_sprs
, 0,
461 self
.test_data
.append(tc
)
466 def run_tst(self
, generator
, initial_mem
=None, initial_pc
=0):
470 gen
= list(generator
.generate_instructions())
471 insn_code
= generator
.assembly
.splitlines()
472 instructions
= list(zip(gen
, insn_code
))
474 pdecode
= create_pdecode()
475 m
.submodules
.pdecode2
= pdecode2
= PowerDecode2(pdecode
)
477 # place program at requested address
478 gen
= (initial_pc
, gen
)
480 simulator
= ISA(pdecode2
, [0] * 32, {}, 0, initial_mem
, 0,
481 initial_insns
=gen
, respect_pc
=True,
482 disassembly
=insn_code
,
483 initial_pc
=initial_pc
,
489 # yield pdecode2.dec.bigendian.eq(bigendian)
494 yield from simulator
.setup_one()
495 except KeyError: # indicates instruction not in imem: stop
498 yield from simulator
.execute_one()
501 sim
.add_process(process
)
502 with sim
.write_vcd("pdecode_simulator.vcd"):
507 def run_tst_program(self
, prog
, reglist
, initial_mem
=None,
508 extra_break_addr
=None):
510 simulator
= self
.run_tst(prog
, initial_mem
=initial_mem
,
511 initial_pc
=0x20000000)
513 with
run_program(prog
, initial_mem
, extra_break_addr
,
514 bigendian
=bigendian
) as q
:
515 self
.qemu_register_compare(simulator
, q
, reglist
)
516 self
.qemu_mem_compare(simulator
, q
, True)
517 print(simulator
.gpr
.dump())
519 def qemu_mem_compare(self
, sim
, qemu
, check
=True):
520 if False: # disable convenient large interesting debugging memory dump
522 qmemdump
= qemu
.get_mem(addr
, 2048)
523 for i
in range(len(qmemdump
)):
524 s
= hex(int(qmemdump
[i
]))
525 print("qemu mem %06x %s" % (addr
+i
*8, s
))
526 for k
, v
in sim
.mem
.mem
.items():
527 qmemdump
= qemu
.get_mem(k
*8, 8)
528 s
= hex(int(qmemdump
[0]))[2:]
529 print("qemu mem %06x %16s" % (k
*8, s
))
530 for k
, v
in sim
.mem
.mem
.items():
531 print("sim mem %06x %016x" % (k
*8, v
))
534 for k
, v
in sim
.mem
.mem
.items():
535 qmemdump
= qemu
.get_mem(k
*8, 1)
536 self
.assertEqual(int(qmemdump
[0]), v
)
538 def qemu_register_compare(self
, sim
, qemu
, regs
):
539 qpc
, qxer
, qcr
= qemu
.get_pc(), qemu
.get_xer(), qemu
.get_cr()
540 sim_cr
= sim
.cr
.value
541 sim_pc
= sim
.pc
.CIA
.value
542 sim_xer
= sim
.spr
['XER'].value
543 print("qemu pc", hex(qpc
))
544 print("qemu cr", hex(qcr
))
545 print("qemu xer", bin(qxer
))
546 print("sim nia", hex(sim
.pc
.NIA
.value
))
547 print("sim pc", hex(sim
.pc
.CIA
.value
))
548 print("sim cr", hex(sim_cr
))
549 print("sim xer", hex(sim_xer
))
550 self
.assertEqual(qpc
, sim_pc
)
552 qemu_val
= qemu
.get_gpr(reg
)
553 sim_val
= sim
.gpr(reg
).value
554 self
.assertEqual(qemu_val
, sim_val
,
555 "expect %x got %x" % (qemu_val
, sim_val
))
556 self
.assertEqual(qcr
, sim_cr
)
559 class DecoderTestCase(DecoderBase
, GeneralTestCases
):
563 if __name__
== "__main__":