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[openpower-isa.git] / src / openpower / sv / trans / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 """SVP64 OpenPOWER v3.0B assembly translator
6
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and creates
8 an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode.
9
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
12
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/
15 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
16 """
17
18 import os, sys
19 from collections import OrderedDict
20
21 from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
22 SV64P_PID_SIZE, SVP64RMFields,
23 SVP64RM_EXTRA2_SPEC_SIZE,
24 SVP64RM_EXTRA3_SPEC_SIZE,
25 SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
26 SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
27 SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
28 SVP64RM_ELWIDTH_SIZE)
29 from openpower.decoder.pseudo.pagereader import ISA
30 from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
31 from openpower.decoder.selectable_int import SelectableInt
32 from openpower.consts import SVP64MODE
33
34 # for debug logging
35 from openpower.util import log
36
37
38 # decode GPR into sv extra
39 def get_extra_gpr(etype, regmode, field):
40 if regmode == 'scalar':
41 # cut into 2-bits 5-bits SS FFFFF
42 sv_extra = field >> 5
43 field = field & 0b11111
44 else:
45 # cut into 5-bits 2-bits FFFFF SS
46 sv_extra = field & 0b11
47 field = field >> 2
48 return sv_extra, field
49
50
51 # decode 3-bit CR into sv extra
52 def get_extra_cr_3bit(etype, regmode, field):
53 if regmode == 'scalar':
54 # cut into 2-bits 3-bits SS FFF
55 sv_extra = field >> 3
56 field = field & 0b111
57 else:
58 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
59 sv_extra = field & 0b1111
60 field = field >> 4
61 return sv_extra, field
62
63
64 # decodes SUBVL
65 def decode_subvl(encoding):
66 pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
67 assert encoding in pmap, \
68 "encoding %s for SUBVL not recognised" % encoding
69 return pmap[encoding]
70
71
72 # decodes elwidth
73 def decode_elwidth(encoding):
74 pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
75 assert encoding in pmap, \
76 "encoding %s for elwidth not recognised" % encoding
77 return pmap[encoding]
78
79
80 # decodes predicate register encoding
81 def decode_predicate(encoding):
82 pmap = { # integer
83 '1<<r3': (0, 0b001),
84 'r3' : (0, 0b010),
85 '~r3' : (0, 0b011),
86 'r10' : (0, 0b100),
87 '~r10' : (0, 0b101),
88 'r30' : (0, 0b110),
89 '~r30' : (0, 0b111),
90 # CR
91 'lt' : (1, 0b000),
92 'nl' : (1, 0b001), 'ge' : (1, 0b001), # same value
93 'gt' : (1, 0b010),
94 'ng' : (1, 0b011), 'le' : (1, 0b011), # same value
95 'eq' : (1, 0b100),
96 'ne' : (1, 0b101),
97 'so' : (1, 0b110), 'un' : (1, 0b110), # same value
98 'ns' : (1, 0b111), 'nu' : (1, 0b111), # same value
99 }
100 assert encoding in pmap, \
101 "encoding %s for predicate not recognised" % encoding
102 return pmap[encoding]
103
104
105 # decodes "Mode" in similar way to BO field (supposed to, anyway)
106 def decode_bo(encoding):
107 pmap = { # TODO: double-check that these are the same as Branch BO
108 'lt' : 0b000,
109 'nl' : 0b001, 'ge' : 0b001, # same value
110 'gt' : 0b010,
111 'ng' : 0b011, 'le' : 0b011, # same value
112 'eq' : 0b100,
113 'ne' : 0b101,
114 'so' : 0b110, 'un' : 0b110, # same value
115 'ns' : 0b111, 'nu' : 0b111, # same value
116 }
117 assert encoding in pmap, \
118 "encoding %s for BO Mode not recognised" % encoding
119 return pmap[encoding]
120
121 # partial-decode fail-first mode
122 def decode_ffirst(encoding):
123 if encoding in ['RC1', '~RC1']:
124 return encoding
125 return decode_bo(encoding)
126
127
128 def decode_reg(field):
129 # decode the field number. "5.v" or "3.s" or "9"
130 field = field.split(".")
131 regmode = 'scalar' # default
132 if len(field) == 2:
133 if field[1] == 's':
134 regmode = 'scalar'
135 elif field[1] == 'v':
136 regmode = 'vector'
137 field = int(field[0]) # actual register number
138 return field, regmode
139
140
141 def decode_imm(field):
142 ldst_imm = "(" in field and field[-1] == ')'
143 if ldst_imm:
144 return field[:-1].split("(")
145 else:
146 return None, field
147
148
149 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
150 class SVP64Asm:
151 def __init__(self, lst, bigendian=False):
152 self.lst = lst
153 self.trans = self.translate(lst)
154 self.isa = ISA() # reads the v3.0B pseudo-code markdown files
155 self.svp64 = SVP64RM() # reads the svp64 Remap entries for registers
156 assert bigendian == False, "error, bigendian not supported yet"
157
158 def __iter__(self):
159 yield from self.trans
160
161 def translate_one(self, insn):
162 isa = self.isa
163 svp64 = self.svp64
164 # find first space, to get opcode
165 ls = insn.split(' ')
166 opcode = ls[0]
167 # now find opcode fields
168 fields = ''.join(ls[1:]).split(',')
169 fields = list(map(str.strip, fields))
170 log ("opcode, fields", ls, opcode, fields)
171
172 # sigh have to do setvl here manually for now...
173 if opcode in ["setvl", "setvl."]:
174 insn = 22 << (31-5) # opcode 22, bits 0-5
175 fields = list(map(int, fields))
176 insn |= fields[0] << (31-10) # RT , bits 6-10
177 insn |= fields[1] << (31-15) # RA , bits 11-15
178 insn |= fields[2] << (31-23) # SVi , bits 16-23
179 insn |= fields[3] << (31-24) # vs , bit 24
180 insn |= fields[4] << (31-25) # ms , bit 25
181 insn |= 0b00000 << (31-30) # XO , bits 26..30
182 if opcode == 'setvl.':
183 insn |= 1 << (31-31) # Rc=1 , bit 31
184 log ("setvl", bin(insn))
185 yield ".long 0x%x" % insn
186 return
187
188 # identify if is a svp64 mnemonic
189 if not opcode.startswith('sv.'):
190 yield insn # unaltered
191 return
192 opcode = opcode[3:] # strip leading "sv"
193
194 # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
195 opmodes = opcode.split("/") # split at "/"
196 v30b_op = opmodes.pop(0) # first is the v3.0B
197 # check instruction ends with dot
198 rc_mode = v30b_op.endswith('.')
199 if rc_mode:
200 v30b_op = v30b_op[:-1]
201
202 if v30b_op not in isa.instr:
203 raise Exception("opcode %s of '%s' not supported" % \
204 (v30b_op, insn))
205 if v30b_op not in svp64.instrs:
206 raise Exception("opcode %s of '%s' not an svp64 instruction" % \
207 (v30b_op, insn))
208 v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
209 rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV
210 log ("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
211 log ("v3.0B regs", opcode, v30b_regs)
212 log ("RM", rm)
213
214 # right. the first thing to do is identify the ordering of
215 # the registers, by name. the EXTRA2/3 ordering is in
216 # rm['0']..rm['3'] but those fields contain the names RA, BB
217 # etc. we have to read the pseudocode to understand which
218 # reg is which in our instruction. sigh.
219
220 # first turn the svp64 rm into a "by name" dict, recording
221 # which position in the RM EXTRA it goes into
222 # also: record if the src or dest was a CR, for sanity-checking
223 # (elwidth overrides on CRs are banned)
224 decode = decode_extra(rm)
225 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
226
227 log ("EXTRA field index, src", svp64_src)
228 log ("EXTRA field index, dest", svp64_dest)
229
230 # okaaay now we identify the field value (opcode N,N,N) with
231 # the pseudo-code info (opcode RT, RA, RB)
232 assert len(fields) == len(v30b_regs), \
233 "length of fields %s must match insn `%s`" % \
234 (str(v30b_regs), insn)
235 opregfields = zip(fields, v30b_regs) # err that was easy
236
237 # now for each of those find its place in the EXTRA encoding
238 # note there is the possibility (for LD/ST-with-update) of
239 # RA occurring **TWICE**. to avoid it getting added to the
240 # v3.0B suffix twice, we spot it as a duplicate, here
241 extras = OrderedDict()
242 for idx, (field, regname) in enumerate(opregfields):
243 imm, regname = decode_imm(regname)
244 rtype = get_regtype(regname)
245 log (" idx find", idx, field, regname, imm)
246 extra = svp64_src.get(regname, None)
247 if extra is not None:
248 extra = ('s', extra, False) # not a duplicate
249 extras[extra] = (idx, field, regname, rtype, imm)
250 log (" idx src", idx, extra, extras[extra])
251 dextra = svp64_dest.get(regname, None)
252 log ("regname in", regname, dextra)
253 if dextra is not None:
254 is_a_duplicate = extra is not None # duplicate spotted
255 dextra = ('d', dextra, is_a_duplicate)
256 extras[dextra] = (idx, field, regname, rtype, imm)
257 log (" idx dst", idx, extra, extras[dextra])
258
259 # great! got the extra fields in their associated positions:
260 # also we know the register type. now to create the EXTRA encodings
261 etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
262 ptype = rm['Ptype'] # Predication type: Twin / Single
263 extra_bits = 0
264 v30b_newfields = []
265 for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
266 # is it a field we don't alter/examine? if so just put it
267 # into newfields
268 if rtype is None:
269 v30b_newfields.append(field)
270
271 # identify if this is a ld/st immediate(reg) thing
272 ldst_imm = "(" in field and field[-1] == ')'
273 if ldst_imm:
274 immed, field = field[:-1].split("(")
275
276 field, regmode = decode_reg(field)
277 log (" ", extra_idx, rname, rtype,
278 regmode, iname, field, end=" ")
279
280 # see Mode field https://libre-soc.org/openpower/sv/svp64/
281 # XXX TODO: the following is a bit of a laborious repeated
282 # mess, which could (and should) easily be parameterised.
283 # XXX also TODO: the LD/ST modes which are different
284 # https://libre-soc.org/openpower/sv/ldst/
285
286 # encode SV-GPR and SV-FPR field into extra, v3.0field
287 if rtype in ['GPR', 'FPR']:
288 sv_extra, field = get_extra_gpr(etype, regmode, field)
289 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
290 # (and shrink to a single bit if ok)
291 if etype == 'EXTRA2':
292 if regmode == 'scalar':
293 # range is r0-r63 in increments of 1
294 assert (sv_extra >> 1) == 0, \
295 "scalar GPR %s cannot fit into EXTRA2 %s" % \
296 (rname, str(extras[extra_idx]))
297 # all good: encode as scalar
298 sv_extra = sv_extra & 0b01
299 else:
300 # range is r0-r127 in increments of 4
301 assert sv_extra & 0b01 == 0, \
302 "%s: vector field %s cannot fit " \
303 "into EXTRA2 %s" % \
304 (insn, rname, str(extras[extra_idx]))
305 # all good: encode as vector (bit 2 set)
306 sv_extra = 0b10 | (sv_extra >> 1)
307 elif regmode == 'vector':
308 # EXTRA3 vector bit needs marking
309 sv_extra |= 0b100
310
311 # encode SV-CR 3-bit field into extra, v3.0field
312 elif rtype == 'CR_3bit':
313 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
314 # now sanity-check (and shrink afterwards)
315 if etype == 'EXTRA2':
316 if regmode == 'scalar':
317 # range is CR0-CR15 in increments of 1
318 assert (sv_extra >> 1) == 0, \
319 "scalar CR %s cannot fit into EXTRA2 %s" % \
320 (rname, str(extras[extra_idx]))
321 # all good: encode as scalar
322 sv_extra = sv_extra & 0b01
323 else:
324 # range is CR0-CR127 in increments of 16
325 assert sv_extra & 0b111 == 0, \
326 "vector CR %s cannot fit into EXTRA2 %s" % \
327 (rname, str(extras[extra_idx]))
328 # all good: encode as vector (bit 2 set)
329 sv_extra = 0b10 | (sv_extra >> 3)
330 else:
331 if regmode == 'scalar':
332 # range is CR0-CR31 in increments of 1
333 assert (sv_extra >> 2) == 0, \
334 "scalar CR %s cannot fit into EXTRA2 %s" % \
335 (rname, str(extras[extra_idx]))
336 # all good: encode as scalar
337 sv_extra = sv_extra & 0b11
338 else:
339 # range is CR0-CR127 in increments of 8
340 assert sv_extra & 0b11 == 0, \
341 "vector CR %s cannot fit into EXTRA2 %s" % \
342 (rname, str(extras[extra_idx]))
343 # all good: encode as vector (bit 3 set)
344 sv_extra = 0b100 | (sv_extra >> 2)
345
346 # encode SV-CR 5-bit field into extra, v3.0field
347 # *sigh* this is the same as 3-bit except the 2 LSBs are
348 # passed through
349 elif rtype == 'CR_5bit':
350 cr_subfield = field & 0b11
351 field = field >> 2 # strip bottom 2 bits
352 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
353 # now sanity-check (and shrink afterwards)
354 if etype == 'EXTRA2':
355 if regmode == 'scalar':
356 # range is CR0-CR15 in increments of 1
357 assert (sv_extra >> 1) == 0, \
358 "scalar CR %s cannot fit into EXTRA2 %s" % \
359 (rname, str(extras[extra_idx]))
360 # all good: encode as scalar
361 sv_extra = sv_extra & 0b01
362 else:
363 # range is CR0-CR127 in increments of 16
364 assert sv_extra & 0b111 == 0, \
365 "vector CR %s cannot fit into EXTRA2 %s" % \
366 (rname, str(extras[extra_idx]))
367 # all good: encode as vector (bit 2 set)
368 sv_extra = 0b10 | (sv_extra >> 3)
369 else:
370 if regmode == 'scalar':
371 # range is CR0-CR31 in increments of 1
372 assert (sv_extra >> 2) == 0, \
373 "scalar CR %s cannot fit into EXTRA2 %s" % \
374 (rname, str(extras[extra_idx]))
375 # all good: encode as scalar
376 sv_extra = sv_extra & 0b11
377 else:
378 # range is CR0-CR127 in increments of 8
379 assert sv_extra & 0b11 == 0, \
380 "vector CR %s cannot fit into EXTRA2 %s" % \
381 (rname, str(extras[extra_idx]))
382 # all good: encode as vector (bit 3 set)
383 sv_extra = 0b100 | (sv_extra >> 2)
384
385 # reconstruct the actual 5-bit CR field
386 field = (field << 2) | cr_subfield
387
388 # capture the extra field info
389 log ("=>", "%5s" % bin(sv_extra), field)
390 extras[extra_idx] = sv_extra
391
392 # append altered field value to v3.0b, differs for LDST
393 # note that duplicates are skipped e.g. EXTRA2 contains
394 # *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
395 srcdest, idx, duplicate = extra_idx
396 if duplicate: # skip adding to v3.0b fields, already added
397 continue
398 if ldst_imm:
399 v30b_newfields.append(("%s(%s)" % (immed, str(field))))
400 else:
401 v30b_newfields.append(str(field))
402
403 log ("new v3.0B fields", v30b_op, v30b_newfields)
404 log ("extras", extras)
405
406 # rright. now we have all the info. start creating SVP64 RM
407 svp64_rm = SVP64RMFields()
408
409 # begin with EXTRA fields
410 for idx, sv_extra in extras.items():
411 if idx is None: continue
412 log (idx)
413 srcdest, idx, duplicate = idx
414 if etype == 'EXTRA2':
415 svp64_rm.extra2[idx].eq(
416 SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
417 else:
418 svp64_rm.extra3[idx].eq(
419 SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
420
421 # identify if the op is a LD/ST. the "blegh" way. copied
422 # from power_enums. TODO, split the list _insns down.
423 is_ld = v30b_op in [
424 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
425 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
426 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
427 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load double
428 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
429 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
430 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
431 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
432 ]
433 is_st = v30b_op in [
434 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
435 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
436 "stfs", "stfsx", "stfsu", "stfux", # FP store single
437 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store double
438 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
439 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
440 ]
441 # use this to determine if the SVP64 RM format is different.
442 # see https://libre-soc.org/openpower/sv/ldst/
443 is_ldst = is_ld or is_st
444
445 # parts of svp64_rm
446 mmode = 0 # bit 0
447 pmask = 0 # bits 1-3
448 destwid = 0 # bits 4-5
449 srcwid = 0 # bits 6-7
450 subvl = 0 # bits 8-9
451 smask = 0 # bits 16-18 but only for twin-predication
452 mode = 0 # bits 19-23
453
454 mask_m_specified = False
455 has_pmask = False
456 has_smask = False
457
458 saturation = None
459 src_zero = 0
460 dst_zero = 0
461 sv_mode = None
462
463 mapreduce = False
464 mapreduce_crm = False
465 mapreduce_svm = False
466
467 predresult = False
468 failfirst = False
469 ldst_elstride = 0
470
471 # ok let's start identifying opcode augmentation fields
472 for encmode in opmodes:
473 # predicate mask (src and dest)
474 if encmode.startswith("m="):
475 pme = encmode
476 pmmode, pmask = decode_predicate(encmode[2:])
477 smmode, smask = pmmode, pmask
478 mmode = pmmode
479 mask_m_specified = True
480 # predicate mask (dest)
481 elif encmode.startswith("dm="):
482 pme = encmode
483 pmmode, pmask = decode_predicate(encmode[3:])
484 mmode = pmmode
485 has_pmask = True
486 # predicate mask (src, twin-pred)
487 elif encmode.startswith("sm="):
488 sme = encmode
489 smmode, smask = decode_predicate(encmode[3:])
490 mmode = smmode
491 has_smask = True
492 # vec2/3/4
493 elif encmode.startswith("vec"):
494 subvl = decode_subvl(encmode[3:])
495 # elwidth
496 elif encmode.startswith("ew="):
497 destwid = decode_elwidth(encmode[3:])
498 elif encmode.startswith("sw="):
499 srcwid = decode_elwidth(encmode[3:])
500 # element-strided LD/ST
501 elif encmode == 'els':
502 ldst_elstride = 1
503 # saturation
504 elif encmode == 'sats':
505 assert sv_mode is None
506 saturation = 1
507 sv_mode = 0b10
508 elif encmode == 'satu':
509 assert sv_mode is None
510 sv_mode = 0b10
511 saturation = 0
512 # predicate zeroing
513 elif encmode == 'sz':
514 src_zero = 1
515 elif encmode == 'dz':
516 dst_zero = 1
517 # failfirst
518 elif encmode.startswith("ff="):
519 assert sv_mode is None
520 sv_mode = 0b01
521 failfirst = decode_ffirst(encmode[3:])
522 # predicate-result, interestingly same as fail-first
523 elif encmode.startswith("pr="):
524 assert sv_mode is None
525 sv_mode = 0b11
526 predresult = decode_ffirst(encmode[3:])
527 # map-reduce mode
528 elif encmode == 'mr':
529 assert sv_mode is None
530 sv_mode = 0b00
531 mapreduce = True
532 elif encmode == 'crm': # CR on map-reduce
533 assert sv_mode is None
534 sv_mode = 0b00
535 mapreduce_crm = True
536 elif encmode == 'svm': # sub-vector mode
537 mapreduce_svm = True
538 else:
539 raise AssertionError("unknown encmode %s" % encmode)
540
541 if ptype == '2P':
542 # since m=xx takes precedence (overrides) sm=xx and dm=xx,
543 # treat them as mutually exclusive
544 if mask_m_specified:
545 assert not has_smask,\
546 "cannot have both source-mask and predicate mask"
547 assert not has_pmask,\
548 "cannot have both dest-mask and predicate mask"
549 # since the default is INT predication (ALWAYS), if you
550 # specify one CR mask, you must specify both, to avoid
551 # mixing INT and CR reg types
552 if has_pmask and pmmode == 1:
553 assert has_smask, \
554 "need explicit source-mask in CR twin predication"
555 if has_smask and smmode == 1:
556 assert has_pmask, \
557 "need explicit dest-mask in CR twin predication"
558 # sanity-check that 2Pred mask is same mode
559 if has_pmask and has_smask:
560 assert smmode == pmmode, \
561 "predicate masks %s and %s must be same reg type" % \
562 (pme, sme)
563
564 # sanity-check that twin-predication mask only specified in 2P mode
565 if ptype == '1P':
566 assert not has_smask, \
567 "source-mask can only be specified on Twin-predicate ops"
568 assert not has_pmask, \
569 "dest-mask can only be specified on Twin-predicate ops"
570
571 # construct the mode field, doing sanity-checking along the way
572 if mapreduce_svm:
573 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
574 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
575
576 if src_zero:
577 assert has_smask or mask_m_specified, \
578 "src zeroing requires a source predicate"
579 if dst_zero:
580 assert has_pmask or mask_m_specified, \
581 "dest zeroing requires a dest predicate"
582
583 ######################################
584 # "normal" mode
585 if sv_mode is None:
586 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
587 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
588 if is_ldst:
589 # TODO: for now, LD/ST-indexed is ignored.
590 mode |= ldst_elstride << SVP64MODE.ELS_NORMAL # element-strided
591 else:
592 # TODO, reduce and subvector mode
593 # 00 1 dz CRM reduce mode (mapreduce), SUBVL=1
594 # 00 1 SVM CRM subvector reduce mode, SUBVL>1
595 pass
596 sv_mode = 0b00
597
598 ######################################
599 # "mapreduce" modes
600 elif sv_mode == 0b00:
601 mode |= (0b1<<SVP64MODE.REDUCE) # sets mapreduce
602 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
603 if mapreduce_crm:
604 mode |= (0b1<<SVP64MODE.CRM) # sets CRM mode
605 assert rc_mode, "CRM only allowed when Rc=1"
606 # bit of weird encoding to jam zero-pred or SVM mode in.
607 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
608 if subvl == 0:
609 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
610 elif mapreduce_svm:
611 mode |= (0b1<<SVP64MODE.SVM) # sets SVM mode
612
613 ######################################
614 # "failfirst" modes
615 elif sv_mode == 0b01:
616 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
617 if failfirst == 'RC1':
618 mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
619 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
620 assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
621 elif failfirst == '~RC1':
622 mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
623 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
624 mode |= (0b1<<SVP64MODE.INV) # ... with inversion
625 assert rc_mode==False, "ffirst RC1 only possible when Rc=0"
626 else:
627 assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
628 assert rc_mode, "ffirst BO only possible when Rc=1"
629 mode |= (failfirst << SVP64MODE.BO_LSB) # set BO
630
631 ######################################
632 # "saturation" modes
633 elif sv_mode == 0b10:
634 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
635 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
636 mode |= (saturation << SVP64MODE.N) # signed/unsigned saturation
637
638 ######################################
639 # "predicate-result" modes. err... code-duplication from ffirst
640 elif sv_mode == 0b11:
641 assert src_zero == 0, "dest-zero not allowed in predresult mode"
642 if predresult == 'RC1':
643 mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
644 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
645 assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
646 elif predresult == '~RC1':
647 mode |= (0b1<<SVP64MODE.RC1) # sets RC1 mode
648 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
649 mode |= (0b1<<SVP64MODE.INV) # ... with inversion
650 assert rc_mode==False, "pr-mode RC1 only possible when Rc=0"
651 else:
652 assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
653 assert rc_mode, "pr-mode BO only possible when Rc=1"
654 mode |= (predresult << SVP64MODE.BO_LSB) # set BO
655
656 # whewww.... modes all done :)
657 # now put into svp64_rm
658 mode |= sv_mode
659 # mode: bits 19-23
660 svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
661
662 # put in predicate masks into svp64_rm
663 if ptype == '2P':
664 # source pred: bits 16-18
665 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
666 # mask mode: bit 0
667 svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
668 # 1-pred: bits 1-3
669 svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
670
671 # and subvl: bits 8-9
672 svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
673
674 # put in elwidths
675 # srcwid: bits 6-7
676 svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
677 # destwid: bits 4-5
678 svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
679
680 # nice debug printout. (and now for something completely different)
681 # https://youtu.be/u0WOIwlXE9g?t=146
682 svp64_rm_value = svp64_rm.spr.value
683 log ("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
684 log (" mmode 0 :", bin(mmode))
685 log (" pmask 1-3 :", bin(pmask))
686 log (" dstwid 4-5 :", bin(destwid))
687 log (" srcwid 6-7 :", bin(srcwid))
688 log (" subvl 8-9 :", bin(subvl))
689 log (" mode 19-23:", bin(mode))
690 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
691 for idx, sv_extra in extras.items():
692 if idx is None: continue
693 srcdest, idx, duplicate = idx
694 start = (10+idx*offs)
695 end = start + offs-1
696 log (" extra%d %2d-%2d:" % (idx, start, end),
697 bin(sv_extra))
698 if ptype == '2P':
699 log (" smask 16-17:", bin(smask))
700 log ()
701
702 # first, construct the prefix from its subfields
703 svp64_prefix = SVP64PrefixFields()
704 svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
705 svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
706 svp64_prefix.rm.eq(svp64_rm.spr)
707
708 # fiinally yield the svp64 prefix and the thingy. v3.0b opcode
709 rc = '.' if rc_mode else ''
710 yield ".long 0x%x" % svp64_prefix.insn.value
711 yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
712 log ("new v3.0B fields", v30b_op, v30b_newfields)
713
714 def translate(self, lst):
715 for insn in lst:
716 yield from self.translate_one(insn)
717
718
719 def asm_process():
720
721 # get an input file and an output file
722 args = sys.argv[1:]
723 if len(args) == 0:
724 infile = sys.stdin
725 outfile = sys.stdout
726 # read the whole lot in advance in case of in-place
727 lines = list(infile.readlines())
728 elif len(args) != 2:
729 print ("pysvp64asm [infile | -] [outfile | -]")
730 exit(0)
731 else:
732 if args[0] == '--':
733 infile = sys.stdin
734 else:
735 infile = open(args[0], "r")
736 # read the whole lot in advance in case of in-place overwrite
737 lines = list(infile.readlines())
738
739 if args[1] == '--':
740 outfile = sys.stdout
741 else:
742 outfile = open(args[1], "w")
743
744 # read the line, look for "sv", process it
745 isa = SVP64Asm([])
746 for line in lines:
747 ls = line.split("#")
748 if len(ls) != 2:
749 outfile.write(line)
750 continue
751 potential= ls[1].strip()
752 if not potential.startswith("sv."):
753 outfile.write(line)
754 continue
755 # find whitespace
756 ws = ''
757 while line:
758 if not line[0].isspace():
759 break
760 ws += line[0]
761 line = line[1:]
762
763 # SV line indentified
764 lst = list(isa.translate_one(potential))
765 lst = '; '.join(lst)
766 outfile.write("%s%s # %s\n" % (ws, lst, potential))
767
768
769 if __name__ == '__main__':
770 lst = ['slw 3, 1, 4',
771 'extsw 5, 3',
772 'sv.extsw 5, 3',
773 'sv.cmpi 5, 1, 3, 2',
774 'sv.setb 5, 31',
775 'sv.isel 64.v, 3, 2, 65.v',
776 'sv.setb/dm=r3/sm=1<<r3 5, 31',
777 'sv.setb/m=r3 5, 31',
778 'sv.setb/vec2 5, 31',
779 'sv.setb/sw=8/ew=16 5, 31',
780 'sv.extsw./ff=eq 5, 31',
781 'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
782 'sv.extsw./pr=eq 5.v, 31',
783 'sv.add. 5.v, 2.v, 1.v',
784 'sv.add./m=r3 5.v, 2.v, 1.v',
785 ]
786 lst += [
787 'sv.stw 5.v, 4(1.v)',
788 'sv.ld 5.v, 4(1.v)',
789 'setvl. 2, 3, 4, 1, 1',
790 ]
791 lst = [
792 "sv.stfsu 0.v, 16(4.v)",
793 ]
794 lst = [
795 "sv.stfsu/els 0.v, 16(4)",
796 ]
797 isa = SVP64Asm(lst)
798 print ("list", list(isa))
799 csvs = SVP64RM()
800 #asm_process()