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[openpower-isa.git] / src / openpower / sv / trans / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 """SVP64 OpenPOWER v3.0B assembly translator
6
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and creates
8 an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode.
9
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
12
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Encoding format of arithmetic: https://libre-soc.org/openpower/sv/normal/
15 Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/
16 **TODO format of branches: https://libre-soc.org/openpower/sv/branches/**
17 **TODO format of CRs: https://libre-soc.org/openpower/sv/cr_ops/**
18 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
19 """
20
21 import os
22 import sys
23 from collections import OrderedDict
24
25 from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
26 SV64P_PID_SIZE, SVP64RMFields,
27 SVP64RM_EXTRA2_SPEC_SIZE,
28 SVP64RM_EXTRA3_SPEC_SIZE,
29 SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
30 SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
31 SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
32 SVP64RM_ELWIDTH_SIZE)
33 from openpower.decoder.pseudo.pagereader import ISA
34 from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
35 from openpower.decoder.selectable_int import SelectableInt
36 from openpower.consts import SVP64MODE
37
38 # for debug logging
39 from openpower.util import log
40
41
42 # decode GPR into sv extra
43 def get_extra_gpr(etype, regmode, field):
44 if regmode == 'scalar':
45 # cut into 2-bits 5-bits SS FFFFF
46 sv_extra = field >> 5
47 field = field & 0b11111
48 else:
49 # cut into 5-bits 2-bits FFFFF SS
50 sv_extra = field & 0b11
51 field = field >> 2
52 return sv_extra, field
53
54
55 # decode 3-bit CR into sv extra
56 def get_extra_cr_3bit(etype, regmode, field):
57 if regmode == 'scalar':
58 # cut into 2-bits 3-bits SS FFF
59 sv_extra = field >> 3
60 field = field & 0b111
61 else:
62 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
63 sv_extra = field & 0b1111
64 field = field >> 4
65 return sv_extra, field
66
67
68 # decodes SUBVL
69 def decode_subvl(encoding):
70 pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
71 assert encoding in pmap, \
72 "encoding %s for SUBVL not recognised" % encoding
73 return pmap[encoding]
74
75
76 # decodes elwidth
77 def decode_elwidth(encoding):
78 pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
79 assert encoding in pmap, \
80 "encoding %s for elwidth not recognised" % encoding
81 return pmap[encoding]
82
83
84 # decodes predicate register encoding
85 def decode_predicate(encoding):
86 pmap = { # integer
87 '1<<r3': (0, 0b001),
88 'r3': (0, 0b010),
89 '~r3': (0, 0b011),
90 'r10': (0, 0b100),
91 '~r10': (0, 0b101),
92 'r30': (0, 0b110),
93 '~r30': (0, 0b111),
94 # CR
95 'lt': (1, 0b000),
96 'nl': (1, 0b001), 'ge': (1, 0b001), # same value
97 'gt': (1, 0b010),
98 'ng': (1, 0b011), 'le': (1, 0b011), # same value
99 'eq': (1, 0b100),
100 'ne': (1, 0b101),
101 'so': (1, 0b110), 'un': (1, 0b110), # same value
102 'ns': (1, 0b111), 'nu': (1, 0b111), # same value
103 }
104 assert encoding in pmap, \
105 "encoding %s for predicate not recognised" % encoding
106 return pmap[encoding]
107
108
109 # decodes "Mode" in similar way to BO field (supposed to, anyway)
110 def decode_bo(encoding):
111 pmap = { # TODO: double-check that these are the same as Branch BO
112 'lt': 0b000,
113 'nl': 0b001, 'ge': 0b001, # same value
114 'gt': 0b010,
115 'ng': 0b011, 'le': 0b011, # same value
116 'eq': 0b100,
117 'ne': 0b101,
118 'so': 0b110, 'un': 0b110, # same value
119 'ns': 0b111, 'nu': 0b111, # same value
120 }
121 assert encoding in pmap, \
122 "encoding %s for BO Mode not recognised" % encoding
123 return pmap[encoding]
124
125 # partial-decode fail-first mode
126
127
128 def decode_ffirst(encoding):
129 if encoding in ['RC1', '~RC1']:
130 return encoding
131 return decode_bo(encoding)
132
133
134 def decode_reg(field):
135 # decode the field number. "5.v" or "3.s" or "9"
136 field = field.split(".")
137 regmode = 'scalar' # default
138 if len(field) == 2:
139 if field[1] == 's':
140 regmode = 'scalar'
141 elif field[1] == 'v':
142 regmode = 'vector'
143 field = int(field[0]) # actual register number
144 return field, regmode
145
146
147 def decode_imm(field):
148 ldst_imm = "(" in field and field[-1] == ')'
149 if ldst_imm:
150 return field[:-1].split("(")
151 else:
152 return None, field
153
154
155 def crf_extra(etype, regmode, field, extras):
156 """takes a CR Field number (CR0-CR127), splits into EXTRA2/3 and v3.0
157 the scalar/vector mode (crNN.v or crNN.s) changes both the format
158 of the EXTRA2/3 encoding as well as what range of registers is possible.
159 this function can be used for both BF/BFA and BA/BB/BT by first removing
160 the bottom 2 bits of BA/BB/BT then re-instating them after encoding.
161 see https://libre-soc.org/openpower/sv/svp64/appendix/#cr_extra
162 for specification
163 """
164 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
165 # now sanity-check (and shrink afterwards)
166 if etype == 'EXTRA2':
167 # 3-bit CR Field (BF, BFA) EXTRA2 encoding
168 if regmode == 'scalar':
169 # range is CR0-CR15 in increments of 1
170 assert (sv_extra >> 1) == 0, \
171 "scalar CR %s cannot fit into EXTRA2 %s" % \
172 (rname, str(extras[extra_idx]))
173 # all good: encode as scalar
174 sv_extra = sv_extra & 0b01
175 else: # vector
176 # range is CR0-CR127 in increments of 16
177 assert sv_extra & 0b111 == 0, \
178 "vector CR %s cannot fit into EXTRA2 %s" % \
179 (rname, str(extras[extra_idx]))
180 # all good: encode as vector (bit 2 set)
181 sv_extra = 0b10 | (sv_extra >> 3)
182 else:
183 # 3-bit CR Field (BF, BFA) EXTRA3 encoding
184 if regmode == 'scalar':
185 # range is CR0-CR31 in increments of 1
186 assert (sv_extra >> 2) == 0, \
187 "scalar CR %s cannot fit into EXTRA3 %s" % \
188 (rname, str(extras[extra_idx]))
189 # all good: encode as scalar
190 sv_extra = sv_extra & 0b11
191 else: # vector
192 # range is CR0-CR127 in increments of 8
193 assert sv_extra & 0b11 == 0, \
194 "vector CR %s cannot fit into EXTRA3 %s" % \
195 (rname, str(extras[extra_idx]))
196 # all good: encode as vector (bit 3 set)
197 sv_extra = 0b100 | (sv_extra >> 2)
198 return sv_extra, field
199
200
201 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
202 class SVP64Asm:
203 def __init__(self, lst, bigendian=False, macros=None):
204 if macros is None:
205 macros = {}
206 self.macros = macros
207 self.lst = lst
208 self.trans = self.translate(lst)
209 self.isa = ISA() # reads the v3.0B pseudo-code markdown files
210 self.svp64 = SVP64RM() # reads the svp64 Remap entries for registers
211 assert bigendian == False, "error, bigendian not supported yet"
212
213 def __iter__(self):
214 yield from self.trans
215
216 def translate_one(self, insn, macros=None):
217 if macros is None:
218 macros = {}
219 macros.update(self.macros)
220 isa = self.isa
221 svp64 = self.svp64
222 # find first space, to get opcode
223 ls = insn.split(' ')
224 opcode = ls[0]
225 # now find opcode fields
226 fields = ''.join(ls[1:]).split(',')
227 mfields = list(map(str.strip, fields))
228 log("opcode, fields", ls, opcode, mfields)
229 fields = []
230 # macro substitution
231 for field in mfields:
232 fields.append(macro_subst(macros, field))
233 log("opcode, fields substed", ls, opcode, fields)
234
235 # this is a *32-bit-only* instruction. it controls SVSTATE.
236 # it is *not* a 64-bit-prefixed Vector instruction (no sv.setvl),
237 # it is a Vector *control* instruction.
238 # note: EXT022 is the "sandbox" major opcode so it's fine to add
239
240 # sigh have to do setvl here manually for now...
241 # note the subtract one from SVi.
242 if opcode in ["setvl", "setvl."]:
243 # 1.6.28 SVL-FORM - from fields.txt
244 # |0 |6 |11 |16 |23 |24 |25 |26 |31 |
245 # | PO | RT | RA | SVi |ms |vs |vf | XO |Rc |
246 insn = 22 << (31-5) # opcode 22, bits 0-5
247 fields = list(map(int, fields))
248 insn |= fields[0] << (31-10) # RT , bits 6-10
249 insn |= fields[1] << (31-15) # RA , bits 11-15
250 insn |= (fields[2]-1) << (31-22) # SVi , bits 16-22
251 insn |= fields[3] << (31-25) # vf , bit 25
252 insn |= fields[4] << (31-24) # vs , bit 24
253 insn |= fields[5] << (31-23) # ms , bit 23
254 insn |= 0b11011 << (31-30) # XO , bits 26..30
255 if opcode == 'setvl.':
256 insn |= 1 << (31-31) # Rc=1 , bit 31
257 log("setvl", bin(insn))
258 yield ".long 0x%x" % insn
259 return
260
261 # this is a 32-bit instruction. it updates SVSTATE.
262 # it *can* be SVP64-prefixed, to indicate that its registers
263 # are Vectorised.
264 # note: EXT022 is the "sandbox" major opcode so it's fine to add
265
266 # sigh have to do setvl here manually for now...
267 # note the subtract one from SVi.
268 if opcode in ["svstep", "svstep."]:
269 # 1.6.28 SVL-FORM - from fields.txt
270 # |0 |6 |11 |16 |23 |24 |25 |26 |31 |
271 # | PO | RT | RA | SVi |ms |vs |vf | XO |Rc |
272 insn = 22 << (31-5) # opcode 22, bits 0-5
273 fields = list(map(int, fields))
274 insn |= fields[0] << (31-10) # RT , bits 6-10
275 insn |= (fields[1]-1) << (31-22) # SVi , bits 16-22
276 insn |= fields[2] << (31-25) # vf , bit 25
277 insn |= 0b10011 << (31-30) # XO , bits 26..30
278 if opcode == 'svstep.':
279 insn |= 1 << (31-31) # Rc=1 , bit 31
280 log("svstep", bin(insn))
281 yield ".long 0x%x" % insn
282 return
283
284 # this is a *32-bit-only* instruction. it updates SVSHAPE and SVSTATE.
285 # it is *not* a 64-bit-prefixed Vector instruction (no sv.svshape),
286 # it is a Vector *control* instruction.
287 # note: EXT022 is the "sandbox" major opcode so it's fine to add
288
289 # and svshape. note that the dimension fields one subtracted from each
290 if opcode == 'svshape':
291 # 1.6.33 SVM-FORM from fields.txt
292 # |0 |6 |11 |16 |21 |25 |26 |31 |
293 # |PO | SVxd | SVyd | SVzd | SVRM |vf | XO | / |
294 insn = 22 << (31-5) # opcode 22, bits 0-5
295 fields = list(map(int, fields))
296 insn |= (fields[0]-1) << (31-10) # SVxd , bits 6-10
297 insn |= (fields[1]-1) << (31-15) # SVyd , bits 11-15
298 insn |= (fields[2]-1) << (31-20) # SVzd , bits 16-20
299 insn |= (fields[3]) << (31-24) # SVRM , bits 21-24
300 insn |= (fields[4]) << (31-25) # vf , bits 25
301 insn |= 0b011001 << (31-31) # XO , bits 26..31
302 #insn &= ((1<<32)-1)
303 log("svshape", bin(insn))
304 yield ".long 0x%x" % insn
305 return
306
307 # this is a *32-bit-only* instruction. it updates the SVSHAPE SPR
308 # it is *not* a 64-bit-prefixed Vector instruction (no sv.svremap),
309 # it is a Vector *control* instruction.
310 # note: EXT022 is the "sandbox" major opcode so it's fine to add
311
312 # and svremap
313 if opcode == 'svremap':
314 # 1.6.34 SVRM-FORM from fields.txt
315 # |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 |
316 # |PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO | / |
317 insn = 22 << (31-5) # opcode 22, bits 0-5
318 fields = list(map(int, fields))
319 insn |= fields[0] << (31-10) # SVme , bits 6-10
320 insn |= fields[1] << (31-12) # mi0 , bits 11-12
321 insn |= fields[2] << (31-14) # mi1 , bits 13-14
322 insn |= fields[3] << (31-16) # mi2 , bits 15-16
323 insn |= fields[4] << (31-18) # m00 , bits 17-18
324 insn |= fields[5] << (31-20) # m01 , bits 19-20
325 insn |= fields[6] << (31-21) # pst , bit 21
326 insn |= 0b111001 << (31-31) # XO , bits 26..31
327 log("svremap", bin(insn))
328 yield ".long 0x%x" % insn
329 return
330
331 # ok from here-on down these are added as 32-bit instructions
332 # and are here only because binutils (at present) doesn't have
333 # them (that's being fixed!)
334 # they can - if implementations then choose - be Vectorised
335 # (sv.fsins) because they are general-purpose scalar instructions
336
337 # and fsins
338 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
339 # however we are out of space with opcode 22
340 if opcode.startswith('fsins'):
341 fields = list(map(int, fields))
342 insn = 59 << (31-5) # opcode 59, bits 0-5
343 insn |= fields[0] << (31-10) # RT , bits 6-10
344 insn |= fields[1] << (31-20) # RB , bits 16-20
345 insn |= 0b1000001110 << (31-30) # XO , bits 21..30
346 if opcode == 'fsins.':
347 insn |= 1 << (31-31) # Rc=1 , bit 31
348 log("fsins", bin(insn))
349 yield ".long 0x%x" % insn
350 return
351
352 # and fcoss
353 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
354 # however we are out of space with opcode 22
355 if opcode.startswith('fcoss'):
356 fields = list(map(int, fields))
357 insn = 59 << (31-5) # opcode 59, bits 0-5
358 insn |= fields[0] << (31-10) # RT , bits 6-10
359 insn |= fields[1] << (31-20) # RB , bits 16-20
360 insn |= 0b1000101110 << (31-30) # XO , bits 21..30
361 if opcode == 'fcoss.':
362 insn |= 1 << (31-31) # Rc=1 , bit 31
363 log("fcoss", bin(insn))
364 yield ".long 0x%x" % insn
365 return
366
367 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
368 # however we are out of space with opcode 22
369 if opcode in ('ternlogi', 'ternlogi.'):
370 po = 5
371 xo = 0
372 rt = int(fields[0])
373 ra = int(fields[1])
374 rb = int(fields[2])
375 imm = int(fields[3])
376 rc = '.' in opcode
377 instr = po
378 instr = (instr << 5) | rt
379 instr = (instr << 5) | ra
380 instr = (instr << 5) | rb
381 instr = (instr << 8) | imm
382 instr = (instr << 2) | xo
383 instr = (instr << 1) | rc
384 asm = f"{opcode} {rt}, {ra}, {rb}, {imm}"
385 yield f".4byte {hex(instr)} # {asm}"
386 return
387
388 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
389 # however we are out of space with opcode 22
390 if opcode in ('grev', 'grevi', 'grevw', 'grevwi',
391 'grev.', 'grevi.', 'grevw.', 'grevwi.'):
392 po = 5
393 # _ matches fields in table at:
394 # https://libre-soc.org/openpower/sv/bitmanip/
395 xo = 0b1_0010_110
396 if 'w' in opcode:
397 xo |= 0b100_000
398 if 'i' in opcode:
399 xo |= 0b1000_000
400 Rc = 1 if '.' in opcode else 0
401 rt = int(fields[0])
402 ra = int(fields[1])
403 rb_imm = int(fields[2])
404 instr = po
405 instr = (instr << 5) | rt
406 instr = (instr << 5) | ra
407 if opcode == 'grevi' or opcode == 'grevi.':
408 assert 0 <= rb_imm < 64
409 instr = (instr << 6) | rb_imm
410 instr = (instr << 9) | xo
411 else:
412 assert 0 <= rb_imm < 32
413 instr = (instr << 5) | rb_imm
414 instr = (instr << 10) | xo
415 instr = (instr << 1) | Rc
416 asm = f"{opcode} {rt}, {ra}, {rb_imm}"
417 yield f".4byte {hex(instr)} # {asm}"
418 return
419
420 # and min/max
421 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
422 # 1.6.7 X-FORM
423 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
424 # | PO | RT | RA | RB | XO |Rc |
425 if opcode in ['mins', 'maxs', 'minu', 'maxu',
426 'mins.', 'maxs.', 'minu.', 'maxu.']:
427 if opcode[:4] == 'maxs':
428 XO = 0b0111001110
429 if opcode[:4] == 'maxu':
430 XO = 0b0011001110
431 if opcode[:4] == 'mins':
432 XO = 0b0101001110
433 if opcode[:4] == 'minu':
434 XO = 0b0001001110
435 fields = list(map(int, fields))
436 insn = 22 << (31-5) # opcode 22, bits 0-5
437 insn |= fields[0] << (31-10) # RT , bits 6-10
438 insn |= fields[1] << (31-15) # RA , bits 11-15
439 insn |= fields[2] << (31-20) # RB , bits 16-20
440 insn |= XO << (31-30) # XO , bits 21..30
441 if opcode.endswith('.'):
442 insn |= 1 << (31-31) # Rc=1 , bit 31
443 log("maxs", bin(insn))
444 yield ".long 0x%x" % insn
445 return
446
447 # and avgadd, absdu, absdacu, absdacs
448 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
449 # 1.6.7 X-FORM
450 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
451 # | PO | RT | RA | RB | XO |Rc |
452 if opcode in ['avgadd', 'absdu', 'absds', 'absdacu', 'absdacs',
453 'cprop']:
454 if opcode[:5] == 'absdu':
455 XO = 0b1011110110
456 elif opcode[:5] == 'absds':
457 XO = 0b1001110110
458 elif opcode[:6] == 'avgadd':
459 XO = 0b1101001110
460 elif opcode[:7] == 'absdacu':
461 XO = 0b1111110110
462 elif opcode[:7] == 'absdacs':
463 XO = 0b0111110110
464 elif opcode[:7] == 'cprop':
465 XO = 0b0110001110
466 fields = list(map(int, fields))
467 insn = 22 << (31-5) # opcode 22, bits 0-5
468 insn |= fields[0] << (31-10) # RT , bits 6-10
469 insn |= fields[1] << (31-15) # RA , bits 11-15
470 insn |= fields[2] << (31-20) # RB , bits 16-20
471 insn |= XO << (31-30) # XO , bits 21..30
472 if opcode.endswith('.'):
473 insn |= 1 << (31-31) # Rc=1 , bit 31
474 log(opcode, bin(insn))
475 yield ".long 0x%x" % insn
476 return
477
478 # identify if is a svp64 mnemonic
479 if not opcode.startswith('sv.'):
480 yield insn # unaltered
481 return
482 opcode = opcode[3:] # strip leading "sv"
483
484 # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
485 opmodes = opcode.split("/") # split at "/"
486 v30b_op = opmodes.pop(0) # first is the v3.0B
487 # check instruction ends with dot
488 rc_mode = v30b_op.endswith('.')
489 if rc_mode:
490 v30b_op = v30b_op[:-1]
491
492 # sigh again, have to recognised LD/ST bit-reverse instructions
493 # this has to be "processed" to fit into a v3.0B without the "sh"
494 # e.g. ldsh is actually ld
495 ldst_shift = v30b_op.startswith("l") and v30b_op.endswith("sh")
496
497 if v30b_op not in isa.instr:
498 raise Exception("opcode %s of '%s' not supported" %
499 (v30b_op, insn))
500
501 if ldst_shift:
502 # okaay we need to process the fields and make this:
503 # ldsh RT, SVD(RA), RC - 11 bits for SVD, 5 for RC
504 # into this:
505 # ld RT, D(RA) - 16 bits
506 # likewise same for SVDS (9 bits for SVDS, 5 for RC, 14 bits for DS)
507 form = isa.instr[v30b_op].form # get form (SVD-Form, SVDS-Form)
508
509 newfields = []
510 for field in fields:
511 # identify if this is a ld/st immediate(reg) thing
512 ldst_imm = "(" in field and field[-1] == ')'
513 if ldst_imm:
514 newfields.append(field[:-1].split("("))
515 else:
516 newfields.append(field)
517
518 immed, RA = newfields[1]
519 immed = int(immed)
520 RC = int(newfields.pop(2)) # better be an integer number!
521 if form == 'SVD': # 16 bit: immed 11 bits, RC shift up 11
522 immed = (immed & 0b11111111111) | (RC << 11)
523 if immed & (1 << 15): # should be negative
524 immed -= 1 << 16
525 if form == 'SVDS': # 14 bit: immed 9 bits, RC shift up 9
526 immed = (immed & 0b111111111) | (RC << 9)
527 if immed & (1 << 13): # should be negative
528 immed -= 1 << 14
529 newfields[1] = "%d(%s)" % (immed, RA)
530 fields = newfields
531
532 # and strip off "sh" from end, and add "sh" to opmodes, instead
533 v30b_op = v30b_op[:-2]
534 opmodes.append("sh")
535 log("rewritten", v30b_op, opmodes, fields)
536
537 if v30b_op not in svp64.instrs:
538 raise Exception("opcode %s of '%s' not an svp64 instruction" %
539 (v30b_op, insn))
540 v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
541 rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV
542 log("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
543 log("v3.0B regs", opcode, v30b_regs)
544 log("RM", rm)
545
546 # right. the first thing to do is identify the ordering of
547 # the registers, by name. the EXTRA2/3 ordering is in
548 # rm['0']..rm['3'] but those fields contain the names RA, BB
549 # etc. we have to read the pseudocode to understand which
550 # reg is which in our instruction. sigh.
551
552 # first turn the svp64 rm into a "by name" dict, recording
553 # which position in the RM EXTRA it goes into
554 # also: record if the src or dest was a CR, for sanity-checking
555 # (elwidth overrides on CRs are banned)
556 decode = decode_extra(rm)
557 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
558
559 log("EXTRA field index, src", svp64_src)
560 log("EXTRA field index, dest", svp64_dest)
561
562 # okaaay now we identify the field value (opcode N,N,N) with
563 # the pseudo-code info (opcode RT, RA, RB)
564 assert len(fields) == len(v30b_regs), \
565 "length of fields %s must match insn `%s` fields %s" % \
566 (str(v30b_regs), insn, str(fields))
567 opregfields = zip(fields, v30b_regs) # err that was easy
568
569 # now for each of those find its place in the EXTRA encoding
570 # note there is the possibility (for LD/ST-with-update) of
571 # RA occurring **TWICE**. to avoid it getting added to the
572 # v3.0B suffix twice, we spot it as a duplicate, here
573 extras = OrderedDict()
574 for idx, (field, regname) in enumerate(opregfields):
575 imm, regname = decode_imm(regname)
576 rtype = get_regtype(regname)
577 log(" idx find", rtype, idx, field, regname, imm)
578 if rtype is None:
579 # probably an immediate field, append it straight
580 extras[('imm', idx, False)] = (idx, field, None, None, None)
581 continue
582 extra = svp64_src.get(regname, None)
583 if extra is not None:
584 extra = ('s', extra, False) # not a duplicate
585 extras[extra] = (idx, field, regname, rtype, imm)
586 log(" idx src", idx, extra, extras[extra])
587 dextra = svp64_dest.get(regname, None)
588 log("regname in", regname, dextra)
589 if dextra is not None:
590 is_a_duplicate = extra is not None # duplicate spotted
591 dextra = ('d', dextra, is_a_duplicate)
592 extras[dextra] = (idx, field, regname, rtype, imm)
593 log(" idx dst", idx, extra, extras[dextra])
594
595 # great! got the extra fields in their associated positions:
596 # also we know the register type. now to create the EXTRA encodings
597 etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
598 ptype = rm['Ptype'] # Predication type: Twin / Single
599 extra_bits = 0
600 v30b_newfields = []
601 for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
602 # is it a field we don't alter/examine? if so just put it
603 # into newfields
604 if rtype is None:
605 v30b_newfields.append(field)
606 continue
607
608 # identify if this is a ld/st immediate(reg) thing
609 ldst_imm = "(" in field and field[-1] == ')'
610 if ldst_imm:
611 immed, field = field[:-1].split("(")
612
613 field, regmode = decode_reg(field)
614 log(" ", extra_idx, rname, rtype,
615 regmode, iname, field, end=" ")
616
617 # see Mode field https://libre-soc.org/openpower/sv/svp64/
618 # XXX TODO: the following is a bit of a laborious repeated
619 # mess, which could (and should) easily be parameterised.
620 # XXX also TODO: the LD/ST modes which are different
621 # https://libre-soc.org/openpower/sv/ldst/
622
623 # rright. SVP64 register numbering is from 0 to 127
624 # for GPRs, FPRs *and* CR Fields, where for v3.0 the GPRs and RPFs
625 # are 0-31 and CR Fields are only 0-7. the SVP64 RM "Extra"
626 # area is used to extend the numbering from the 32-bit
627 # instruction, and also to record whether the register
628 # is scalar or vector. on a per-operand basis. this
629 # results in a slightly finnicky encoding: here we go...
630
631 # encode SV-GPR and SV-FPR field into extra, v3.0field
632 if rtype in ['GPR', 'FPR']:
633 sv_extra, field = get_extra_gpr(etype, regmode, field)
634 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
635 # (and shrink to a single bit if ok)
636 if etype == 'EXTRA2':
637 if regmode == 'scalar':
638 # range is r0-r63 in increments of 1
639 assert (sv_extra >> 1) == 0, \
640 "scalar GPR %s cannot fit into EXTRA2 %s" % \
641 (rname, str(extras[extra_idx]))
642 # all good: encode as scalar
643 sv_extra = sv_extra & 0b01
644 else:
645 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
646 assert sv_extra & 0b01 == 0, \
647 "%s: vector field %s cannot fit " \
648 "into EXTRA2 %s" % \
649 (insn, rname, str(extras[extra_idx]))
650 # all good: encode as vector (bit 2 set)
651 sv_extra = 0b10 | (sv_extra >> 1)
652 elif regmode == 'vector':
653 # EXTRA3 vector bit needs marking
654 sv_extra |= 0b100
655
656 # encode SV-CR 3-bit field into extra, v3.0field.
657 # 3-bit is for things like BF and BFA
658 elif rtype == 'CR_3bit':
659 sv_extra, field = crf_extra(etype, regmode, field, extras)
660
661 # encode SV-CR 5-bit field into extra, v3.0field
662 # 5-bit is for things like BA BB BC BT etc.
663 # *sigh* this is the same as 3-bit except the 2 LSBs of the
664 # 5-bit field are passed through unaltered.
665 elif rtype == 'CR_5bit':
666 cr_subfield = field & 0b11 # record bottom 2 bits for later
667 field = field >> 2 # strip bottom 2 bits
668 # use the exact same 3-bit function for the top 3 bits
669 sv_extra, field = crf_extra(etype, regmode, field, extras)
670 # reconstruct the actual 5-bit CR field (preserving the
671 # bottom 2 bits, unaltered)
672 field = (field << 2) | cr_subfield
673
674 else:
675 raise Exception("no type match: %s" % rtype)
676
677 # capture the extra field info
678 log("=>", "%5s" % bin(sv_extra), field)
679 extras[extra_idx] = sv_extra
680
681 # append altered field value to v3.0b, differs for LDST
682 # note that duplicates are skipped e.g. EXTRA2 contains
683 # *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
684 srcdest, idx, duplicate = extra_idx
685 if duplicate: # skip adding to v3.0b fields, already added
686 continue
687 if ldst_imm:
688 v30b_newfields.append(("%s(%s)" % (immed, str(field))))
689 else:
690 v30b_newfields.append(str(field))
691
692 log("new v3.0B fields", v30b_op, v30b_newfields)
693 log("extras", extras)
694
695 # rright. now we have all the info. start creating SVP64 RM
696 svp64_rm = SVP64RMFields()
697
698 # begin with EXTRA fields
699 for idx, sv_extra in extras.items():
700 log(idx)
701 if idx is None:
702 continue
703 if idx[0] == 'imm':
704 continue
705 srcdest, idx, duplicate = idx
706 if etype == 'EXTRA2':
707 svp64_rm.extra2[idx].eq(
708 SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
709 else:
710 svp64_rm.extra3[idx].eq(
711 SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
712
713 # identify if the op is a LD/ST. the "blegh" way. copied
714 # from power_enums. TODO, split the list _insns down.
715 is_ld = v30b_op in [
716 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
717 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
718 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
719 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load dbl
720 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
721 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
722 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
723 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
724 ]
725 is_st = v30b_op in [
726 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
727 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
728 "stfs", "stfsx", "stfsu", "stfux", # FP store sgl
729 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store dbl
730 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
731 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
732 ]
733 # use this to determine if the SVP64 RM format is different.
734 # see https://libre-soc.org/openpower/sv/ldst/
735 is_ldst = is_ld or is_st
736
737 # branch-conditional detection
738 is_bc = v30b_op in [
739 "bc", "bclr",
740 ]
741
742 # parts of svp64_rm
743 mmode = 0 # bit 0
744 pmask = 0 # bits 1-3
745 destwid = 0 # bits 4-5
746 srcwid = 0 # bits 6-7
747 subvl = 0 # bits 8-9
748 smask = 0 # bits 16-18 but only for twin-predication
749 mode = 0 # bits 19-23
750
751 mask_m_specified = False
752 has_pmask = False
753 has_smask = False
754
755 saturation = None
756 src_zero = 0
757 dst_zero = 0
758 sv_mode = None
759
760 mapreduce = False
761 reverse_gear = False
762 mapreduce_crm = False
763 mapreduce_svm = False
764
765 predresult = False
766 failfirst = False
767 ldst_elstride = 0
768
769 # branch-conditional bits
770 bc_all = 0
771 bc_lru = 0
772 bc_brc = 0
773 bc_svstep = 0
774 bc_vsb = 0
775 bc_vlset = 0
776 bc_vli = 0
777 bc_snz = 0
778
779 # ok let's start identifying opcode augmentation fields
780 for encmode in opmodes:
781 # predicate mask (src and dest)
782 if encmode.startswith("m="):
783 pme = encmode
784 pmmode, pmask = decode_predicate(encmode[2:])
785 smmode, smask = pmmode, pmask
786 mmode = pmmode
787 mask_m_specified = True
788 # predicate mask (dest)
789 elif encmode.startswith("dm="):
790 pme = encmode
791 pmmode, pmask = decode_predicate(encmode[3:])
792 mmode = pmmode
793 has_pmask = True
794 # predicate mask (src, twin-pred)
795 elif encmode.startswith("sm="):
796 sme = encmode
797 smmode, smask = decode_predicate(encmode[3:])
798 mmode = smmode
799 has_smask = True
800 # shifted LD/ST
801 elif encmode.startswith("sh"):
802 ldst_shift = True
803 # vec2/3/4
804 elif encmode.startswith("vec"):
805 subvl = decode_subvl(encmode[3:])
806 # elwidth
807 elif encmode.startswith("ew="):
808 destwid = decode_elwidth(encmode[3:])
809 elif encmode.startswith("sw="):
810 srcwid = decode_elwidth(encmode[3:])
811 # element-strided LD/ST
812 elif encmode == 'els':
813 ldst_elstride = 1
814 # saturation
815 elif encmode == 'sats':
816 assert sv_mode is None
817 saturation = 1
818 sv_mode = 0b10
819 elif encmode == 'satu':
820 assert sv_mode is None
821 sv_mode = 0b10
822 saturation = 0
823 # predicate zeroing
824 elif encmode == 'sz':
825 src_zero = 1
826 elif encmode == 'dz':
827 dst_zero = 1
828 # failfirst
829 elif encmode.startswith("ff="):
830 assert sv_mode is None
831 sv_mode = 0b01
832 failfirst = decode_ffirst(encmode[3:])
833 # predicate-result, interestingly same as fail-first
834 elif encmode.startswith("pr="):
835 assert sv_mode is None
836 sv_mode = 0b11
837 predresult = decode_ffirst(encmode[3:])
838 # map-reduce mode, reverse-gear
839 elif encmode == 'mrr':
840 assert sv_mode is None
841 sv_mode = 0b00
842 mapreduce = True
843 reverse_gear = True
844 # map-reduce mode
845 elif encmode == 'mr':
846 assert sv_mode is None
847 sv_mode = 0b00
848 mapreduce = True
849 elif encmode == 'crm': # CR on map-reduce
850 assert sv_mode is None
851 sv_mode = 0b00
852 mapreduce_crm = True
853 elif encmode == 'svm': # sub-vector mode
854 mapreduce_svm = True
855 elif is_bc:
856 if encmode == 'all':
857 bc_all = 1
858 elif encmode == 'st': # svstep mode
859 bc_step = 1
860 elif encmode == 'sr': # svstep BRc mode
861 bc_step = 1
862 bc_brc = 1
863 elif encmode == 'vs': # VLSET mode
864 bc_vlset = 1
865 elif encmode == 'vsi': # VLSET mode with VLI (VL inclusives)
866 bc_vlset = 1
867 bc_vli = 1
868 elif encmode == 'vsb': # VLSET mode with VSb
869 bc_vlset = 1
870 bc_vsb = 1
871 elif encmode == 'vsbi': # VLSET mode with VLI and VSb
872 bc_vlset = 1
873 bc_vli = 1
874 bc_vsb = 1
875 elif encmode == 'snz': # sz (only) already set above
876 src_zero = 1
877 bc_snz = 1
878 elif encmode == 'lu': # LR update mode
879 bc_lru = 1
880 else:
881 raise AssertionError("unknown encmode %s" % encmode)
882 else:
883 raise AssertionError("unknown encmode %s" % encmode)
884
885 if ptype == '2P':
886 # since m=xx takes precedence (overrides) sm=xx and dm=xx,
887 # treat them as mutually exclusive
888 if mask_m_specified:
889 assert not has_smask,\
890 "cannot have both source-mask and predicate mask"
891 assert not has_pmask,\
892 "cannot have both dest-mask and predicate mask"
893 # since the default is INT predication (ALWAYS), if you
894 # specify one CR mask, you must specify both, to avoid
895 # mixing INT and CR reg types
896 if has_pmask and pmmode == 1:
897 assert has_smask, \
898 "need explicit source-mask in CR twin predication"
899 if has_smask and smmode == 1:
900 assert has_pmask, \
901 "need explicit dest-mask in CR twin predication"
902 # sanity-check that 2Pred mask is same mode
903 if has_pmask and has_smask:
904 assert smmode == pmmode, \
905 "predicate masks %s and %s must be same reg type" % \
906 (pme, sme)
907
908 # sanity-check that twin-predication mask only specified in 2P mode
909 if ptype == '1P':
910 assert not has_smask, \
911 "source-mask can only be specified on Twin-predicate ops"
912 assert not has_pmask, \
913 "dest-mask can only be specified on Twin-predicate ops"
914
915 # construct the mode field, doing sanity-checking along the way
916 if mapreduce_svm:
917 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
918 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
919
920 if src_zero:
921 assert has_smask or mask_m_specified, \
922 "src zeroing requires a source predicate"
923 if dst_zero:
924 assert has_pmask or mask_m_specified, \
925 "dest zeroing requires a dest predicate"
926
927 # check LDST shifted, only available in "normal" mode
928 if is_ldst and ldst_shift:
929 assert sv_mode is None, \
930 "LD shift cannot have modes (%s) applied" % sv_mode
931
932 # okaaay, so there are 4 different modes, here, which will be
933 # partly-merged-in: is_ldst is merged in with "normal", but
934 # is_bc is so different it's done separately. likewise is_cr
935 # (when it is done). here are the maps:
936
937 # for "normal" arithmetic: https://libre-soc.org/openpower/sv/normal/
938 """
939 | 0-1 | 2 | 3 4 | description |
940 | --- | --- |---------|-------------------------- |
941 | 00 | 0 | dz sz | normal mode |
942 | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 |
943 | 00 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 |
944 | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 |
945 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
946 | 01 | inv | VLi RC1 | Rc=0: ffirst z/nonz |
947 | 10 | N | dz sz | sat mode: N=0/1 u/s |
948 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
949 | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
950 """
951
952 # https://libre-soc.org/openpower/sv/ldst/
953 # for LD/ST-immediate:
954 """
955 | 0-1 | 2 | 3 4 | description |
956 | --- | --- |---------|--------------------------- |
957 | 00 | 0 | dz els | normal mode |
958 | 00 | 1 | dz shf | shift mode |
959 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
960 | 01 | inv | els RC1 | Rc=0: ffirst z/nonz |
961 | 10 | N | dz els | sat mode: N=0/1 u/s |
962 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
963 | 11 | inv | els RC1 | Rc=0: pred-result z/nonz |
964 """
965
966 # for LD/ST-indexed (RA+RB):
967 """
968 | 0-1 | 2 | 3 4 | description |
969 | --- | --- |---------|-------------------------- |
970 | 00 | SEA | dz sz | normal mode |
971 | 01 | SEA | dz sz | Strided (scalar only source) |
972 | 10 | N | dz sz | sat mode: N=0/1 u/s |
973 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
974 | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
975 """
976
977 # and leaving out branches and cr_ops for now because they're
978 # under development
979 """ TODO branches and cr_ops
980 """
981
982 # now create mode and (overridden) src/dst widths
983 # XXX TODO: sanity-check bc modes
984 if is_bc:
985 sv_mode = ((bc_svstep << SVP64MODE.MOD2_MSB) |
986 (bc_vlset << SVP64MODE.MOD2_LSB) |
987 (bc_snz << SVP64MODE.BC_SNZ))
988 srcwid = (bc_vsb << 1) | bc_lru
989 destwid = (bc_lru << 1) | bc_all
990
991 else:
992
993 ######################################
994 # "normal" mode
995 if sv_mode is None:
996 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
997 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
998 if is_ldst:
999 # TODO: for now, LD/ST-indexed is ignored.
1000 mode |= ldst_elstride << SVP64MODE.ELS_NORMAL # el-strided
1001 # shifted mode
1002 if ldst_shift:
1003 mode |= 1 << SVP64MODE.LDST_SHIFT
1004 else:
1005 # TODO, reduce and subvector mode
1006 # 00 1 dz CRM reduce mode (mapreduce), SUBVL=1
1007 # 00 1 SVM CRM subvector reduce mode, SUBVL>1
1008 pass
1009 sv_mode = 0b00
1010
1011 ######################################
1012 # "mapreduce" modes
1013 elif sv_mode == 0b00:
1014 mode |= (0b1 << SVP64MODE.REDUCE) # sets mapreduce
1015 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
1016 if reverse_gear:
1017 mode |= (0b1 << SVP64MODE.RG) # sets Reverse-gear mode
1018 if mapreduce_crm:
1019 mode |= (0b1 << SVP64MODE.CRM) # sets CRM mode
1020 assert rc_mode, "CRM only allowed when Rc=1"
1021 # bit of weird encoding to jam zero-pred or SVM mode in.
1022 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
1023 if subvl == 0:
1024 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
1025 elif mapreduce_svm:
1026 mode |= (0b1 << SVP64MODE.SVM) # sets SVM mode
1027
1028 ######################################
1029 # "failfirst" modes
1030 elif sv_mode == 0b01:
1031 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
1032 if failfirst == 'RC1':
1033 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1034 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1035 assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1036 elif failfirst == '~RC1':
1037 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1038 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1039 mode |= (0b1 << SVP64MODE.INV) # ... with inversion
1040 assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1041 else:
1042 assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
1043 assert rc_mode, "ffirst BO only possible when Rc=1"
1044 mode |= (failfirst << SVP64MODE.BO_LSB) # set BO
1045
1046 ######################################
1047 # "saturation" modes
1048 elif sv_mode == 0b10:
1049 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
1050 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
1051 mode |= (saturation << SVP64MODE.N) # signed/us saturation
1052
1053 ######################################
1054 # "predicate-result" modes. err... code-duplication from ffirst
1055 elif sv_mode == 0b11:
1056 assert src_zero == 0, "dest-zero not allowed in predresult mode"
1057 if predresult == 'RC1':
1058 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1059 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1060 assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1061 elif predresult == '~RC1':
1062 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1063 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1064 mode |= (0b1 << SVP64MODE.INV) # ... with inversion
1065 assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1066 else:
1067 assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
1068 assert rc_mode, "pr-mode BO only possible when Rc=1"
1069 mode |= (predresult << SVP64MODE.BO_LSB) # set BO
1070
1071 # whewww.... modes all done :)
1072 # now put into svp64_rm
1073 mode |= sv_mode
1074 # mode: bits 19-23
1075 svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
1076
1077 # put in predicate masks into svp64_rm
1078 if ptype == '2P':
1079 # source pred: bits 16-18
1080 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
1081 # mask mode: bit 0
1082 svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
1083 # 1-pred: bits 1-3
1084 svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
1085
1086 # and subvl: bits 8-9
1087 svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
1088
1089 # put in elwidths
1090 # srcwid: bits 6-7
1091 svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
1092 # destwid: bits 4-5
1093 svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
1094
1095 # nice debug printout. (and now for something completely different)
1096 # https://youtu.be/u0WOIwlXE9g?t=146
1097 svp64_rm_value = svp64_rm.spr.value
1098 log("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
1099 log(" mmode 0 :", bin(mmode))
1100 log(" pmask 1-3 :", bin(pmask))
1101 log(" dstwid 4-5 :", bin(destwid))
1102 log(" srcwid 6-7 :", bin(srcwid))
1103 log(" subvl 8-9 :", bin(subvl))
1104 log(" mode 19-23:", bin(mode))
1105 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
1106 for idx, sv_extra in extras.items():
1107 if idx is None:
1108 continue
1109 if idx[0] == 'imm':
1110 continue
1111 srcdest, idx, duplicate = idx
1112 start = (10+idx*offs)
1113 end = start + offs-1
1114 log(" extra%d %2d-%2d:" % (idx, start, end),
1115 bin(sv_extra))
1116 if ptype == '2P':
1117 log(" smask 16-17:", bin(smask))
1118 log()
1119
1120 # first, construct the prefix from its subfields
1121 svp64_prefix = SVP64PrefixFields()
1122 svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
1123 svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
1124 svp64_prefix.rm.eq(svp64_rm.spr)
1125
1126 # fiinally yield the svp64 prefix and the thingy. v3.0b opcode
1127 rc = '.' if rc_mode else ''
1128 yield ".long 0x%08x" % svp64_prefix.insn.value
1129 log(v30b_newfields)
1130 # argh, sv.fmadds etc. need to be done manually
1131 if v30b_op == 'ffmadds':
1132 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1133 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1134 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1135 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1136 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
1137 opcode |= 0b00101 << (32-31) # bits 26-30
1138 if rc:
1139 opcode |= 1 # Rc, bit 31.
1140 yield ".long 0x%x" % opcode
1141 # argh, sv.fdmadds need to be done manually
1142 elif v30b_op == 'fdmadds':
1143 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1144 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1145 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1146 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1147 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
1148 opcode |= 0b01111 << (32-31) # bits 26-30
1149 if rc:
1150 opcode |= 1 # Rc, bit 31.
1151 yield ".long 0x%x" % opcode
1152 # argh, sv.ffadds etc. need to be done manually
1153 elif v30b_op == 'ffadds':
1154 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1155 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1156 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1157 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1158 opcode |= 0b01101 << (32-31) # bits 26-30
1159 if rc:
1160 opcode |= 1 # Rc, bit 31.
1161 yield ".long 0x%x" % opcode
1162 # sigh have to do svstep here manually for now...
1163 elif opcode in ["svstep", "svstep."]:
1164 insn = 22 << (31-5) # opcode 22, bits 0-5
1165 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
1166 insn |= int(v30b_newfields[1]) << (31-22) # SVi , bits 16-22
1167 insn |= int(v30b_newfields[2]) << (31-25) # vf , bit 25
1168 insn |= 0b10011 << (31-30) # XO , bits 26..30
1169 if opcode == 'svstep.':
1170 insn |= 1 << (31-31) # Rc=1 , bit 31
1171 log("svstep", bin(insn))
1172 yield ".long 0x%x" % insn
1173 # argh, sv.fcoss etc. need to be done manually
1174 elif v30b_op in ["fcoss", "fcoss."]:
1175 insn = 59 << (31-5) # opcode 59, bits 0-5
1176 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
1177 insn |= int(v30b_newfields[1]) << (31-20) # RB , bits 16-20
1178 insn |= 0b1000101110 << (31-30) # XO , bits 21..30
1179 if opcode == 'fcoss.':
1180 insn |= 1 << (31-31) # Rc=1 , bit 31
1181 log("fcoss", bin(insn))
1182 yield ".long 0x%x" % insn
1183
1184 else:
1185 yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
1186 log("new v3.0B fields", v30b_op, v30b_newfields)
1187
1188 def translate(self, lst):
1189 for insn in lst:
1190 yield from self.translate_one(insn)
1191
1192
1193 def macro_subst(macros, txt):
1194 again = True
1195 log("subst", txt, macros)
1196 while again:
1197 again = False
1198 for macro, value in macros.items():
1199 if macro == txt:
1200 again = True
1201 replaced = txt.replace(macro, value)
1202 log("macro", txt, "replaced", replaced, macro, value)
1203 txt = replaced
1204 continue
1205 toreplace = '%s.s' % macro
1206 if toreplace == txt:
1207 again = True
1208 replaced = txt.replace(toreplace, "%s.s" % value)
1209 log("macro", txt, "replaced", replaced, toreplace, value)
1210 txt = replaced
1211 continue
1212 toreplace = '%s.v' % macro
1213 if toreplace == txt:
1214 again = True
1215 replaced = txt.replace(toreplace, "%s.v" % value)
1216 log("macro", txt, "replaced", replaced, toreplace, value)
1217 txt = replaced
1218 continue
1219 toreplace = '(%s)' % macro
1220 if toreplace in txt:
1221 again = True
1222 replaced = txt.replace(toreplace, '(%s)' % value)
1223 log("macro", txt, "replaced", replaced, toreplace, value)
1224 txt = replaced
1225 continue
1226 log(" processed", txt)
1227 return txt
1228
1229
1230 def get_ws(line):
1231 # find whitespace
1232 ws = ''
1233 while line:
1234 if not line[0].isspace():
1235 break
1236 ws += line[0]
1237 line = line[1:]
1238 return ws, line
1239
1240
1241 def asm_process():
1242 # get an input file and an output file
1243 args = sys.argv[1:]
1244 if len(args) == 0:
1245 infile = sys.stdin
1246 outfile = sys.stdout
1247 # read the whole lot in advance in case of in-place
1248 lines = list(infile.readlines())
1249 elif len(args) != 2:
1250 print("pysvp64asm [infile | -] [outfile | -]", file=sys.stderr)
1251 exit(0)
1252 else:
1253 if args[0] == '--':
1254 infile = sys.stdin
1255 else:
1256 infile = open(args[0], "r")
1257 # read the whole lot in advance in case of in-place overwrite
1258 lines = list(infile.readlines())
1259
1260 if args[1] == '--':
1261 outfile = sys.stdout
1262 else:
1263 outfile = open(args[1], "w")
1264
1265 # read the line, look for "sv", process it
1266 macros = {} # macros which start ".set"
1267 isa = SVP64Asm([])
1268 for line in lines:
1269 op = line.split("#")[0].strip()
1270 # identify macros
1271 if op.startswith(".set"):
1272 macro = op[4:].split(",")
1273 (macro, value) = map(str.strip, macro)
1274 macros[macro] = value
1275 if not (op.startswith("sv.") or
1276 op.startswith("setvl") or
1277 op.startswith("svshape")):
1278 outfile.write(line)
1279 continue
1280
1281 (ws, line) = get_ws(line)
1282 lst = isa.translate_one(op, macros)
1283 lst = '; '.join(lst)
1284 outfile.write("%s%s # %s\n" % (ws, lst, op))
1285
1286
1287 if __name__ == '__main__':
1288 lst = ['slw 3, 1, 4',
1289 'extsw 5, 3',
1290 'sv.extsw 5, 3',
1291 'sv.cmpi 5, 1, 3, 2',
1292 'sv.setb 5, 31',
1293 'sv.isel 64.v, 3, 2, 65.v',
1294 'sv.setb/dm=r3/sm=1<<r3 5, 31',
1295 'sv.setb/m=r3 5, 31',
1296 'sv.setb/vec2 5, 31',
1297 'sv.setb/sw=8/ew=16 5, 31',
1298 'sv.extsw./ff=eq 5, 31',
1299 'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
1300 'sv.extsw./pr=eq 5.v, 31',
1301 'sv.add. 5.v, 2.v, 1.v',
1302 'sv.add./m=r3 5.v, 2.v, 1.v',
1303 ]
1304 lst += [
1305 'sv.stw 5.v, 4(1.v)',
1306 'sv.ld 5.v, 4(1.v)',
1307 'setvl. 2, 3, 4, 0, 1, 1',
1308 'sv.setvl. 2, 3, 4, 0, 1, 1',
1309 ]
1310 lst = [
1311 "sv.stfsu 0.v, 16(4.v)",
1312 ]
1313 lst = [
1314 "sv.stfsu/els 0.v, 16(4)",
1315 ]
1316 lst = [
1317 'sv.add./mr 5.v, 2.v, 1.v',
1318 ]
1319 macros = {'win2': '50', 'win': '60'}
1320 lst = [
1321 'sv.addi win2.v, win.v, -1',
1322 'sv.add./mrr 5.v, 2.v, 1.v',
1323 #'sv.lhzsh 5.v, 11(9.v), 15',
1324 #'sv.lwzsh 5.v, 11(9.v), 15',
1325 'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
1326 ]
1327 lst = [
1328 #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
1329 #'sv.ffadds 0.v, 8.v, 4.v',
1330 'svremap 11, 0, 1, 2, 3, 2, 1',
1331 'svshape 8, 1, 1, 1, 0',
1332 'svshape 8, 1, 1, 1, 1',
1333 ]
1334 lst = [
1335 #'sv.lfssh 4.v, 11(8.v), 15',
1336 #'sv.lwzsh 4.v, 11(8.v), 15',
1337 #'sv.svstep. 2.v, 4, 0',
1338 #'sv.fcfids. 48.v, 64.v',
1339 'sv.fcoss. 80.v, 0.v',
1340 'sv.fcoss. 20.v, 0.v',
1341 ]
1342 lst = [
1343 'sv.bc/all 3,12,192',
1344 'sv.bclr/vsbi 3,81.v,192',
1345 'sv.ld 5.v, 4(1.v)',
1346 'sv.svstep. 2.v, 4, 0',
1347 ]
1348 lst = [
1349 'maxs 3,12,5',
1350 'maxs. 3,12,5',
1351 'avgadd 3,12,5',
1352 'absdu 3,12,5',
1353 'absds 3,12,5',
1354 'absdacu 3,12,5',
1355 'absdacs 3,12,5',
1356 'cprop 3,12,5',
1357 ]
1358 isa = SVP64Asm(lst, macros=macros)
1359 log("list", list(isa))
1360 asm_process()