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[openpower-isa.git] / src / openpower / sv / trans / svp64.py
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
4
5 """SVP64 OpenPOWER v3.0B assembly translator
6
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and creates
8 an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode.
9
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
12
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Encoding format of arithmetic: https://libre-soc.org/openpower/sv/normal/
15 Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/
16 **TODO format of branches: https://libre-soc.org/openpower/sv/branches/**
17 **TODO format of CRs: https://libre-soc.org/openpower/sv/cr_ops/**
18 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
19 """
20
21 import functools
22 import os
23 import sys
24 from collections import OrderedDict
25
26 from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
27 SV64P_PID_SIZE, SVP64RMFields,
28 SVP64RM_EXTRA2_SPEC_SIZE,
29 SVP64RM_EXTRA3_SPEC_SIZE,
30 SVP64RM_MODE_SIZE,
31 SVP64RM_SMASK_SIZE,
32 SVP64RM_MMODE_SIZE,
33 SVP64RM_MASK_SIZE,
34 SVP64RM_SUBVL_SIZE,
35 SVP64RM_EWSRC_SIZE,
36 SVP64RM_ELWIDTH_SIZE)
37 from openpower.decoder.pseudo.pagereader import ISA
38 from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
39 from openpower.decoder.selectable_int import SelectableInt
40 from openpower.consts import SVP64MODE
41
42 # for debug logging
43 from openpower.util import log
44
45
46 def instruction(*fields):
47 def instruction(insn, desc):
48 (value, start, end) = desc
49 bits = ((1,) * ((end + 1) - start))
50 mask = 0
51 for bit in bits:
52 mask = ((mask << 1) | bit)
53 return (insn | ((value & mask) << (31 - end)))
54
55 return functools.reduce(instruction, fields, 0)
56
57
58 def setvl(fields, Rc):
59 """
60 setvl is a *32-bit-only* instruction. It controls SVSTATE.
61 It is *not* a 64-bit-prefixed Vector instruction (no sv.setvl, yet),
62 it is a Vector *control* instruction.
63
64 * setvl RT,RA,SVi,vf,vs,ms
65
66 1.6.28 SVL-FORM - from fields.txt
67 |0 |6 |11 |16 |23 |24 |25 |26 |31 |
68 | PO | RT | RA | SVi |ms |vs |vf | XO |Rc |
69 """
70 PO = 22
71 XO = 0b11011
72 # ARRRGH these are in a non-obvious order in openpower/isa/simplev.mdwn
73 # compared to the SVL-Form above. sigh
74 # setvl RT,RA,SVi,vf,vs,ms
75 (RT, RA, SVi, vf, vs, ms) = fields
76 SVi -= 1
77 return instruction(
78 (PO , 0 , 5 ),
79 (RT , 6 , 10),
80 (RA , 11, 15),
81 (SVi, 16, 22),
82 (ms , 23, 23),
83 (vs , 24, 24),
84 (vf , 25, 25),
85 (XO , 26, 30),
86 (Rc , 31, 31),
87 )
88
89
90 def svstep(fields, Rc):
91 """
92 svstep is a 32-bit instruction. It updates SVSTATE.
93 It *can* be SVP64-prefixed, to indicate that its registers
94 are Vectorised.
95
96 * svstep RT,SVi,vf
97
98 # 1.6.28 SVL-FORM - from fields.txt
99 # |0 |6 |11 |16 |23 |24 |25 |26 |31 |
100 # | PO | RT | / | SVi |/ |/ |vf | XO |Rc |
101
102 """
103 PO = 22
104 XO = 0b10011
105 (RT, SVi, vf) = fields
106 SVi -= 1
107 return instruction(
108 (PO , 0 , 5 ),
109 (RT , 6 , 10),
110 (0 , 11, 15),
111 (SVi, 16, 22),
112 (0 , 23, 23),
113 (0 , 24, 24),
114 (vf , 25, 25),
115 (XO , 26, 30),
116 (Rc , 31, 31),
117 )
118
119
120 def svshape(fields):
121 """
122 svshape is a *32-bit-only* instruction. It updates SVSHAPE and SVSTATE.
123 It is *not* a 64-bit-prefixed Vector instruction (no sv.svshape, yet),
124 it is a Vector *control* instruction.
125
126 * svshape SVxd,SVyd,SVzd,SVrm,vf
127
128 # 1.6.33 SVM-FORM from fields.txt
129 # |0 |6 |11 |16 |21 |25 |26 |31 |
130 # | PO | SVxd | SVyd | SVzd | SVrm |vf | XO |
131
132 """
133 PO = 22
134 XO = 0b011001
135 (SVxd, SVyd, SVzd, SVrm, vf) = fields
136 SVxd -= 1
137 SVyd -= 1
138 SVzd -= 1
139 return instruction(
140 (PO , 0 , 5 ),
141 (SVxd, 6 , 10),
142 (SVyd, 11, 15),
143 (SVzd, 16, 20),
144 (SVrm, 21, 24),
145 (vf , 25, 25),
146 (XO , 26, 31),
147 )
148
149
150 def svindex(fields):
151 """
152 svindex is a *32-bit-only* instruction. It is a convenience
153 instruction that reduces instruction count for Indexed REMAP
154 Mode.
155 It is *not* a 64-bit-prefixed Vector instruction (no sv.svindex, yet),
156 it is a Vector *control* instruction.
157
158 1.6.28 SVI-FORM
159 |0 |6 |11 |16 |21 |23|24|25|26 31|
160 | PO | SVG|rmm | SVd |ew |yx|mm|sk| XO |
161 """
162 # note that the dimension field one subtracted
163 PO = 22
164 XO = 0b101001
165 (SVG, rmm, SVd, ew, yx, mm, sk) = fields
166 SVd -= 1
167 return instruction(
168 (PO , 0 , 5 ),
169 (SVG, 6 , 10),
170 (rmm, 11, 15),
171 (SVd, 16, 20),
172 (ew , 21, 22),
173 (yx , 23, 23),
174 (mm , 24, 24),
175 (sk , 25, 25),
176 (XO , 26, 31),
177 )
178
179
180 def svremap(fields):
181 """
182 this is a *32-bit-only* instruction. It updates the SVSHAPE SPR
183 it is *not* a 64-bit-prefixed Vector instruction (no sv.svremap),
184 it is a Vector *control* instruction.
185
186 * svremap SVme,mi0,mi1,mi2,mo0,mo1,pst
187
188 # 1.6.34 SVRM-FORM
189 |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 |
190 | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO |
191
192 """
193 PO = 22
194 XO = 0b111001
195 (SVme, mi0, mi1, mi2, mo0, mo1, pst) = fields
196 return instruction(
197 (PO , 0 , 5 ),
198 (SVme, 6 , 10),
199 (mi0 , 11, 12),
200 (mi1 , 13, 14),
201 (mi2 , 15, 16),
202 (mo0 , 17, 18),
203 (mo1 , 19, 20),
204 (pst , 21, 21),
205 (0 , 22, 25),
206 (XO , 26, 31),
207 )
208
209
210 # ok from here-on down these are added as 32-bit instructions
211 # and are here only because binutils (at present) doesn't have
212 # them (that's being fixed!)
213 # they can - if implementations then choose - be Vectorised
214 # because they are general-purpose scalar instructions
215 def bmask(fields):
216 """
217 1.6.2.2 BM2-FORM
218 |0 |6 |11 |16 |21 |26 |27 31|
219 | PO | RT | RA | RB |bm |L | XO |
220 """
221 PO = 22
222 XO = 0b010001
223 (RT, RA, RB, bm, L) = fields
224 return instruction(
225 (PO, 0 , 5 ),
226 (RT, 6 , 10),
227 (RA, 11, 15),
228 (RB, 16, 20),
229 (bm, 21, 25),
230 (L , 26, 26),
231 (XO, 27, 31),
232 )
233
234
235 def fsins(fields, Rc):
236 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
237 # however we are out of space with opcode 22
238 # 1.6.7 X-FORM
239 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
240 # | PO | FRT | /// | FRB | XO |Rc |
241 PO = 59
242 XO = 0b1000001110
243 (FRT, FRB) = fields
244 return instruction(
245 (PO , 0 , 5 ),
246 (FRT, 6 , 10),
247 (0 , 11, 15),
248 (FRB, 16, 20),
249 (XO , 21, 30),
250 (Rc , 31, 31),
251 )
252
253
254 def fcoss(fields, Rc):
255 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
256 # however we are out of space with opcode 22
257 # 1.6.7 X-FORM
258 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
259 # | PO | FRT | /// | FRB | XO |Rc |
260 PO = 59
261 XO = 0b1000101110
262 (FRT, FRB) = fields
263 return instruction(
264 (PO , 0 , 5 ),
265 (FRT, 6 , 10),
266 (0 , 11, 15),
267 (FRB, 16, 20),
268 (XO , 21, 30),
269 (Rc , 31, 31),
270 )
271
272
273 def ternlogi(fields, Rc):
274 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
275 # however we are out of space with opcode 22
276 # 1.6.34 TLI-FORM
277 # |0 |6 |11 |16 |21 |29 |31 |
278 # | PO | RT | RA | RB | TLI | XO |Rc |
279 PO = 5
280 XO = 0
281 (RT, RA, RB, TLI) = fields
282 return instruction(
283 (PO , 0 , 5 ),
284 (RT , 6 , 10),
285 (RA , 11, 15),
286 (RB , 16, 20),
287 (TLI, 21, 28),
288 (XO , 29, 30),
289 (Rc , 31, 31),
290 )
291
292
293 def grev(fields, Rc, imm, wide):
294 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
295 # however we are out of space with opcode 22
296 insn = PO = 5
297 # _ matches fields in table at:
298 # https://libre-soc.org/openPOwer/sv/bitmanip/
299 XO = 0b1_0010_110
300 if wide:
301 XO |= 0b100_000
302 if imm:
303 XO |= 0b1000_000
304 (RT, RA, XBI) = fields
305 insn = (insn << 5) | RT
306 insn = (insn << 5) | RA
307 if imm and not wide:
308 assert 0 <= XBI < 64
309 insn = (insn << 6) | XBI
310 insn = (insn << 9) | XO
311 else:
312 assert 0 <= XBI < 32
313 insn = (insn << 5) | XBI
314 insn = (insn << 10) | XO
315 insn = (insn << 1) | Rc
316 return insn
317
318
319 def av(fields, XO, Rc):
320 # 1.6.7 X-FORM
321 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
322 # | PO | RT | RA | RB | XO |Rc |
323 PO = 22
324 (RT, RA, RB) = fields
325 return instruction(
326 (PO, 0 , 5 ),
327 (RT, 6 , 10),
328 (RA, 11, 15),
329 (RB, 16, 20),
330 (XO, 21, 30),
331 (Rc, 31, 31),
332 )
333
334
335 def fmvis(fields):
336 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
337 # V3.0B 1.6.6 DX-FORM
338 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |26|27 |31 |
339 # | PO | FRS | d1 | d0 | XO |d2 |
340 PO = 22
341 XO = 0b00011
342 (FRS, imm) = fields
343 # first split imm into d1, d0 and d2. sigh
344 d2 = (imm & 1) # LSB (0)
345 d1 = (imm >> 1) & 0b11111 # bits 1-5
346 d0 = (imm >> 5) # MSBs 6-15
347 return instruction(
348 (PO , 0 , 5),
349 (FRS, 6 , 10),
350 (d1, 11, 15),
351 (d0, 16, 26),
352 (XO , 27, 30),
353 (d2 , 31, 31),
354 )
355
356
357 def fishmv(fields):
358 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
359 # V3.0B 1.6.6 DX-FORM
360 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |26|27 |31 |
361 # | PO | FRS | d1 | d0 | XO |d2 |
362 PO = 22
363 XO = 0b01011
364 (FRS, imm) = fields
365 # first split imm into d1, d0 and d2. sigh
366 d2 = (imm & 1) # LSB (0)
367 d1 = (imm >> 1) & 0b11111 # bits 1-5
368 d0 = (imm >> 5) # MSBs 6-15
369 print("imm", hex(imm))
370 print("d0 d1 d2", hex(d0), hex(d1), hex(d2))
371 return instruction(
372 (PO , 0 , 5),
373 (FRS, 6 , 10),
374 (d1, 11, 15),
375 (d0, 16, 26),
376 (XO , 27, 30),
377 (d2 , 31, 31),
378 )
379
380
381 CUSTOM_INSNS = {}
382 for (name, hook) in (
383 ("setvl", setvl),
384 ("svstep", svstep),
385 ("fsins", fsins),
386 ("fcoss", fcoss),
387 ("ternlogi", ternlogi),
388 ):
389 CUSTOM_INSNS[name] = functools.partial(hook, Rc=False)
390 CUSTOM_INSNS[f"{name}."] = functools.partial(hook, Rc=True)
391 CUSTOM_INSNS["bmask"] = bmask
392 CUSTOM_INSNS["svshape"] = svshape
393 CUSTOM_INSNS["svindex"] = svindex
394 CUSTOM_INSNS["svremap"] = svremap
395 CUSTOM_INSNS["fmvis"] = fmvis
396 CUSTOM_INSNS["fishmv"] = fishmv
397
398 for (name, imm, wide) in (
399 ("grev", False, False),
400 ("grevi", True, False),
401 ("grevw", False, True),
402 ("grevwi", True, True),
403 ):
404 CUSTOM_INSNS[name] = functools.partial(grev,
405 imm=("i" in name), wide=("w" in name), Rc=False)
406 CUSTOM_INSNS[f"{name}."] = functools.partial(grev,
407 imm=("i" in name), wide=("w" in name), Rc=True)
408
409 for (name, XO) in (
410 ("maxs" , 0b0111001110),
411 ("maxu" , 0b0011001110),
412 ("minu" , 0b0001001110),
413 ("mins" , 0b0101001110),
414 ("absdu" , 0b1011110110),
415 ("absds" , 0b1001110110),
416 ("avgadd" , 0b1101001110),
417 ("absdacu", 0b1111110110),
418 ("absdacs", 0b0111110110),
419 ("cprop" , 0b0110001110),
420 ):
421 CUSTOM_INSNS[name] = functools.partial(av, XO=XO, Rc=False)
422 CUSTOM_INSNS[f"{name}."] = functools.partial(av, XO=XO, Rc=True)
423
424
425 # decode GPR into sv extra
426 def get_extra_gpr(etype, regmode, field):
427 if regmode == 'scalar':
428 # cut into 2-bits 5-bits SS FFFFF
429 sv_extra = field >> 5
430 field = field & 0b11111
431 else:
432 # cut into 5-bits 2-bits FFFFF SS
433 sv_extra = field & 0b11
434 field = field >> 2
435 return sv_extra, field
436
437
438 # decode 3-bit CR into sv extra
439 def get_extra_cr_3bit(etype, regmode, field):
440 if regmode == 'scalar':
441 # cut into 2-bits 3-bits SS FFF
442 sv_extra = field >> 3
443 field = field & 0b111
444 else:
445 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
446 sv_extra = field & 0b1111
447 field = field >> 4
448 return sv_extra, field
449
450
451 # decodes SUBVL
452 def decode_subvl(encoding):
453 pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
454 assert encoding in pmap, \
455 "encoding %s for SUBVL not recognised" % encoding
456 return pmap[encoding]
457
458
459 # decodes elwidth
460 def decode_elwidth(encoding):
461 pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
462 assert encoding in pmap, \
463 "encoding %s for elwidth not recognised" % encoding
464 return pmap[encoding]
465
466
467 # decodes predicate register encoding
468 def decode_predicate(encoding):
469 pmap = { # integer
470 '1<<r3': (0, 0b001),
471 'r3': (0, 0b010),
472 '~r3': (0, 0b011),
473 'r10': (0, 0b100),
474 '~r10': (0, 0b101),
475 'r30': (0, 0b110),
476 '~r30': (0, 0b111),
477 # CR
478 'lt': (1, 0b000),
479 'nl': (1, 0b001), 'ge': (1, 0b001), # same value
480 'gt': (1, 0b010),
481 'ng': (1, 0b011), 'le': (1, 0b011), # same value
482 'eq': (1, 0b100),
483 'ne': (1, 0b101),
484 'so': (1, 0b110), 'un': (1, 0b110), # same value
485 'ns': (1, 0b111), 'nu': (1, 0b111), # same value
486 }
487 assert encoding in pmap, \
488 "encoding %s for predicate not recognised" % encoding
489 return pmap[encoding]
490
491
492 # decodes "Mode" in similar way to BO field (supposed to, anyway)
493 def decode_bo(encoding):
494 pmap = { # TODO: double-check that these are the same as Branch BO
495 'lt': 0b000,
496 'nl': 0b001, 'ge': 0b001, # same value
497 'gt': 0b010,
498 'ng': 0b011, 'le': 0b011, # same value
499 'eq': 0b100,
500 'ne': 0b101,
501 'so': 0b110, 'un': 0b110, # same value
502 'ns': 0b111, 'nu': 0b111, # same value
503 }
504 assert encoding in pmap, \
505 "encoding %s for BO Mode not recognised" % encoding
506 return pmap[encoding]
507
508 # partial-decode fail-first mode
509
510
511 def decode_ffirst(encoding):
512 if encoding in ['RC1', '~RC1']:
513 return encoding
514 return decode_bo(encoding)
515
516
517 def decode_reg(field, macros=None):
518 if macros is None:
519 macros = {}
520 # decode the field number. "5.v" or "3.s" or "9"
521 # and now also "*0", and "*%0". note: *NOT* to add "*%rNNN" etc.
522 # https://bugs.libre-soc.org/show_bug.cgi?id=884#c0
523 if field.startswith(("*%", "*")):
524 if field.startswith("*%"):
525 field = field[2:]
526 else:
527 field = field[1:]
528 while field in macros:
529 field = macros[field]
530 return int(field), "vector" # actual register number
531
532 # try old convention (to be retired)
533 field = field.split(".")
534 regmode = 'scalar' # default
535 if len(field) == 2:
536 if field[1] == 's':
537 regmode = 'scalar'
538 elif field[1] == 'v':
539 regmode = 'vector'
540 field = int(field[0]) # actual register number
541 return field, regmode
542
543
544 def decode_imm(field):
545 ldst_imm = "(" in field and field[-1] == ')'
546 if ldst_imm:
547 return field[:-1].split("(")
548 else:
549 return None, field
550
551
552 def crf_extra(etype, regmode, field, extras):
553 """takes a CR Field number (CR0-CR127), splits into EXTRA2/3 and v3.0
554 the scalar/vector mode (crNN.v or crNN.s) changes both the format
555 of the EXTRA2/3 encoding as well as what range of registers is possible.
556 this function can be used for both BF/BFA and BA/BB/BT by first removing
557 the bottom 2 bits of BA/BB/BT then re-instating them after encoding.
558 see https://libre-soc.org/openpower/sv/svp64/appendix/#cr_extra
559 for specification
560 """
561 sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
562 # now sanity-check (and shrink afterwards)
563 if etype == 'EXTRA2':
564 # 3-bit CR Field (BF, BFA) EXTRA2 encoding
565 if regmode == 'scalar':
566 # range is CR0-CR15 in increments of 1
567 assert (sv_extra >> 1) == 0, \
568 "scalar CR %s cannot fit into EXTRA2 %s" % \
569 (rname, str(extras[extra_idx]))
570 # all good: encode as scalar
571 sv_extra = sv_extra & 0b01
572 else: # vector
573 # range is CR0-CR127 in increments of 16
574 assert sv_extra & 0b111 == 0, \
575 "vector CR %s cannot fit into EXTRA2 %s" % \
576 (rname, str(extras[extra_idx]))
577 # all good: encode as vector (bit 2 set)
578 sv_extra = 0b10 | (sv_extra >> 3)
579 else:
580 # 3-bit CR Field (BF, BFA) EXTRA3 encoding
581 if regmode == 'scalar':
582 # range is CR0-CR31 in increments of 1
583 assert (sv_extra >> 2) == 0, \
584 "scalar CR %s cannot fit into EXTRA3 %s" % \
585 (rname, str(extras[extra_idx]))
586 # all good: encode as scalar
587 sv_extra = sv_extra & 0b11
588 else: # vector
589 # range is CR0-CR127 in increments of 8
590 assert sv_extra & 0b11 == 0, \
591 "vector CR %s cannot fit into EXTRA3 %s" % \
592 (rname, str(extras[extra_idx]))
593 # all good: encode as vector (bit 3 set)
594 sv_extra = 0b100 | (sv_extra >> 2)
595 return sv_extra, field
596
597
598 def to_number(field):
599 if field.startswith("0x"):
600 return eval(field)
601 if field.startswith("0b"):
602 return eval(field)
603 return int(field)
604
605
606 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
607 class SVP64Asm:
608 def __init__(self, lst, bigendian=False, macros=None):
609 if macros is None:
610 macros = {}
611 self.macros = macros
612 self.lst = lst
613 self.trans = self.translate(lst)
614 self.isa = ISA() # reads the v3.0B pseudo-code markdown files
615 self.svp64 = SVP64RM() # reads the svp64 Remap entries for registers
616 assert bigendian == False, "error, bigendian not supported yet"
617
618 def __iter__(self):
619 yield from self.trans
620
621 def translate_one(self, insn, macros=None):
622 if macros is None:
623 macros = {}
624 macros.update(self.macros)
625 isa = self.isa
626 svp64 = self.svp64
627 # find first space, to get opcode
628 ls = insn.split(' ')
629 opcode = ls[0]
630 # now find opcode fields
631 fields = ''.join(ls[1:]).split(',')
632 mfields = list(map(str.strip, fields))
633 log("opcode, fields", ls, opcode, mfields)
634 fields = []
635 # macro substitution
636 for field in mfields:
637 fields.append(macro_subst(macros, field))
638 log("opcode, fields substed", ls, opcode, fields)
639
640 # identify if it is a special instruction
641 custom_insn_hook = CUSTOM_INSNS.get(opcode)
642 if custom_insn_hook is not None:
643 fields = tuple(map(to_number, fields))
644 insn = custom_insn_hook(fields)
645 log(opcode, bin(insn))
646 yield ".long 0x%x" % insn
647 return
648
649 # identify if is a svp64 mnemonic
650 if not opcode.startswith('sv.'):
651 yield insn # unaltered
652 return
653 opcode = opcode[3:] # strip leading "sv"
654
655 # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
656 opmodes = opcode.split("/") # split at "/"
657 v30b_op = opmodes.pop(0) # first is the v3.0B
658 # check instruction ends with dot
659 rc_mode = v30b_op.endswith('.')
660 if rc_mode:
661 v30b_op = v30b_op[:-1]
662
663 # sigh again, have to recognised LD/ST bit-reverse instructions
664 # this has to be "processed" to fit into a v3.0B without the "sh"
665 # e.g. ldsh is actually ld
666 ldst_shift = v30b_op.startswith("l") and v30b_op.endswith("sh")
667
668 if v30b_op not in isa.instr:
669 raise Exception("opcode %s of '%s' not supported" %
670 (v30b_op, insn))
671
672 if ldst_shift:
673 # okaay we need to process the fields and make this:
674 # ldsh RT, SVD(RA), RC - 11 bits for SVD, 5 for RC
675 # into this:
676 # ld RT, D(RA) - 16 bits
677 # likewise same for SVDS (9 bits for SVDS, 5 for RC, 14 bits for DS)
678 form = isa.instr[v30b_op].form # get form (SVD-Form, SVDS-Form)
679
680 newfields = []
681 for field in fields:
682 # identify if this is a ld/st immediate(reg) thing
683 ldst_imm = "(" in field and field[-1] == ')'
684 if ldst_imm:
685 newfields.append(field[:-1].split("("))
686 else:
687 newfields.append(field)
688
689 immed, RA = newfields[1]
690 immed = int(immed)
691 RC = int(newfields.pop(2)) # better be an integer number!
692 if form == 'SVD': # 16 bit: immed 11 bits, RC shift up 11
693 immed = (immed & 0b11111111111) | (RC << 11)
694 if immed & (1 << 15): # should be negative
695 immed -= 1 << 16
696 if form == 'SVDS': # 14 bit: immed 9 bits, RC shift up 9
697 immed = (immed & 0b111111111) | (RC << 9)
698 if immed & (1 << 13): # should be negative
699 immed -= 1 << 14
700 newfields[1] = "%d(%s)" % (immed, RA)
701 fields = newfields
702
703 # and strip off "sh" from end, and add "sh" to opmodes, instead
704 v30b_op = v30b_op[:-2]
705 opmodes.append("sh")
706 log("rewritten", v30b_op, opmodes, fields)
707
708 if v30b_op not in svp64.instrs:
709 raise Exception("opcode %s of '%s' not an svp64 instruction" %
710 (v30b_op, insn))
711 v30b_regs = isa.instr[v30b_op].regs[0] # get regs info "RT, RA, RB"
712 rm = svp64.instrs[v30b_op] # one row of the svp64 RM CSV
713 log("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
714 log("v3.0B regs", opcode, v30b_regs)
715 log("RM", rm)
716
717 # right. the first thing to do is identify the ordering of
718 # the registers, by name. the EXTRA2/3 ordering is in
719 # rm['0']..rm['3'] but those fields contain the names RA, BB
720 # etc. we have to read the pseudocode to understand which
721 # reg is which in our instruction. sigh.
722
723 # first turn the svp64 rm into a "by name" dict, recording
724 # which position in the RM EXTRA it goes into
725 # also: record if the src or dest was a CR, for sanity-checking
726 # (elwidth overrides on CRs are banned)
727 decode = decode_extra(rm)
728 dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
729
730 log("EXTRA field index, src", svp64_src)
731 log("EXTRA field index, dest", svp64_dest)
732
733 # okaaay now we identify the field value (opcode N,N,N) with
734 # the pseudo-code info (opcode RT, RA, RB)
735 assert len(fields) == len(v30b_regs), \
736 "length of fields %s must match insn `%s` fields %s" % \
737 (str(v30b_regs), insn, str(fields))
738 opregfields = zip(fields, v30b_regs) # err that was easy
739
740 # now for each of those find its place in the EXTRA encoding
741 # note there is the possibility (for LD/ST-with-update) of
742 # RA occurring **TWICE**. to avoid it getting added to the
743 # v3.0B suffix twice, we spot it as a duplicate, here
744 extras = OrderedDict()
745 for idx, (field, regname) in enumerate(opregfields):
746 imm, regname = decode_imm(regname)
747 rtype = get_regtype(regname)
748 log(" idx find", rtype, idx, field, regname, imm)
749 if rtype is None:
750 # probably an immediate field, append it straight
751 extras[('imm', idx, False)] = (idx, field, None, None, None)
752 continue
753 extra = svp64_src.get(regname, None)
754 if extra is not None:
755 extra = ('s', extra, False) # not a duplicate
756 extras[extra] = (idx, field, regname, rtype, imm)
757 log(" idx src", idx, extra, extras[extra])
758 dextra = svp64_dest.get(regname, None)
759 log("regname in", regname, dextra)
760 if dextra is not None:
761 is_a_duplicate = extra is not None # duplicate spotted
762 dextra = ('d', dextra, is_a_duplicate)
763 extras[dextra] = (idx, field, regname, rtype, imm)
764 log(" idx dst", idx, extra, extras[dextra])
765
766 # great! got the extra fields in their associated positions:
767 # also we know the register type. now to create the EXTRA encodings
768 etype = rm['Etype'] # Extra type: EXTRA3/EXTRA2
769 ptype = rm['Ptype'] # Predication type: Twin / Single
770 extra_bits = 0
771 v30b_newfields = []
772 for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
773 # is it a field we don't alter/examine? if so just put it
774 # into newfields
775 if rtype is None:
776 v30b_newfields.append(field)
777 continue
778
779 # identify if this is a ld/st immediate(reg) thing
780 ldst_imm = "(" in field and field[-1] == ')'
781 if ldst_imm:
782 immed, field = field[:-1].split("(")
783
784 field, regmode = decode_reg(field, macros=macros)
785 log(" ", extra_idx, rname, rtype,
786 regmode, iname, field, end=" ")
787
788 # see Mode field https://libre-soc.org/openpower/sv/svp64/
789 # XXX TODO: the following is a bit of a laborious repeated
790 # mess, which could (and should) easily be parameterised.
791 # XXX also TODO: the LD/ST modes which are different
792 # https://libre-soc.org/openpower/sv/ldst/
793
794 # rright. SVP64 register numbering is from 0 to 127
795 # for GPRs, FPRs *and* CR Fields, where for v3.0 the GPRs and RPFs
796 # are 0-31 and CR Fields are only 0-7. the SVP64 RM "Extra"
797 # area is used to extend the numbering from the 32-bit
798 # instruction, and also to record whether the register
799 # is scalar or vector. on a per-operand basis. this
800 # results in a slightly finnicky encoding: here we go...
801
802 # encode SV-GPR and SV-FPR field into extra, v3.0field
803 if rtype in ['GPR', 'FPR']:
804 sv_extra, field = get_extra_gpr(etype, regmode, field)
805 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
806 # (and shrink to a single bit if ok)
807 if etype == 'EXTRA2':
808 if regmode == 'scalar':
809 # range is r0-r63 in increments of 1
810 assert (sv_extra >> 1) == 0, \
811 "scalar GPR %s cannot fit into EXTRA2 %s" % \
812 (rname, str(extras[extra_idx]))
813 # all good: encode as scalar
814 sv_extra = sv_extra & 0b01
815 else:
816 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
817 assert sv_extra & 0b01 == 0, \
818 "%s: vector field %s cannot fit " \
819 "into EXTRA2 %s" % \
820 (insn, rname, str(extras[extra_idx]))
821 # all good: encode as vector (bit 2 set)
822 sv_extra = 0b10 | (sv_extra >> 1)
823 elif regmode == 'vector':
824 # EXTRA3 vector bit needs marking
825 sv_extra |= 0b100
826
827 # encode SV-CR 3-bit field into extra, v3.0field.
828 # 3-bit is for things like BF and BFA
829 elif rtype == 'CR_3bit':
830 sv_extra, field = crf_extra(etype, regmode, field, extras)
831
832 # encode SV-CR 5-bit field into extra, v3.0field
833 # 5-bit is for things like BA BB BC BT etc.
834 # *sigh* this is the same as 3-bit except the 2 LSBs of the
835 # 5-bit field are passed through unaltered.
836 elif rtype == 'CR_5bit':
837 cr_subfield = field & 0b11 # record bottom 2 bits for later
838 field = field >> 2 # strip bottom 2 bits
839 # use the exact same 3-bit function for the top 3 bits
840 sv_extra, field = crf_extra(etype, regmode, field, extras)
841 # reconstruct the actual 5-bit CR field (preserving the
842 # bottom 2 bits, unaltered)
843 field = (field << 2) | cr_subfield
844
845 else:
846 raise Exception("no type match: %s" % rtype)
847
848 # capture the extra field info
849 log("=>", "%5s" % bin(sv_extra), field)
850 extras[extra_idx] = sv_extra
851
852 # append altered field value to v3.0b, differs for LDST
853 # note that duplicates are skipped e.g. EXTRA2 contains
854 # *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
855 srcdest, idx, duplicate = extra_idx
856 if duplicate: # skip adding to v3.0b fields, already added
857 continue
858 if ldst_imm:
859 v30b_newfields.append(("%s(%s)" % (immed, str(field))))
860 else:
861 v30b_newfields.append(str(field))
862
863 log("new v3.0B fields", v30b_op, v30b_newfields)
864 log("extras", extras)
865
866 # rright. now we have all the info. start creating SVP64 RM
867 svp64_rm = SVP64RMFields()
868
869 # begin with EXTRA fields
870 for idx, sv_extra in extras.items():
871 log(idx)
872 if idx is None:
873 continue
874 if idx[0] == 'imm':
875 continue
876 srcdest, idx, duplicate = idx
877 if etype == 'EXTRA2':
878 svp64_rm.extra2[idx].eq(
879 SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
880 else:
881 svp64_rm.extra3[idx].eq(
882 SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
883
884 # identify if the op is a LD/ST. the "blegh" way. copied
885 # from power_enums. TODO, split the list _insns down.
886 is_ld = v30b_op in [
887 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
888 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
889 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
890 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load dbl
891 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
892 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
893 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
894 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
895 ]
896 is_st = v30b_op in [
897 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
898 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
899 "stfs", "stfsx", "stfsu", "stfux", # FP store sgl
900 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store dbl
901 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
902 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
903 ]
904 # use this to determine if the SVP64 RM format is different.
905 # see https://libre-soc.org/openpower/sv/ldst/
906 is_ldst = is_ld or is_st
907
908 # branch-conditional detection
909 is_bc = v30b_op in [
910 "bc", "bclr",
911 ]
912
913 # parts of svp64_rm
914 mmode = 0 # bit 0
915 pmask = 0 # bits 1-3
916 destwid = 0 # bits 4-5
917 srcwid = 0 # bits 6-7
918 subvl = 0 # bits 8-9
919 smask = 0 # bits 16-18 but only for twin-predication
920 mode = 0 # bits 19-23
921
922 mask_m_specified = False
923 has_pmask = False
924 has_smask = False
925
926 saturation = None
927 src_zero = 0
928 dst_zero = 0
929 sv_mode = None
930
931 mapreduce = False
932 reverse_gear = False
933 mapreduce_crm = False
934 mapreduce_svm = False
935
936 predresult = False
937 failfirst = False
938 ldst_elstride = 0
939
940 # branch-conditional bits
941 bc_all = 0
942 bc_lru = 0
943 bc_brc = 0
944 bc_svstep = 0
945 bc_vsb = 0
946 bc_vlset = 0
947 bc_vli = 0
948 bc_snz = 0
949
950 # ok let's start identifying opcode augmentation fields
951 for encmode in opmodes:
952 # predicate mask (src and dest)
953 if encmode.startswith("m="):
954 pme = encmode
955 pmmode, pmask = decode_predicate(encmode[2:])
956 smmode, smask = pmmode, pmask
957 mmode = pmmode
958 mask_m_specified = True
959 # predicate mask (dest)
960 elif encmode.startswith("dm="):
961 pme = encmode
962 pmmode, pmask = decode_predicate(encmode[3:])
963 mmode = pmmode
964 has_pmask = True
965 # predicate mask (src, twin-pred)
966 elif encmode.startswith("sm="):
967 sme = encmode
968 smmode, smask = decode_predicate(encmode[3:])
969 mmode = smmode
970 has_smask = True
971 # shifted LD/ST
972 elif encmode.startswith("sh"):
973 ldst_shift = True
974 # vec2/3/4
975 elif encmode.startswith("vec"):
976 subvl = decode_subvl(encmode[3:])
977 # elwidth
978 elif encmode.startswith("ew="):
979 destwid = decode_elwidth(encmode[3:])
980 elif encmode.startswith("sw="):
981 srcwid = decode_elwidth(encmode[3:])
982 # element-strided LD/ST
983 elif encmode == 'els':
984 ldst_elstride = 1
985 # saturation
986 elif encmode == 'sats':
987 assert sv_mode is None
988 saturation = 1
989 sv_mode = 0b10
990 elif encmode == 'satu':
991 assert sv_mode is None
992 sv_mode = 0b10
993 saturation = 0
994 # predicate zeroing
995 elif encmode == 'sz':
996 src_zero = 1
997 elif encmode == 'dz':
998 dst_zero = 1
999 # failfirst
1000 elif encmode.startswith("ff="):
1001 assert sv_mode is None
1002 sv_mode = 0b01
1003 failfirst = decode_ffirst(encmode[3:])
1004 # predicate-result, interestingly same as fail-first
1005 elif encmode.startswith("pr="):
1006 assert sv_mode is None
1007 sv_mode = 0b11
1008 predresult = decode_ffirst(encmode[3:])
1009 # map-reduce mode, reverse-gear
1010 elif encmode == 'mrr':
1011 assert sv_mode is None
1012 sv_mode = 0b00
1013 mapreduce = True
1014 reverse_gear = True
1015 # map-reduce mode
1016 elif encmode == 'mr':
1017 assert sv_mode is None
1018 sv_mode = 0b00
1019 mapreduce = True
1020 elif encmode == 'crm': # CR on map-reduce
1021 assert sv_mode is None
1022 sv_mode = 0b00
1023 mapreduce_crm = True
1024 elif encmode == 'svm': # sub-vector mode
1025 mapreduce_svm = True
1026 elif is_bc:
1027 if encmode == 'all':
1028 bc_all = 1
1029 elif encmode == 'st': # svstep mode
1030 bc_step = 1
1031 elif encmode == 'sr': # svstep BRc mode
1032 bc_step = 1
1033 bc_brc = 1
1034 elif encmode == 'vs': # VLSET mode
1035 bc_vlset = 1
1036 elif encmode == 'vsi': # VLSET mode with VLI (VL inclusives)
1037 bc_vlset = 1
1038 bc_vli = 1
1039 elif encmode == 'vsb': # VLSET mode with VSb
1040 bc_vlset = 1
1041 bc_vsb = 1
1042 elif encmode == 'vsbi': # VLSET mode with VLI and VSb
1043 bc_vlset = 1
1044 bc_vli = 1
1045 bc_vsb = 1
1046 elif encmode == 'snz': # sz (only) already set above
1047 src_zero = 1
1048 bc_snz = 1
1049 elif encmode == 'lu': # LR update mode
1050 bc_lru = 1
1051 else:
1052 raise AssertionError("unknown encmode %s" % encmode)
1053 else:
1054 raise AssertionError("unknown encmode %s" % encmode)
1055
1056 if ptype == '2P':
1057 # since m=xx takes precedence (overrides) sm=xx and dm=xx,
1058 # treat them as mutually exclusive
1059 if mask_m_specified:
1060 assert not has_smask,\
1061 "cannot have both source-mask and predicate mask"
1062 assert not has_pmask,\
1063 "cannot have both dest-mask and predicate mask"
1064 # since the default is INT predication (ALWAYS), if you
1065 # specify one CR mask, you must specify both, to avoid
1066 # mixing INT and CR reg types
1067 if has_pmask and pmmode == 1:
1068 assert has_smask, \
1069 "need explicit source-mask in CR twin predication"
1070 if has_smask and smmode == 1:
1071 assert has_pmask, \
1072 "need explicit dest-mask in CR twin predication"
1073 # sanity-check that 2Pred mask is same mode
1074 if has_pmask and has_smask:
1075 assert smmode == pmmode, \
1076 "predicate masks %s and %s must be same reg type" % \
1077 (pme, sme)
1078
1079 # sanity-check that twin-predication mask only specified in 2P mode
1080 if ptype == '1P':
1081 assert not has_smask, \
1082 "source-mask can only be specified on Twin-predicate ops"
1083 assert not has_pmask, \
1084 "dest-mask can only be specified on Twin-predicate ops"
1085
1086 # construct the mode field, doing sanity-checking along the way
1087 if mapreduce_svm:
1088 assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
1089 assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
1090
1091 if src_zero:
1092 assert has_smask or mask_m_specified, \
1093 "src zeroing requires a source predicate"
1094 if dst_zero:
1095 assert has_pmask or mask_m_specified, \
1096 "dest zeroing requires a dest predicate"
1097
1098 # check LDST shifted, only available in "normal" mode
1099 if is_ldst and ldst_shift:
1100 assert sv_mode is None, \
1101 "LD shift cannot have modes (%s) applied" % sv_mode
1102
1103 # okaaay, so there are 4 different modes, here, which will be
1104 # partly-merged-in: is_ldst is merged in with "normal", but
1105 # is_bc is so different it's done separately. likewise is_cr
1106 # (when it is done). here are the maps:
1107
1108 # for "normal" arithmetic: https://libre-soc.org/openpower/sv/normal/
1109 """
1110 | 0-1 | 2 | 3 4 | description |
1111 | --- | --- |---------|-------------------------- |
1112 | 00 | 0 | dz sz | normal mode |
1113 | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 |
1114 | 00 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 |
1115 | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 |
1116 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
1117 | 01 | inv | VLi RC1 | Rc=0: ffirst z/nonz |
1118 | 10 | N | dz sz | sat mode: N=0/1 u/s |
1119 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1120 | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
1121 """
1122
1123 # https://libre-soc.org/openpower/sv/ldst/
1124 # for LD/ST-immediate:
1125 """
1126 | 0-1 | 2 | 3 4 | description |
1127 | --- | --- |---------|--------------------------- |
1128 | 00 | 0 | dz els | normal mode |
1129 | 00 | 1 | dz shf | shift mode |
1130 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
1131 | 01 | inv | els RC1 | Rc=0: ffirst z/nonz |
1132 | 10 | N | dz els | sat mode: N=0/1 u/s |
1133 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1134 | 11 | inv | els RC1 | Rc=0: pred-result z/nonz |
1135 """
1136
1137 # for LD/ST-indexed (RA+RB):
1138 """
1139 | 0-1 | 2 | 3 4 | description |
1140 | --- | --- |---------|-------------------------- |
1141 | 00 | SEA | dz sz | normal mode |
1142 | 01 | SEA | dz sz | Strided (scalar only source) |
1143 | 10 | N | dz sz | sat mode: N=0/1 u/s |
1144 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1145 | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
1146 """
1147
1148 # and leaving out branches and cr_ops for now because they're
1149 # under development
1150 """ TODO branches and cr_ops
1151 """
1152
1153 # now create mode and (overridden) src/dst widths
1154 # XXX TODO: sanity-check bc modes
1155 if is_bc:
1156 sv_mode = ((bc_svstep << SVP64MODE.MOD2_MSB) |
1157 (bc_vlset << SVP64MODE.MOD2_LSB) |
1158 (bc_snz << SVP64MODE.BC_SNZ))
1159 srcwid = (bc_vsb << 1) | bc_lru
1160 destwid = (bc_lru << 1) | bc_all
1161
1162 else:
1163
1164 ######################################
1165 # "normal" mode
1166 if sv_mode is None:
1167 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
1168 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
1169 if is_ldst:
1170 # TODO: for now, LD/ST-indexed is ignored.
1171 mode |= ldst_elstride << SVP64MODE.ELS_NORMAL # el-strided
1172 # shifted mode
1173 if ldst_shift:
1174 mode |= 1 << SVP64MODE.LDST_SHIFT
1175 else:
1176 # TODO, reduce and subvector mode
1177 # 00 1 dz CRM reduce mode (mapreduce), SUBVL=1
1178 # 00 1 SVM CRM subvector reduce mode, SUBVL>1
1179 pass
1180 sv_mode = 0b00
1181
1182 ######################################
1183 # "mapreduce" modes
1184 elif sv_mode == 0b00:
1185 mode |= (0b1 << SVP64MODE.REDUCE) # sets mapreduce
1186 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
1187 if reverse_gear:
1188 mode |= (0b1 << SVP64MODE.RG) # sets Reverse-gear mode
1189 if mapreduce_crm:
1190 mode |= (0b1 << SVP64MODE.CRM) # sets CRM mode
1191 assert rc_mode, "CRM only allowed when Rc=1"
1192 # bit of weird encoding to jam zero-pred or SVM mode in.
1193 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
1194 if subvl == 0:
1195 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
1196 elif mapreduce_svm:
1197 mode |= (0b1 << SVP64MODE.SVM) # sets SVM mode
1198
1199 ######################################
1200 # "failfirst" modes
1201 elif sv_mode == 0b01:
1202 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
1203 if failfirst == 'RC1':
1204 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1205 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1206 assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1207 elif failfirst == '~RC1':
1208 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1209 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1210 mode |= (0b1 << SVP64MODE.INV) # ... with inversion
1211 assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1212 else:
1213 assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
1214 assert rc_mode, "ffirst BO only possible when Rc=1"
1215 mode |= (failfirst << SVP64MODE.BO_LSB) # set BO
1216
1217 ######################################
1218 # "saturation" modes
1219 elif sv_mode == 0b10:
1220 mode |= src_zero << SVP64MODE.SZ # predicate zeroing
1221 mode |= dst_zero << SVP64MODE.DZ # predicate zeroing
1222 mode |= (saturation << SVP64MODE.N) # signed/us saturation
1223
1224 ######################################
1225 # "predicate-result" modes. err... code-duplication from ffirst
1226 elif sv_mode == 0b11:
1227 assert src_zero == 0, "dest-zero not allowed in predresult mode"
1228 if predresult == 'RC1':
1229 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1230 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1231 assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1232 elif predresult == '~RC1':
1233 mode |= (0b1 << SVP64MODE.RC1) # sets RC1 mode
1234 mode |= (dst_zero << SVP64MODE.DZ) # predicate dst-zeroing
1235 mode |= (0b1 << SVP64MODE.INV) # ... with inversion
1236 assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1237 else:
1238 assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
1239 assert rc_mode, "pr-mode BO only possible when Rc=1"
1240 mode |= (predresult << SVP64MODE.BO_LSB) # set BO
1241
1242 # whewww.... modes all done :)
1243 # now put into svp64_rm
1244 mode |= sv_mode
1245 # mode: bits 19-23
1246 svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
1247
1248 # put in predicate masks into svp64_rm
1249 if ptype == '2P':
1250 # source pred: bits 16-18
1251 svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
1252 # mask mode: bit 0
1253 svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
1254 # 1-pred: bits 1-3
1255 svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
1256
1257 # and subvl: bits 8-9
1258 svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
1259
1260 # put in elwidths
1261 # srcwid: bits 6-7
1262 svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
1263 # destwid: bits 4-5
1264 svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
1265
1266 # nice debug printout. (and now for something completely different)
1267 # https://youtu.be/u0WOIwlXE9g?t=146
1268 svp64_rm_value = svp64_rm.spr.value
1269 log("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
1270 log(" mmode 0 :", bin(mmode))
1271 log(" pmask 1-3 :", bin(pmask))
1272 log(" dstwid 4-5 :", bin(destwid))
1273 log(" srcwid 6-7 :", bin(srcwid))
1274 log(" subvl 8-9 :", bin(subvl))
1275 log(" mode 19-23:", bin(mode))
1276 offs = 2 if etype == 'EXTRA2' else 3 # 2 or 3 bits
1277 for idx, sv_extra in extras.items():
1278 if idx is None:
1279 continue
1280 if idx[0] == 'imm':
1281 continue
1282 srcdest, idx, duplicate = idx
1283 start = (10+idx*offs)
1284 end = start + offs-1
1285 log(" extra%d %2d-%2d:" % (idx, start, end),
1286 bin(sv_extra))
1287 if ptype == '2P':
1288 log(" smask 16-17:", bin(smask))
1289 log()
1290
1291 # first, construct the prefix from its subfields
1292 svp64_prefix = SVP64PrefixFields()
1293 svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
1294 svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
1295 svp64_prefix.rm.eq(svp64_rm.spr)
1296
1297 # fiinally yield the svp64 prefix and the thingy. v3.0b opcode
1298 rc = '.' if rc_mode else ''
1299 yield ".long 0x%08x" % svp64_prefix.insn.value
1300 log(v30b_op, v30b_newfields)
1301 # argh, sv.fmadds etc. need to be done manually
1302 if v30b_op == 'ffmadds':
1303 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1304 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1305 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1306 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1307 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
1308 opcode |= 0b00101 << (32-31) # bits 26-30
1309 if rc:
1310 opcode |= 1 # Rc, bit 31.
1311 yield ".long 0x%x" % opcode
1312 # argh, sv.fdmadds need to be done manually
1313 elif v30b_op == 'fdmadds':
1314 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1315 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1316 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1317 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1318 opcode |= int(v30b_newfields[3]) << (32-26) # FRC
1319 opcode |= 0b01111 << (32-31) # bits 26-30
1320 if rc:
1321 opcode |= 1 # Rc, bit 31.
1322 yield ".long 0x%x" % opcode
1323 # argh, sv.ffadds etc. need to be done manually
1324 elif v30b_op == 'ffadds':
1325 opcode = 59 << (32-6) # bits 0..6 (MSB0)
1326 opcode |= int(v30b_newfields[0]) << (32-11) # FRT
1327 opcode |= int(v30b_newfields[1]) << (32-16) # FRA
1328 opcode |= int(v30b_newfields[2]) << (32-21) # FRB
1329 opcode |= 0b01101 << (32-31) # bits 26-30
1330 if rc:
1331 opcode |= 1 # Rc, bit 31.
1332 yield ".long 0x%x" % opcode
1333 # sigh have to do svstep here manually for now...
1334 elif v30b_op in ["svstep", "svstep."]:
1335 insn = 22 << (31-5) # opcode 22, bits 0-5
1336 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
1337 insn |= int(v30b_newfields[1]) << (31-22) # SVi , bits 16-22
1338 insn |= int(v30b_newfields[2]) << (31-25) # vf , bit 25
1339 insn |= 0b10011 << (31-30) # XO , bits 26..30
1340 if opcode == 'svstep.':
1341 insn |= 1 << (31-31) # Rc=1 , bit 31
1342 log("svstep", bin(insn))
1343 yield ".long 0x%x" % insn
1344 # argh, sv.fcoss etc. need to be done manually
1345 elif v30b_op in ["fcoss", "fcoss."]:
1346 insn = 59 << (31-5) # opcode 59, bits 0-5
1347 insn |= int(v30b_newfields[0]) << (31-10) # RT , bits 6-10
1348 insn |= int(v30b_newfields[1]) << (31-20) # RB , bits 16-20
1349 insn |= 0b1000101110 << (31-30) # XO , bits 21..30
1350 if opcode == 'fcoss.':
1351 insn |= 1 << (31-31) # Rc=1 , bit 31
1352 log("fcoss", bin(insn))
1353 yield ".long 0x%x" % insn
1354 else:
1355 yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
1356 log("new v3.0B fields", v30b_op, v30b_newfields)
1357
1358 def translate(self, lst):
1359 for insn in lst:
1360 yield from self.translate_one(insn)
1361
1362
1363 def macro_subst(macros, txt):
1364 again = True
1365 log("subst", txt, macros)
1366 while again:
1367 again = False
1368 for macro, value in macros.items():
1369 if macro == txt:
1370 again = True
1371 replaced = txt.replace(macro, value)
1372 log("macro", txt, "replaced", replaced, macro, value)
1373 txt = replaced
1374 continue
1375 toreplace = '%s.s' % macro
1376 if toreplace == txt:
1377 again = True
1378 replaced = txt.replace(toreplace, "%s.s" % value)
1379 log("macro", txt, "replaced", replaced, toreplace, value)
1380 txt = replaced
1381 continue
1382 toreplace = '%s.v' % macro
1383 if toreplace == txt:
1384 again = True
1385 replaced = txt.replace(toreplace, "%s.v" % value)
1386 log("macro", txt, "replaced", replaced, toreplace, value)
1387 txt = replaced
1388 continue
1389 toreplace = '(%s)' % macro
1390 if toreplace in txt:
1391 again = True
1392 replaced = txt.replace(toreplace, '(%s)' % value)
1393 log("macro", txt, "replaced", replaced, toreplace, value)
1394 txt = replaced
1395 continue
1396 log(" processed", txt)
1397 return txt
1398
1399
1400 def get_ws(line):
1401 # find whitespace
1402 ws = ''
1403 while line:
1404 if not line[0].isspace():
1405 break
1406 ws += line[0]
1407 line = line[1:]
1408 return ws, line
1409
1410
1411 def asm_process():
1412 # get an input file and an output file
1413 args = sys.argv[1:]
1414 if len(args) == 0:
1415 infile = sys.stdin
1416 outfile = sys.stdout
1417 # read the whole lot in advance in case of in-place
1418 lines = list(infile.readlines())
1419 elif len(args) != 2:
1420 print("pysvp64asm [infile | -] [outfile | -]", file=sys.stderr)
1421 exit(0)
1422 else:
1423 if args[0] == '--':
1424 infile = sys.stdin
1425 else:
1426 infile = open(args[0], "r")
1427 # read the whole lot in advance in case of in-place overwrite
1428 lines = list(infile.readlines())
1429
1430 if args[1] == '--':
1431 outfile = sys.stdout
1432 else:
1433 outfile = open(args[1], "w")
1434
1435 # read the line, look for custom insn, process it
1436 macros = {} # macros which start ".set"
1437 isa = SVP64Asm([])
1438 for line in lines:
1439 op = line.split("#")[0].strip()
1440 # identify macros
1441 if op.startswith(".set"):
1442 macro = op[4:].split(",")
1443 (macro, value) = map(str.strip, macro)
1444 macros[macro] = value
1445 if not op.startswith('sv.') and not op.startswith(tuple(CUSTOM_INSNS)):
1446 outfile.write(line)
1447 continue
1448
1449 (ws, line) = get_ws(line)
1450 lst = isa.translate_one(op, macros)
1451 lst = '; '.join(lst)
1452 outfile.write("%s%s # %s\n" % (ws, lst, op))
1453
1454
1455 if __name__ == '__main__':
1456 lst = ['slw 3, 1, 4',
1457 'extsw 5, 3',
1458 'sv.extsw 5, 3',
1459 'sv.cmpi 5, 1, 3, 2',
1460 'sv.setb 5, 31',
1461 'sv.isel 64.v, 3, 2, 65.v',
1462 'sv.setb/dm=r3/sm=1<<r3 5, 31',
1463 'sv.setb/m=r3 5, 31',
1464 'sv.setb/vec2 5, 31',
1465 'sv.setb/sw=8/ew=16 5, 31',
1466 'sv.extsw./ff=eq 5, 31',
1467 'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
1468 'sv.extsw./pr=eq 5.v, 31',
1469 'sv.add. 5.v, 2.v, 1.v',
1470 'sv.add./m=r3 5.v, 2.v, 1.v',
1471 ]
1472 lst += [
1473 'sv.stw 5.v, 4(1.v)',
1474 'sv.ld 5.v, 4(1.v)',
1475 'setvl. 2, 3, 4, 0, 1, 1',
1476 'sv.setvl. 2, 3, 4, 0, 1, 1',
1477 ]
1478 lst = [
1479 "sv.stfsu 0.v, 16(4.v)",
1480 ]
1481 lst = [
1482 "sv.stfsu/els 0.v, 16(4)",
1483 ]
1484 lst = [
1485 'sv.add./mr 5.v, 2.v, 1.v',
1486 ]
1487 macros = {'win2': '50', 'win': '60'}
1488 lst = [
1489 'sv.addi win2.v, win.v, -1',
1490 'sv.add./mrr 5.v, 2.v, 1.v',
1491 #'sv.lhzsh 5.v, 11(9.v), 15',
1492 #'sv.lwzsh 5.v, 11(9.v), 15',
1493 'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
1494 ]
1495 lst = [
1496 #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
1497 #'sv.ffadds 0.v, 8.v, 4.v',
1498 'svremap 11, 0, 1, 2, 3, 2, 1',
1499 'svshape 8, 1, 1, 1, 0',
1500 'svshape 8, 1, 1, 1, 1',
1501 ]
1502 lst = [
1503 #'sv.lfssh 4.v, 11(8.v), 15',
1504 #'sv.lwzsh 4.v, 11(8.v), 15',
1505 #'sv.svstep. 2.v, 4, 0',
1506 #'sv.fcfids. 48.v, 64.v',
1507 'sv.fcoss. 80.v, 0.v',
1508 'sv.fcoss. 20.v, 0.v',
1509 ]
1510 lst = [
1511 'sv.bc/all 3,12,192',
1512 'sv.bclr/vsbi 3,81.v,192',
1513 'sv.ld 5.v, 4(1.v)',
1514 'sv.svstep. 2.v, 4, 0',
1515 ]
1516 lst = [
1517 'maxs 3,12,5',
1518 'maxs. 3,12,5',
1519 'avgadd 3,12,5',
1520 'absdu 3,12,5',
1521 'absds 3,12,5',
1522 'absdacu 3,12,5',
1523 'absdacs 3,12,5',
1524 'cprop 3,12,5',
1525 'svindex 0,0,1,0,0,0,0',
1526 ]
1527 lst = [
1528 'sv.svstep./m=r3 2.v, 4, 0',
1529 'ternlogi 0,0,0,0x5',
1530 'fmvis 5,65535',
1531 'fmvis 5,1',
1532 'fmvis 5,32768',
1533 ]
1534 isa = SVP64Asm(lst, macros=macros)
1535 log("list", list(isa))
1536 asm_process()