src/openpower/sv/trans/svp64.py

   1 # SPDX-License-Identifier: LGPLv3+
   2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   3 # Funded by NLnet http://nlnet.nl
   4
   5 """SVP64 OpenPOWER v3.0B assembly translator
   6
   7 This class takes raw svp64 assembly mnemonics (aliases excluded) and creates
   8 an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode.
   9
  10 It is very simple and straightforward, the only weirdness being the
  11 extraction of the register information and conversion to v3.0B numbering.
  12
  13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
  14 Encoding format of arithmetic: https://libre-soc.org/openpower/sv/normal/
  15 Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/
  16 **TODO format of branches: https://libre-soc.org/openpower/sv/branches/**
  17 **TODO format of CRs: https://libre-soc.org/openpower/sv/cr_ops/**
  18 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
  19 """
  20
  21 import os
  22 import sys
  23 from collections import OrderedDict
  24
  25 from openpower.decoder.isa.caller import (SVP64PrefixFields, SV64P_MAJOR_SIZE,
  26                                           SV64P_PID_SIZE, SVP64RMFields,
  27                                           SVP64RM_EXTRA2_SPEC_SIZE,
  28                                           SVP64RM_EXTRA3_SPEC_SIZE,
  29                                           SVP64RM_MODE_SIZE, SVP64RM_SMASK_SIZE,
  30                                           SVP64RM_MMODE_SIZE, SVP64RM_MASK_SIZE,
  31                                           SVP64RM_SUBVL_SIZE, SVP64RM_EWSRC_SIZE,
  32                                           SVP64RM_ELWIDTH_SIZE)
  33 from openpower.decoder.pseudo.pagereader import ISA
  34 from openpower.decoder.power_svp64 import SVP64RM, get_regtype, decode_extra
  35 from openpower.decoder.selectable_int import SelectableInt
  36 from openpower.consts import SVP64MODE
  37
  38 # for debug logging
  39 from openpower.util import log
  40
  41
  42 # decode GPR into sv extra
  43 def get_extra_gpr(etype, regmode, field):
  44     if regmode == 'scalar':
  45         # cut into 2-bits 5-bits SS FFFFF
  46         sv_extra = field >> 5
  47         field = field & 0b11111
  48     else:
  49         # cut into 5-bits 2-bits FFFFF SS
  50         sv_extra = field & 0b11
  51         field = field >> 2
  52     return sv_extra, field
  53
  54
  55 # decode 3-bit CR into sv extra
  56 def get_extra_cr_3bit(etype, regmode, field):
  57     if regmode == 'scalar':
  58         # cut into 2-bits 3-bits SS FFF
  59         sv_extra = field >> 3
  60         field = field & 0b111
  61     else:
  62         # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
  63         sv_extra = field & 0b1111
  64         field = field >> 4
  65     return sv_extra, field
  66
  67
  68 # decodes SUBVL
  69 def decode_subvl(encoding):
  70     pmap = {'2': 0b01, '3': 0b10, '4': 0b11}
  71     assert encoding in pmap, \
  72         "encoding %s for SUBVL not recognised" % encoding
  73     return pmap[encoding]
  74
  75
  76 # decodes elwidth
  77 def decode_elwidth(encoding):
  78     pmap = {'8': 0b11, '16': 0b10, '32': 0b01}
  79     assert encoding in pmap, \
  80         "encoding %s for elwidth not recognised" % encoding
  81     return pmap[encoding]
  82
  83
  84 # decodes predicate register encoding
  85 def decode_predicate(encoding):
  86     pmap = {  # integer
  87         '1<<r3': (0, 0b001),
  88         'r3': (0, 0b010),
  89         '~r3': (0, 0b011),
  90         'r10': (0, 0b100),
  91         '~r10': (0, 0b101),
  92         'r30': (0, 0b110),
  93         '~r30': (0, 0b111),
  94         # CR
  95         'lt': (1, 0b000),
  96         'nl': (1, 0b001), 'ge': (1, 0b001),  # same value
  97         'gt': (1, 0b010),
  98         'ng': (1, 0b011), 'le': (1, 0b011),  # same value
  99         'eq': (1, 0b100),
 100         'ne': (1, 0b101),
 101         'so': (1, 0b110), 'un': (1, 0b110),  # same value
 102         'ns': (1, 0b111), 'nu': (1, 0b111),  # same value
 103     }
 104     assert encoding in pmap, \
 105         "encoding %s for predicate not recognised" % encoding
 106     return pmap[encoding]
 107
 108
 109 # decodes "Mode" in similar way to BO field (supposed to, anyway)
 110 def decode_bo(encoding):
 111     pmap = {  # TODO: double-check that these are the same as Branch BO
 112         'lt': 0b000,
 113         'nl': 0b001, 'ge': 0b001,  # same value
 114         'gt': 0b010,
 115         'ng': 0b011, 'le': 0b011,  # same value
 116         'eq': 0b100,
 117         'ne': 0b101,
 118         'so': 0b110, 'un': 0b110,  # same value
 119         'ns': 0b111, 'nu': 0b111,  # same value
 120     }
 121     assert encoding in pmap, \
 122         "encoding %s for BO Mode not recognised" % encoding
 123     return pmap[encoding]
 124
 125 # partial-decode fail-first mode
 126
 127
 128 def decode_ffirst(encoding):
 129     if encoding in ['RC1', '~RC1']:
 130         return encoding
 131     return decode_bo(encoding)
 132
 133
 134 def decode_reg(field):
 135     # decode the field number. "5.v" or "3.s" or "9"
 136     field = field.split(".")
 137     regmode = 'scalar'  # default
 138     if len(field) == 2:
 139         if field[1] == 's':
 140             regmode = 'scalar'
 141         elif field[1] == 'v':
 142             regmode = 'vector'
 143     field = int(field[0])  # actual register number
 144     return field, regmode
 145
 146
 147 def decode_imm(field):
 148     ldst_imm = "(" in field and field[-1] == ')'
 149     if ldst_imm:
 150         return field[:-1].split("(")
 151     else:
 152         return None, field
 153
 154
 155 def crf_extra(etype, regmode, field, extras):
 156     """takes a CR Field number (CR0-CR127), splits into EXTRA2/3 and v3.0
 157     the scalar/vector mode (crNN.v or crNN.s) changes both the format
 158     of the EXTRA2/3 encoding as well as what range of registers is possible.
 159     this function can be used for both BF/BFA and BA/BB/BT by first removing
 160     the bottom 2 bits of BA/BB/BT then re-instating them after encoding.
 161     see https://libre-soc.org/openpower/sv/svp64/appendix/#cr_extra
 162     for specification
 163     """
 164     sv_extra, field = get_extra_cr_3bit(etype, regmode, field)
 165     # now sanity-check (and shrink afterwards)
 166     if etype == 'EXTRA2':
 167         # 3-bit CR Field (BF, BFA) EXTRA2 encoding
 168         if regmode == 'scalar':
 169             # range is CR0-CR15 in increments of 1
 170             assert (sv_extra >> 1) == 0, \
 171                 "scalar CR %s cannot fit into EXTRA2 %s" % \
 172                 (rname, str(extras[extra_idx]))
 173             # all good: encode as scalar
 174             sv_extra = sv_extra & 0b01
 175         else: # vector
 176             # range is CR0-CR127 in increments of 16
 177             assert sv_extra & 0b111 == 0, \
 178                 "vector CR %s cannot fit into EXTRA2 %s" % \
 179                 (rname, str(extras[extra_idx]))
 180             # all good: encode as vector (bit 2 set)
 181             sv_extra = 0b10 | (sv_extra >> 3)
 182     else:
 183         # 3-bit CR Field (BF, BFA) EXTRA3 encoding
 184         if regmode == 'scalar':
 185             # range is CR0-CR31 in increments of 1
 186             assert (sv_extra >> 2) == 0, \
 187                 "scalar CR %s cannot fit into EXTRA3 %s" % \
 188                 (rname, str(extras[extra_idx]))
 189             # all good: encode as scalar
 190             sv_extra = sv_extra & 0b11
 191         else: # vector
 192             # range is CR0-CR127 in increments of 8
 193             assert sv_extra & 0b11 == 0, \
 194                 "vector CR %s cannot fit into EXTRA3 %s" % \
 195                 (rname, str(extras[extra_idx]))
 196             # all good: encode as vector (bit 3 set)
 197             sv_extra = 0b100 | (sv_extra >> 2)
 198     return sv_extra, field
 199
 200
 201 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
 202 class SVP64Asm:
 203     def __init__(self, lst, bigendian=False, macros=None):
 204         if macros is None:
 205             macros = {}
 206         self.macros = macros
 207         self.lst = lst
 208         self.trans = self.translate(lst)
 209         self.isa = ISA()  # reads the v3.0B pseudo-code markdown files
 210         self.svp64 = SVP64RM()  # reads the svp64 Remap entries for registers
 211         assert bigendian == False, "error, bigendian not supported yet"
 212
 213     def __iter__(self):
 214         yield from self.trans
 215
 216     def translate_one(self, insn, macros=None):
 217         if macros is None:
 218             macros = {}
 219         macros.update(self.macros)
 220         isa = self.isa
 221         svp64 = self.svp64
 222         # find first space, to get opcode
 223         ls = insn.split(' ')
 224         opcode = ls[0]
 225         # now find opcode fields
 226         fields = ''.join(ls[1:]).split(',')
 227         mfields = list(map(str.strip, fields))
 228         log("opcode, fields", ls, opcode, mfields)
 229         fields = []
 230         # macro substitution
 231         for field in mfields:
 232             fields.append(macro_subst(macros, field))
 233         log("opcode, fields substed", ls, opcode, fields)
 234
 235         # this is a *32-bit-only* instruction. it controls SVSTATE.
 236         # it is *not* a 64-bit-prefixed Vector instruction (no sv.setvl),
 237         # it is a Vector *control* instruction.
 238         # note: EXT022 is the "sandbox" major opcode so it's fine to add
 239
 240         # sigh have to do setvl here manually for now...
 241         # note the subtract one from SVi.
 242         if opcode in ["setvl", "setvl."]:
 243             # 1.6.28 SVL-FORM - from fields.txt
 244             # |0     |6    |11    |16   |23 |24 |25 |26    |31 |
 245             # | PO   |  RT |   RA | SVi |ms |vs |vf |   XO |Rc |
 246             insn = 22 << (31-5)          # opcode 22, bits 0-5
 247             fields = list(map(int, fields))
 248             insn |= fields[0] << (31-10)  # RT       , bits 6-10
 249             insn |= fields[1] << (31-15)  # RA       , bits 11-15
 250             insn |= (fields[2]-1) << (31-22)  # SVi      , bits 16-22
 251             insn |= fields[3] << (31-25)  # vf       , bit  25
 252             insn |= fields[4] << (31-24)  # vs       , bit  24
 253             insn |= fields[5] << (31-23)  # ms       , bit  23
 254             insn |= 0b11011 << (31-30)    # XO       , bits 26..30
 255             if opcode == 'setvl.':
 256                 insn |= 1 << (31-31)     # Rc=1     , bit 31
 257             log("setvl", bin(insn))
 258             yield ".long 0x%x" % insn
 259             return
 260
 261         # this is a 32-bit instruction. it updates SVSTATE.
 262         # it *can* be SVP64-prefixed, to indicate that its registers
 263         # are Vectorised.
 264         # note: EXT022 is the "sandbox" major opcode so it's fine to add
 265
 266         # sigh have to do setvl here manually for now...
 267         # note the subtract one from SVi.
 268         if opcode in ["svstep", "svstep."]:
 269             # 1.6.28 SVL-FORM - from fields.txt
 270             # |0     |6    |11    |16   |23 |24 |25 |26    |31 |
 271             # | PO   |  RT |   RA | SVi |ms |vs |vf |   XO |Rc |
 272             insn = 22 << (31-5)          # opcode 22, bits 0-5
 273             fields = list(map(int, fields))
 274             insn |= fields[0] << (31-10)  # RT       , bits 6-10
 275             insn |= (fields[1]-1) << (31-22)  # SVi      , bits 16-22
 276             insn |= fields[2] << (31-25)  # vf       , bit  25
 277             insn |= 0b10011 << (31-30)    # XO       , bits 26..30
 278             if opcode == 'svstep.':
 279                 insn |= 1 << (31-31)     # Rc=1     , bit 31
 280             log("svstep", bin(insn))
 281             yield ".long 0x%x" % insn
 282             return
 283
 284         # this is a *32-bit-only* instruction. it updates SVSHAPE and SVSTATE.
 285         # it is *not* a 64-bit-prefixed Vector instruction (no sv.svshape),
 286         # it is a Vector *control* instruction.
 287         # note: EXT022 is the "sandbox" major opcode so it's fine to add
 288
 289         # and svshape.  note that the dimension fields one subtracted from each
 290         if opcode == 'svshape':
 291             # 1.6.33 SVM-FORM from fields.txt
 292             # |0  |6        |11      |16    |21    |25 |26    |31  |
 293             # |PO |  SVxd   |   SVyd | SVzd | SVRM |vf |   XO |  / |
 294             insn = 22 << (31-5)          # opcode 22, bits 0-5
 295             fields = list(map(int, fields))
 296             insn |= (fields[0]-1) << (31-10)  # SVxd       , bits 6-10
 297             insn |= (fields[1]-1) << (31-15)  # SVyd       , bits 11-15
 298             insn |= (fields[2]-1) << (31-20)  # SVzd       , bits 16-20
 299             insn |= (fields[3]) << (31-24)  # SVRM       , bits 21-24
 300             insn |= (fields[4]) << (31-25)  # vf         , bits 25
 301             insn |= 0b011001 << (31-31)  # XO       , bits 26..31
 302             #insn &= ((1<<32)-1)
 303             log("svshape", bin(insn))
 304             yield ".long 0x%x" % insn
 305             return
 306
 307         # this is a *32-bit-only* instruction. it updates the SVSHAPE SPR
 308         # it is *not* a 64-bit-prefixed Vector instruction (no sv.svremap),
 309         # it is a Vector *control* instruction.
 310         # note: EXT022 is the "sandbox" major opcode so it's fine to add
 311
 312         # and svremap
 313         if opcode == 'svremap':
 314             # 1.6.34 SVRM-FORM from fields.txt
 315             # |0  |6     |11  |13   |15   |17   |19   |21  |22   |26     |31 |
 316             # |PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |///  | XO    | / |
 317             insn = 22 << (31-5)          # opcode 22, bits 0-5
 318             fields = list(map(int, fields))
 319             insn |= fields[0] << (31-10)  # SVme       , bits 6-10
 320             insn |= fields[1] << (31-12)  # mi0        , bits 11-12
 321             insn |= fields[2] << (31-14)  # mi1        , bits 13-14
 322             insn |= fields[3] << (31-16)  # mi2        , bits 15-16
 323             insn |= fields[4] << (31-18)  # m00        , bits 17-18
 324             insn |= fields[5] << (31-20)  # m01        , bits 19-20
 325             insn |= fields[6] << (31-21)  # pst        , bit 21
 326             insn |= 0b111001 << (31-31)   # XO       , bits 26..31
 327             log("svremap", bin(insn))
 328             yield ".long 0x%x" % insn
 329             return
 330
 331         # ok from here-on down these are added as 32-bit instructions
 332         # and are here only because binutils (at present) doesn't have
 333         # them (that's being fixed!)
 334         # they can - if implementations then choose - be Vectorised
 335         # (sv.fsins) because they are general-purpose scalar instructions
 336
 337         # 1.6.2.2 BM2-FORM
 338         # |0     |6    |11    |16    |21   |26 |27    31|
 339         # | PO   |  RT |   RA |   RB |bm   |L  |   XO   |
 340         if opcode == ('bmask'):
 341             fields = list(map(int, fields))
 342             insn = 22 << (31-5)  # opcode 22, bits 0-5
 343             insn |= fields[0] << (31-10)  # RT       , bits 6-10
 344             insn |= fields[1] << (31-15)  # RA       , bits 11-15
 345             insn |= fields[2] << (31-20)  # RB       , bits 16-20
 346             insn |= fields[3] << (31-25)  # mask     , bits 21-25
 347             insn |= fields[4] << (31-26)   # L       , bit 26
 348             insn |=  0b010001 << (31-31)   # XO       , bits 26..31
 349             log("bmask", bin(insn))
 350             yield ".long 0x%x" % insn
 351             return
 352
 353
 354         # and fsins
 355         # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
 356         # however we are out of space with opcode 22
 357         if opcode.startswith('fsins'):
 358             fields = list(map(int, fields))
 359             insn = 59 << (31-5)  # opcode 59, bits 0-5
 360             insn |= fields[0] << (31-10)  # RT       , bits 6-10
 361             insn |= fields[1] << (31-20)  # RB       , bits 16-20
 362             insn |= 0b1000001110 << (31-30)  # XO       , bits 21..30
 363             if opcode == 'fsins.':
 364                 insn |= 1 << (31-31)     # Rc=1     , bit 31
 365             log("fsins", bin(insn))
 366             yield ".long 0x%x" % insn
 367             return
 368
 369         # and fcoss
 370         # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
 371         # however we are out of space with opcode 22
 372         if opcode.startswith('fcoss'):
 373             fields = list(map(int, fields))
 374             insn = 59 << (31-5)  # opcode 59, bits 0-5
 375             insn |= fields[0] << (31-10)  # RT       , bits 6-10
 376             insn |= fields[1] << (31-20)  # RB       , bits 16-20
 377             insn |= 0b1000101110 << (31-30)  # XO       , bits 21..30
 378             if opcode == 'fcoss.':
 379                 insn |= 1 << (31-31)     # Rc=1     , bit 31
 380             log("fcoss", bin(insn))
 381             yield ".long 0x%x" % insn
 382             return
 383
 384         # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
 385         # however we are out of space with opcode 22
 386         if opcode in ('ternlogi', 'ternlogi.'):
 387             po = 5
 388             xo = 0
 389             rt = int(fields[0])
 390             ra = int(fields[1])
 391             rb = int(fields[2])
 392             imm = int(fields[3])
 393             rc = '.' in opcode
 394             instr = po
 395             instr = (instr << 5) | rt
 396             instr = (instr << 5) | ra
 397             instr = (instr << 5) | rb
 398             instr = (instr << 8) | imm
 399             instr = (instr << 2) | xo
 400             instr = (instr << 1) | rc
 401             asm = f"{opcode} {rt}, {ra}, {rb}, {imm}"
 402             yield f".4byte {hex(instr)} # {asm}"
 403             return
 404
 405         # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
 406         # however we are out of space with opcode 22
 407         if opcode in ('grev', 'grevi', 'grevw', 'grevwi',
 408                       'grev.', 'grevi.', 'grevw.', 'grevwi.'):
 409             po = 5
 410             # _ matches fields in table at:
 411             # https://libre-soc.org/openpower/sv/bitmanip/
 412             xo = 0b1_0010_110
 413             if 'w' in opcode:
 414                 xo |= 0b100_000
 415             if 'i' in opcode:
 416                 xo |= 0b1000_000
 417             Rc = 1 if '.' in opcode else 0
 418             rt = int(fields[0])
 419             ra = int(fields[1])
 420             rb_imm = int(fields[2])
 421             instr = po
 422             instr = (instr << 5) | rt
 423             instr = (instr << 5) | ra
 424             if opcode == 'grevi' or opcode == 'grevi.':
 425                 assert 0 <= rb_imm < 64
 426                 instr = (instr << 6) | rb_imm
 427                 instr = (instr << 9) | xo
 428             else:
 429                 assert 0 <= rb_imm < 32
 430                 instr = (instr << 5) | rb_imm
 431                 instr = (instr << 10) | xo
 432             instr = (instr << 1) | Rc
 433             asm = f"{opcode} {rt}, {ra}, {rb_imm}"
 434             yield f".4byte {hex(instr)} # {asm}"
 435             return
 436
 437         # and min/max
 438         # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
 439         # 1.6.7 X-FORM
 440         # |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 441         # | PO   |       RT      |    RA       |    RB       |   XO |Rc  |
 442         if opcode in ['mins', 'maxs', 'minu', 'maxu',
 443                      'mins.', 'maxs.', 'minu.', 'maxu.']:
 444             if opcode[:4] == 'maxs':
 445                 XO = 0b0111001110
 446             if opcode[:4] == 'maxu':
 447                 XO = 0b0011001110
 448             if opcode[:4] == 'mins':
 449                 XO = 0b0101001110
 450             if opcode[:4] == 'minu':
 451                 XO = 0b0001001110
 452             fields = list(map(int, fields))
 453             insn = 22 << (31-5)  # opcode 22, bits 0-5
 454             insn |= fields[0] << (31-10)  # RT       , bits 6-10
 455             insn |= fields[1] << (31-15)  # RA       , bits 11-15
 456             insn |= fields[2] << (31-20)  # RB       , bits 16-20
 457             insn |= XO        << (31-30)  # XO       , bits 21..30
 458             if opcode.endswith('.'):
 459                 insn |= 1 << (31-31)     # Rc=1     , bit 31
 460             log("maxs", bin(insn))
 461             yield ".long 0x%x" % insn
 462             return
 463
 464         # and avgadd, absdu, absdacu, absdacs
 465         # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
 466         # 1.6.7 X-FORM
 467         # |0     |6 |7|8|9  |10  |11|12|13  |15|16|17     |20|21    |31  |
 468         # | PO   |       RT      |    RA       |    RB       |   XO |Rc  |
 469         if opcode in ['avgadd', 'absdu', 'absds', 'absdacu', 'absdacs',
 470                       'cprop']:
 471             if opcode[:5] == 'absdu':
 472                 XO = 0b1011110110
 473             elif opcode[:5] == 'absds':
 474                 XO = 0b1001110110
 475             elif opcode[:6] == 'avgadd':
 476                 XO = 0b1101001110
 477             elif opcode[:7] == 'absdacu':
 478                 XO = 0b1111110110
 479             elif opcode[:7] == 'absdacs':
 480                 XO = 0b0111110110
 481             elif opcode[:7] == 'cprop':
 482                 XO = 0b0110001110
 483             fields = list(map(int, fields))
 484             insn = 22 << (31-5)  # opcode 22, bits 0-5
 485             insn |= fields[0] << (31-10)  # RT       , bits 6-10
 486             insn |= fields[1] << (31-15)  # RA       , bits 11-15
 487             insn |= fields[2] << (31-20)  # RB       , bits 16-20
 488             insn |= XO        << (31-30)  # XO       , bits 21..30
 489             if opcode.endswith('.'):
 490                 insn |= 1 << (31-31)     # Rc=1     , bit 31
 491             log(opcode, bin(insn))
 492             yield ".long 0x%x" % insn
 493             return
 494
 495         # identify if is a svp64 mnemonic
 496         if not opcode.startswith('sv.'):
 497             yield insn  # unaltered
 498             return
 499         opcode = opcode[3:]  # strip leading "sv"
 500
 501         # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
 502         opmodes = opcode.split("/")  # split at "/"
 503         v30b_op = opmodes.pop(0)    # first is the v3.0B
 504         # check instruction ends with dot
 505         rc_mode = v30b_op.endswith('.')
 506         if rc_mode:
 507             v30b_op = v30b_op[:-1]
 508
 509         # sigh again, have to recognised LD/ST bit-reverse instructions
 510         # this has to be "processed" to fit into a v3.0B without the "sh"
 511         # e.g. ldsh is actually ld
 512         ldst_shift = v30b_op.startswith("l") and v30b_op.endswith("sh")
 513
 514         if v30b_op not in isa.instr:
 515             raise Exception("opcode %s of '%s' not supported" %
 516                             (v30b_op, insn))
 517
 518         if ldst_shift:
 519             # okaay we need to process the fields and make this:
 520             #     ldsh RT, SVD(RA), RC  - 11 bits for SVD, 5 for RC
 521             # into this:
 522             #     ld RT, D(RA)          - 16 bits
 523             # likewise same for SVDS (9 bits for SVDS, 5 for RC, 14 bits for DS)
 524             form = isa.instr[v30b_op].form  # get form (SVD-Form, SVDS-Form)
 525
 526             newfields = []
 527             for field in fields:
 528                 # identify if this is a ld/st immediate(reg) thing
 529                 ldst_imm = "(" in field and field[-1] == ')'
 530                 if ldst_imm:
 531                     newfields.append(field[:-1].split("("))
 532                 else:
 533                     newfields.append(field)
 534
 535             immed, RA = newfields[1]
 536             immed = int(immed)
 537             RC = int(newfields.pop(2))  # better be an integer number!
 538             if form == 'SVD':  # 16 bit: immed 11 bits, RC shift up 11
 539                 immed = (immed & 0b11111111111) | (RC << 11)
 540                 if immed & (1 << 15):  # should be negative
 541                     immed -= 1 << 16
 542             if form == 'SVDS':  # 14 bit: immed 9 bits, RC shift up 9
 543                 immed = (immed & 0b111111111) | (RC << 9)
 544                 if immed & (1 << 13):  # should be negative
 545                     immed -= 1 << 14
 546             newfields[1] = "%d(%s)" % (immed, RA)
 547             fields = newfields
 548
 549             # and strip off "sh" from end, and add "sh" to opmodes, instead
 550             v30b_op = v30b_op[:-2]
 551             opmodes.append("sh")
 552             log("rewritten", v30b_op, opmodes, fields)
 553
 554         if v30b_op not in svp64.instrs:
 555             raise Exception("opcode %s of '%s' not an svp64 instruction" %
 556                             (v30b_op, insn))
 557         v30b_regs = isa.instr[v30b_op].regs[0]  # get regs info "RT, RA, RB"
 558         rm = svp64.instrs[v30b_op]             # one row of the svp64 RM CSV
 559         log("v3.0B op", v30b_op, "Rc=1" if rc_mode else '')
 560         log("v3.0B regs", opcode, v30b_regs)
 561         log("RM", rm)
 562
 563         # right.  the first thing to do is identify the ordering of
 564         # the registers, by name.  the EXTRA2/3 ordering is in
 565         # rm['0']..rm['3'] but those fields contain the names RA, BB
 566         # etc.  we have to read the pseudocode to understand which
 567         # reg is which in our instruction. sigh.
 568
 569         # first turn the svp64 rm into a "by name" dict, recording
 570         # which position in the RM EXTRA it goes into
 571         # also: record if the src or dest was a CR, for sanity-checking
 572         # (elwidth overrides on CRs are banned)
 573         decode = decode_extra(rm)
 574         dest_reg_cr, src_reg_cr, svp64_src, svp64_dest = decode
 575
 576         log("EXTRA field index, src", svp64_src)
 577         log("EXTRA field index, dest", svp64_dest)
 578
 579         # okaaay now we identify the field value (opcode N,N,N) with
 580         # the pseudo-code info (opcode RT, RA, RB)
 581         assert len(fields) == len(v30b_regs), \
 582             "length of fields %s must match insn `%s` fields %s" % \
 583             (str(v30b_regs), insn, str(fields))
 584         opregfields = zip(fields, v30b_regs)  # err that was easy
 585
 586         # now for each of those find its place in the EXTRA encoding
 587         # note there is the possibility (for LD/ST-with-update) of
 588         # RA occurring **TWICE**.  to avoid it getting added to the
 589         # v3.0B suffix twice, we spot it as a duplicate, here
 590         extras = OrderedDict()
 591         for idx, (field, regname) in enumerate(opregfields):
 592             imm, regname = decode_imm(regname)
 593             rtype = get_regtype(regname)
 594             log("    idx find", rtype, idx, field, regname, imm)
 595             if rtype is None:
 596                 # probably an immediate field, append it straight
 597                 extras[('imm', idx, False)] = (idx, field, None, None, None)
 598                 continue
 599             extra = svp64_src.get(regname, None)
 600             if extra is not None:
 601                 extra = ('s', extra, False)  # not a duplicate
 602                 extras[extra] = (idx, field, regname, rtype, imm)
 603                 log("    idx src", idx, extra, extras[extra])
 604             dextra = svp64_dest.get(regname, None)
 605             log("regname in", regname, dextra)
 606             if dextra is not None:
 607                 is_a_duplicate = extra is not None  # duplicate spotted
 608                 dextra = ('d', dextra, is_a_duplicate)
 609                 extras[dextra] = (idx, field, regname, rtype, imm)
 610                 log("    idx dst", idx, extra, extras[dextra])
 611
 612         # great! got the extra fields in their associated positions:
 613         # also we know the register type. now to create the EXTRA encodings
 614         etype = rm['Etype']  # Extra type: EXTRA3/EXTRA2
 615         ptype = rm['Ptype']  # Predication type: Twin / Single
 616         extra_bits = 0
 617         v30b_newfields = []
 618         for extra_idx, (idx, field, rname, rtype, iname) in extras.items():
 619             # is it a field we don't alter/examine?  if so just put it
 620             # into newfields
 621             if rtype is None:
 622                 v30b_newfields.append(field)
 623                 continue
 624
 625             # identify if this is a ld/st immediate(reg) thing
 626             ldst_imm = "(" in field and field[-1] == ')'
 627             if ldst_imm:
 628                 immed, field = field[:-1].split("(")
 629
 630             field, regmode = decode_reg(field)
 631             log("    ", extra_idx, rname, rtype,
 632                 regmode, iname, field, end=" ")
 633
 634             # see Mode field https://libre-soc.org/openpower/sv/svp64/
 635             # XXX TODO: the following is a bit of a laborious repeated
 636             # mess, which could (and should) easily be parameterised.
 637             # XXX also TODO: the LD/ST modes which are different
 638             # https://libre-soc.org/openpower/sv/ldst/
 639
 640             # rright.  SVP64 register numbering is from 0 to 127
 641             # for GPRs, FPRs *and* CR Fields, where for v3.0 the GPRs and RPFs
 642             # are 0-31 and CR Fields are only 0-7.  the SVP64 RM "Extra"
 643             # area is used to extend the numbering from the 32-bit
 644             # instruction, and also to record whether the register
 645             # is scalar or vector. on a per-operand basis.  this
 646             # results in a slightly finnicky encoding: here we go...
 647
 648             # encode SV-GPR and SV-FPR field into extra, v3.0field
 649             if rtype in ['GPR', 'FPR']:
 650                 sv_extra, field = get_extra_gpr(etype, regmode, field)
 651                 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
 652                 # (and shrink to a single bit if ok)
 653                 if etype == 'EXTRA2':
 654                     if regmode == 'scalar':
 655                         # range is r0-r63 in increments of 1
 656                         assert (sv_extra >> 1) == 0, \
 657                             "scalar GPR %s cannot fit into EXTRA2 %s" % \
 658                             (rname, str(extras[extra_idx]))
 659                         # all good: encode as scalar
 660                         sv_extra = sv_extra & 0b01
 661                     else:
 662                         # range is r0-r127 in increments of 2 (r0 r2 ... r126)
 663                         assert sv_extra & 0b01 == 0, \
 664                             "%s: vector field %s cannot fit " \
 665                             "into EXTRA2 %s" % \
 666                             (insn, rname, str(extras[extra_idx]))
 667                         # all good: encode as vector (bit 2 set)
 668                         sv_extra = 0b10 | (sv_extra >> 1)
 669                 elif regmode == 'vector':
 670                     # EXTRA3 vector bit needs marking
 671                     sv_extra |= 0b100
 672
 673             # encode SV-CR 3-bit field into extra, v3.0field.
 674             # 3-bit is for things like BF and BFA
 675             elif rtype == 'CR_3bit':
 676                 sv_extra, field =  crf_extra(etype, regmode, field, extras)
 677
 678             # encode SV-CR 5-bit field into extra, v3.0field
 679             # 5-bit is for things like BA BB BC BT etc.
 680             # *sigh* this is the same as 3-bit except the 2 LSBs of the
 681             # 5-bit field are passed through unaltered.
 682             elif rtype == 'CR_5bit':
 683                 cr_subfield = field & 0b11 # record bottom 2 bits for later
 684                 field = field >> 2         # strip bottom 2 bits
 685                 # use the exact same 3-bit function for the top 3 bits
 686                 sv_extra, field =  crf_extra(etype, regmode, field, extras)
 687                 # reconstruct the actual 5-bit CR field (preserving the
 688                 # bottom 2 bits, unaltered)
 689                 field = (field << 2) | cr_subfield
 690
 691             else:
 692                 raise Exception("no type match: %s" % rtype)
 693
 694             # capture the extra field info
 695             log("=>", "%5s" % bin(sv_extra), field)
 696             extras[extra_idx] = sv_extra
 697
 698             # append altered field value to v3.0b, differs for LDST
 699             # note that duplicates are skipped e.g. EXTRA2 contains
 700             # *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
 701             srcdest, idx, duplicate = extra_idx
 702             if duplicate:  # skip adding to v3.0b fields, already added
 703                 continue
 704             if ldst_imm:
 705                 v30b_newfields.append(("%s(%s)" % (immed, str(field))))
 706             else:
 707                 v30b_newfields.append(str(field))
 708
 709         log("new v3.0B fields", v30b_op, v30b_newfields)
 710         log("extras", extras)
 711
 712         # rright.  now we have all the info. start creating SVP64 RM
 713         svp64_rm = SVP64RMFields()
 714
 715         # begin with EXTRA fields
 716         for idx, sv_extra in extras.items():
 717             log(idx)
 718             if idx is None:
 719                 continue
 720             if idx[0] == 'imm':
 721                 continue
 722             srcdest, idx, duplicate = idx
 723             if etype == 'EXTRA2':
 724                 svp64_rm.extra2[idx].eq(
 725                     SelectableInt(sv_extra, SVP64RM_EXTRA2_SPEC_SIZE))
 726             else:
 727                 svp64_rm.extra3[idx].eq(
 728                     SelectableInt(sv_extra, SVP64RM_EXTRA3_SPEC_SIZE))
 729
 730         # identify if the op is a LD/ST. the "blegh" way. copied
 731         # from power_enums.  TODO, split the list _insns down.
 732         is_ld = v30b_op in [
 733             "lbarx", "lbz", "lbzu", "lbzux", "lbzx",            # load byte
 734             "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx",       # load double
 735             "lfs", "lfsx", "lfsu", "lfsux",                     # FP load single
 736             "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax",  # FP load dbl
 737             "lha", "lharx", "lhau", "lhaux", "lhax",            # load half
 738             "lhbrx", "lhz", "lhzu", "lhzux", "lhzx",            # more load half
 739             "lwa", "lwarx", "lwaux", "lwax", "lwbrx",           # load word
 740             "lwz", "lwzcix", "lwzu", "lwzux", "lwzx",           # more load word
 741         ]
 742         is_st = v30b_op in [
 743             "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
 744             "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
 745             "stfs", "stfsx", "stfsu", "stfux",                  # FP store sgl
 746             "stfd", "stfdx", "stfdu", "stfdux", "stfiwx",       # FP store dbl
 747             "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
 748             "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
 749         ]
 750         # use this to determine if the SVP64 RM format is different.
 751         # see https://libre-soc.org/openpower/sv/ldst/
 752         is_ldst = is_ld or is_st
 753
 754         # branch-conditional detection
 755         is_bc = v30b_op in [
 756             "bc", "bclr",
 757         ]
 758
 759         # parts of svp64_rm
 760         mmode = 0  # bit 0
 761         pmask = 0  # bits 1-3
 762         destwid = 0  # bits 4-5
 763         srcwid = 0  # bits 6-7
 764         subvl = 0   # bits 8-9
 765         smask = 0  # bits 16-18 but only for twin-predication
 766         mode = 0  # bits 19-23
 767
 768         mask_m_specified = False
 769         has_pmask = False
 770         has_smask = False
 771
 772         saturation = None
 773         src_zero = 0
 774         dst_zero = 0
 775         sv_mode = None
 776
 777         mapreduce = False
 778         reverse_gear = False
 779         mapreduce_crm = False
 780         mapreduce_svm = False
 781
 782         predresult = False
 783         failfirst = False
 784         ldst_elstride = 0
 785
 786         # branch-conditional bits
 787         bc_all = 0
 788         bc_lru = 0
 789         bc_brc = 0
 790         bc_svstep = 0
 791         bc_vsb = 0
 792         bc_vlset = 0
 793         bc_vli = 0
 794         bc_snz = 0
 795
 796         # ok let's start identifying opcode augmentation fields
 797         for encmode in opmodes:
 798             # predicate mask (src and dest)
 799             if encmode.startswith("m="):
 800                 pme = encmode
 801                 pmmode, pmask = decode_predicate(encmode[2:])
 802                 smmode, smask = pmmode, pmask
 803                 mmode = pmmode
 804                 mask_m_specified = True
 805             # predicate mask (dest)
 806             elif encmode.startswith("dm="):
 807                 pme = encmode
 808                 pmmode, pmask = decode_predicate(encmode[3:])
 809                 mmode = pmmode
 810                 has_pmask = True
 811             # predicate mask (src, twin-pred)
 812             elif encmode.startswith("sm="):
 813                 sme = encmode
 814                 smmode, smask = decode_predicate(encmode[3:])
 815                 mmode = smmode
 816                 has_smask = True
 817             # shifted LD/ST
 818             elif encmode.startswith("sh"):
 819                 ldst_shift = True
 820             # vec2/3/4
 821             elif encmode.startswith("vec"):
 822                 subvl = decode_subvl(encmode[3:])
 823             # elwidth
 824             elif encmode.startswith("ew="):
 825                 destwid = decode_elwidth(encmode[3:])
 826             elif encmode.startswith("sw="):
 827                 srcwid = decode_elwidth(encmode[3:])
 828             # element-strided LD/ST
 829             elif encmode == 'els':
 830                 ldst_elstride = 1
 831             # saturation
 832             elif encmode == 'sats':
 833                 assert sv_mode is None
 834                 saturation = 1
 835                 sv_mode = 0b10
 836             elif encmode == 'satu':
 837                 assert sv_mode is None
 838                 sv_mode = 0b10
 839                 saturation = 0
 840             # predicate zeroing
 841             elif encmode == 'sz':
 842                 src_zero = 1
 843             elif encmode == 'dz':
 844                 dst_zero = 1
 845             # failfirst
 846             elif encmode.startswith("ff="):
 847                 assert sv_mode is None
 848                 sv_mode = 0b01
 849                 failfirst = decode_ffirst(encmode[3:])
 850             # predicate-result, interestingly same as fail-first
 851             elif encmode.startswith("pr="):
 852                 assert sv_mode is None
 853                 sv_mode = 0b11
 854                 predresult = decode_ffirst(encmode[3:])
 855             # map-reduce mode, reverse-gear
 856             elif encmode == 'mrr':
 857                 assert sv_mode is None
 858                 sv_mode = 0b00
 859                 mapreduce = True
 860                 reverse_gear = True
 861             # map-reduce mode
 862             elif encmode == 'mr':
 863                 assert sv_mode is None
 864                 sv_mode = 0b00
 865                 mapreduce = True
 866             elif encmode == 'crm':  # CR on map-reduce
 867                 assert sv_mode is None
 868                 sv_mode = 0b00
 869                 mapreduce_crm = True
 870             elif encmode == 'svm':  # sub-vector mode
 871                 mapreduce_svm = True
 872             elif is_bc:
 873                 if encmode == 'all':
 874                     bc_all = 1
 875                 elif encmode == 'st':  # svstep mode
 876                     bc_step = 1
 877                 elif encmode == 'sr':  # svstep BRc mode
 878                     bc_step = 1
 879                     bc_brc = 1
 880                 elif encmode == 'vs':  # VLSET mode
 881                     bc_vlset = 1
 882                 elif encmode == 'vsi':  # VLSET mode with VLI (VL inclusives)
 883                     bc_vlset = 1
 884                     bc_vli = 1
 885                 elif encmode == 'vsb':  # VLSET mode with VSb
 886                     bc_vlset = 1
 887                     bc_vsb = 1
 888                 elif encmode == 'vsbi':  # VLSET mode with VLI and VSb
 889                     bc_vlset = 1
 890                     bc_vli = 1
 891                     bc_vsb = 1
 892                 elif encmode == 'snz':  # sz (only) already set above
 893                     src_zero = 1
 894                     bc_snz = 1
 895                 elif encmode == 'lu':  # LR update mode
 896                     bc_lru = 1
 897                 else:
 898                     raise AssertionError("unknown encmode %s" % encmode)
 899             else:
 900                 raise AssertionError("unknown encmode %s" % encmode)
 901
 902         if ptype == '2P':
 903             # since m=xx takes precedence (overrides) sm=xx and dm=xx,
 904             # treat them as mutually exclusive
 905             if mask_m_specified:
 906                 assert not has_smask,\
 907                     "cannot have both source-mask and predicate mask"
 908                 assert not has_pmask,\
 909                     "cannot have both dest-mask and predicate mask"
 910             # since the default is INT predication (ALWAYS), if you
 911             # specify one CR mask, you must specify both, to avoid
 912             # mixing INT and CR reg types
 913             if has_pmask and pmmode == 1:
 914                 assert has_smask, \
 915                     "need explicit source-mask in CR twin predication"
 916             if has_smask and smmode == 1:
 917                 assert has_pmask, \
 918                     "need explicit dest-mask in CR twin predication"
 919             # sanity-check that 2Pred mask is same mode
 920             if has_pmask and has_smask:
 921                 assert smmode == pmmode, \
 922                     "predicate masks %s and %s must be same reg type" % \
 923                     (pme, sme)
 924
 925         # sanity-check that twin-predication mask only specified in 2P mode
 926         if ptype == '1P':
 927             assert not has_smask, \
 928                 "source-mask can only be specified on Twin-predicate ops"
 929             assert not has_pmask, \
 930                 "dest-mask can only be specified on Twin-predicate ops"
 931
 932         # construct the mode field, doing sanity-checking along the way
 933         if mapreduce_svm:
 934             assert sv_mode == 0b00, "sub-vector mode in mapreduce only"
 935             assert subvl != 0, "sub-vector mode not possible on SUBVL=1"
 936
 937         if src_zero:
 938             assert has_smask or mask_m_specified, \
 939                 "src zeroing requires a source predicate"
 940         if dst_zero:
 941             assert has_pmask or mask_m_specified, \
 942                 "dest zeroing requires a dest predicate"
 943
 944         # check LDST shifted, only available in "normal" mode
 945         if is_ldst and ldst_shift:
 946             assert sv_mode is None, \
 947                 "LD shift cannot have modes (%s) applied" % sv_mode
 948
 949         # okaaay, so there are 4 different modes, here, which will be
 950         # partly-merged-in: is_ldst is merged in with "normal", but
 951         # is_bc is so different it's done separately.  likewise is_cr
 952         # (when it is done).  here are the maps:
 953
 954         # for "normal" arithmetic: https://libre-soc.org/openpower/sv/normal/
 955         """
 956             | 0-1 |  2  |  3   4  |  description              |
 957             | --- | --- |---------|-------------------------- |
 958             | 00  |   0 |  dz  sz | normal mode                      |
 959             | 00  |   1 | 0  RG   | scalar reduce mode (mapreduce), SUBVL=1 |
 960             | 00  |   1 | 1  /    | parallel reduce mode (mapreduce), SUBVL=1 |
 961             | 00  |   1 | SVM RG  | subvector reduce mode, SUBVL>1   |
 962             | 01  | inv | CR-bit  | Rc=1: ffirst CR sel              |
 963             | 01  | inv | VLi RC1 |  Rc=0: ffirst z/nonz |
 964             | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
 965             | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
 966             | 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
 967         """
 968
 969         # https://libre-soc.org/openpower/sv/ldst/
 970         # for LD/ST-immediate:
 971         """
 972             | 0-1 |  2  |  3   4  |  description               |
 973             | --- | --- |---------|--------------------------- |
 974             | 00  | 0   |  dz els | normal mode                |
 975             | 00  | 1   |  dz shf | shift mode                 |
 976             | 01  | inv | CR-bit  | Rc=1: ffirst CR sel        |
 977             | 01  | inv | els RC1 |  Rc=0: ffirst z/nonz       |
 978             | 10  |   N | dz  els |  sat mode: N=0/1 u/s       |
 979             | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel  |
 980             | 11  | inv | els RC1 |  Rc=0: pred-result z/nonz  |
 981         """
 982
 983         # for LD/ST-indexed (RA+RB):
 984         """
 985             | 0-1 |  2  |  3   4  |  description              |
 986             | --- | --- |---------|-------------------------- |
 987             | 00  | SEA |  dz  sz | normal mode        |
 988             | 01  | SEA | dz sz  | Strided (scalar only source)   |
 989             | 10  |   N | dz   sz |  sat mode: N=0/1 u/s |
 990             | 11  | inv | CR-bit  |  Rc=1: pred-result CR sel |
 991             | 11  | inv | dz  RC1 |  Rc=0: pred-result z/nonz |
 992         """
 993
 994         # and leaving out branches and cr_ops for now because they're
 995         # under development
 996         """ TODO branches and cr_ops
 997         """
 998
 999         # now create mode and (overridden) src/dst widths
1000         # XXX TODO: sanity-check bc modes
1001         if is_bc:
1002             sv_mode = ((bc_svstep << SVP64MODE.MOD2_MSB) |
1003                        (bc_vlset << SVP64MODE.MOD2_LSB) |
1004                        (bc_snz << SVP64MODE.BC_SNZ))
1005             srcwid = (bc_vsb << 1) | bc_lru
1006             destwid = (bc_lru << 1) | bc_all
1007
1008         else:
1009
1010             ######################################
1011             # "normal" mode
1012             if sv_mode is None:
1013                 mode |= src_zero << SVP64MODE.SZ  # predicate zeroing
1014                 mode |= dst_zero << SVP64MODE.DZ  # predicate zeroing
1015                 if is_ldst:
1016                     # TODO: for now, LD/ST-indexed is ignored.
1017                     mode |= ldst_elstride << SVP64MODE.ELS_NORMAL  # el-strided
1018                     # shifted mode
1019                     if ldst_shift:
1020                         mode |= 1 << SVP64MODE.LDST_SHIFT
1021                 else:
1022                     # TODO, reduce and subvector mode
1023                     # 00  1   dz CRM  reduce mode (mapreduce), SUBVL=1
1024                     # 00  1   SVM CRM subvector reduce mode, SUBVL>1
1025                     pass
1026                 sv_mode = 0b00
1027
1028             ######################################
1029             # "mapreduce" modes
1030             elif sv_mode == 0b00:
1031                 mode |= (0b1 << SVP64MODE.REDUCE)  # sets mapreduce
1032                 assert dst_zero == 0, "dest-zero not allowed in mapreduce mode"
1033                 if reverse_gear:
1034                     mode |= (0b1 << SVP64MODE.RG)  # sets Reverse-gear mode
1035                 if mapreduce_crm:
1036                     mode |= (0b1 << SVP64MODE.CRM)  # sets CRM mode
1037                     assert rc_mode, "CRM only allowed when Rc=1"
1038                 # bit of weird encoding to jam zero-pred or SVM mode in.
1039                 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
1040                 if subvl == 0:
1041                     mode |= dst_zero << SVP64MODE.DZ  # predicate zeroing
1042                 elif mapreduce_svm:
1043                     mode |= (0b1 << SVP64MODE.SVM)  # sets SVM mode
1044
1045             ######################################
1046             # "failfirst" modes
1047             elif sv_mode == 0b01:
1048                 assert src_zero == 0, "dest-zero not allowed in failfirst mode"
1049                 if failfirst == 'RC1':
1050                     mode |= (0b1 << SVP64MODE.RC1)  # sets RC1 mode
1051                     mode |= (dst_zero << SVP64MODE.DZ)  # predicate dst-zeroing
1052                     assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1053                 elif failfirst == '~RC1':
1054                     mode |= (0b1 << SVP64MODE.RC1)  # sets RC1 mode
1055                     mode |= (dst_zero << SVP64MODE.DZ)  # predicate dst-zeroing
1056                     mode |= (0b1 << SVP64MODE.INV)  # ... with inversion
1057                     assert rc_mode == False, "ffirst RC1 only ok when Rc=0"
1058                 else:
1059                     assert dst_zero == 0, "dst-zero not allowed in ffirst BO"
1060                     assert rc_mode, "ffirst BO only possible when Rc=1"
1061                     mode |= (failfirst << SVP64MODE.BO_LSB)  # set BO
1062
1063             ######################################
1064             # "saturation" modes
1065             elif sv_mode == 0b10:
1066                 mode |= src_zero << SVP64MODE.SZ  # predicate zeroing
1067                 mode |= dst_zero << SVP64MODE.DZ  # predicate zeroing
1068                 mode |= (saturation << SVP64MODE.N)  # signed/us saturation
1069
1070             ######################################
1071             # "predicate-result" modes.  err... code-duplication from ffirst
1072             elif sv_mode == 0b11:
1073                 assert src_zero == 0, "dest-zero not allowed in predresult mode"
1074                 if predresult == 'RC1':
1075                     mode |= (0b1 << SVP64MODE.RC1)  # sets RC1 mode
1076                     mode |= (dst_zero << SVP64MODE.DZ)  # predicate dst-zeroing
1077                     assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1078                 elif predresult == '~RC1':
1079                     mode |= (0b1 << SVP64MODE.RC1)  # sets RC1 mode
1080                     mode |= (dst_zero << SVP64MODE.DZ)  # predicate dst-zeroing
1081                     mode |= (0b1 << SVP64MODE.INV)  # ... with inversion
1082                     assert rc_mode == False, "pr-mode RC1 only ok when Rc=0"
1083                 else:
1084                     assert dst_zero == 0, "dst-zero not allowed in pr-mode BO"
1085                     assert rc_mode, "pr-mode BO only possible when Rc=1"
1086                     mode |= (predresult << SVP64MODE.BO_LSB)  # set BO
1087
1088         # whewww.... modes all done :)
1089         # now put into svp64_rm
1090         mode |= sv_mode
1091         # mode: bits 19-23
1092         svp64_rm.mode.eq(SelectableInt(mode, SVP64RM_MODE_SIZE))
1093
1094         # put in predicate masks into svp64_rm
1095         if ptype == '2P':
1096             # source pred: bits 16-18
1097             svp64_rm.smask.eq(SelectableInt(smask, SVP64RM_SMASK_SIZE))
1098         # mask mode: bit 0
1099         svp64_rm.mmode.eq(SelectableInt(mmode, SVP64RM_MMODE_SIZE))
1100         # 1-pred: bits 1-3
1101         svp64_rm.mask.eq(SelectableInt(pmask, SVP64RM_MASK_SIZE))
1102
1103         # and subvl: bits 8-9
1104         svp64_rm.subvl.eq(SelectableInt(subvl, SVP64RM_SUBVL_SIZE))
1105
1106         # put in elwidths
1107         # srcwid: bits 6-7
1108         svp64_rm.ewsrc.eq(SelectableInt(srcwid, SVP64RM_EWSRC_SIZE))
1109         # destwid: bits 4-5
1110         svp64_rm.elwidth.eq(SelectableInt(destwid, SVP64RM_ELWIDTH_SIZE))
1111
1112         # nice debug printout. (and now for something completely different)
1113         # https://youtu.be/u0WOIwlXE9g?t=146
1114         svp64_rm_value = svp64_rm.spr.value
1115         log("svp64_rm", hex(svp64_rm_value), bin(svp64_rm_value))
1116         log("    mmode  0    :", bin(mmode))
1117         log("    pmask  1-3  :", bin(pmask))
1118         log("    dstwid 4-5  :", bin(destwid))
1119         log("    srcwid 6-7  :", bin(srcwid))
1120         log("    subvl  8-9  :", bin(subvl))
1121         log("    mode   19-23:", bin(mode))
1122         offs = 2 if etype == 'EXTRA2' else 3  # 2 or 3 bits
1123         for idx, sv_extra in extras.items():
1124             if idx is None:
1125                 continue
1126             if idx[0] == 'imm':
1127                 continue
1128             srcdest, idx, duplicate = idx
1129             start = (10+idx*offs)
1130             end = start + offs-1
1131             log("    extra%d %2d-%2d:" % (idx, start, end),
1132                 bin(sv_extra))
1133         if ptype == '2P':
1134             log("    smask  16-17:", bin(smask))
1135         log()
1136
1137         # first, construct the prefix from its subfields
1138         svp64_prefix = SVP64PrefixFields()
1139         svp64_prefix.major.eq(SelectableInt(0x1, SV64P_MAJOR_SIZE))
1140         svp64_prefix.pid.eq(SelectableInt(0b11, SV64P_PID_SIZE))
1141         svp64_prefix.rm.eq(svp64_rm.spr)
1142
1143         # fiinally yield the svp64 prefix and the thingy.  v3.0b opcode
1144         rc = '.' if rc_mode else ''
1145         yield ".long 0x%08x" % svp64_prefix.insn.value
1146         log(v30b_newfields)
1147         # argh, sv.fmadds etc. need to be done manually
1148         if v30b_op == 'ffmadds':
1149             opcode = 59 << (32-6)    # bits 0..6 (MSB0)
1150             opcode |= int(v30b_newfields[0]) << (32-11)  # FRT
1151             opcode |= int(v30b_newfields[1]) << (32-16)  # FRA
1152             opcode |= int(v30b_newfields[2]) << (32-21)  # FRB
1153             opcode |= int(v30b_newfields[3]) << (32-26)  # FRC
1154             opcode |= 0b00101 << (32-31)   # bits 26-30
1155             if rc:
1156                 opcode |= 1  # Rc, bit 31.
1157             yield ".long 0x%x" % opcode
1158         # argh, sv.fdmadds need to be done manually
1159         elif v30b_op == 'fdmadds':
1160             opcode = 59 << (32-6)    # bits 0..6 (MSB0)
1161             opcode |= int(v30b_newfields[0]) << (32-11)  # FRT
1162             opcode |= int(v30b_newfields[1]) << (32-16)  # FRA
1163             opcode |= int(v30b_newfields[2]) << (32-21)  # FRB
1164             opcode |= int(v30b_newfields[3]) << (32-26)  # FRC
1165             opcode |= 0b01111 << (32-31)   # bits 26-30
1166             if rc:
1167                 opcode |= 1  # Rc, bit 31.
1168             yield ".long 0x%x" % opcode
1169         # argh, sv.ffadds etc. need to be done manually
1170         elif v30b_op == 'ffadds':
1171             opcode = 59 << (32-6)    # bits 0..6 (MSB0)
1172             opcode |= int(v30b_newfields[0]) << (32-11)  # FRT
1173             opcode |= int(v30b_newfields[1]) << (32-16)  # FRA
1174             opcode |= int(v30b_newfields[2]) << (32-21)  # FRB
1175             opcode |= 0b01101 << (32-31)   # bits 26-30
1176             if rc:
1177                 opcode |= 1  # Rc, bit 31.
1178             yield ".long 0x%x" % opcode
1179         # sigh have to do svstep here manually for now...
1180         elif opcode in ["svstep", "svstep."]:
1181             insn = 22 << (31-5)          # opcode 22, bits 0-5
1182             insn |= int(v30b_newfields[0]) << (31-10)  # RT       , bits 6-10
1183             insn |= int(v30b_newfields[1]) << (31-22)  # SVi      , bits 16-22
1184             insn |= int(v30b_newfields[2]) << (31-25)  # vf       , bit  25
1185             insn |= 0b10011 << (31-30)  # XO       , bits 26..30
1186             if opcode == 'svstep.':
1187                 insn |= 1 << (31-31)     # Rc=1     , bit 31
1188             log("svstep", bin(insn))
1189             yield ".long 0x%x" % insn
1190         # argh, sv.fcoss etc. need to be done manually
1191         elif v30b_op in ["fcoss", "fcoss."]:
1192             insn = 59 << (31-5)  # opcode 59, bits 0-5
1193             insn |= int(v30b_newfields[0]) << (31-10)  # RT       , bits 6-10
1194             insn |= int(v30b_newfields[1]) << (31-20)  # RB       , bits 16-20
1195             insn |= 0b1000101110 << (31-30)  # XO       , bits 21..30
1196             if opcode == 'fcoss.':
1197                 insn |= 1 << (31-31)     # Rc=1     , bit 31
1198             log("fcoss", bin(insn))
1199             yield ".long 0x%x" % insn
1200
1201         else:
1202             yield "%s %s" % (v30b_op+rc, ", ".join(v30b_newfields))
1203         log("new v3.0B fields", v30b_op, v30b_newfields)
1204
1205     def translate(self, lst):
1206         for insn in lst:
1207             yield from self.translate_one(insn)
1208
1209
1210 def macro_subst(macros, txt):
1211     again = True
1212     log("subst", txt, macros)
1213     while again:
1214         again = False
1215         for macro, value in macros.items():
1216             if macro == txt:
1217                 again = True
1218                 replaced = txt.replace(macro, value)
1219                 log("macro", txt, "replaced", replaced, macro, value)
1220                 txt = replaced
1221                 continue
1222             toreplace = '%s.s' % macro
1223             if toreplace == txt:
1224                 again = True
1225                 replaced = txt.replace(toreplace, "%s.s" % value)
1226                 log("macro", txt, "replaced", replaced, toreplace, value)
1227                 txt = replaced
1228                 continue
1229             toreplace = '%s.v' % macro
1230             if toreplace == txt:
1231                 again = True
1232                 replaced = txt.replace(toreplace, "%s.v" % value)
1233                 log("macro", txt, "replaced", replaced, toreplace, value)
1234                 txt = replaced
1235                 continue
1236             toreplace = '(%s)' % macro
1237             if toreplace in txt:
1238                 again = True
1239                 replaced = txt.replace(toreplace, '(%s)' % value)
1240                 log("macro", txt, "replaced", replaced, toreplace, value)
1241                 txt = replaced
1242                 continue
1243     log("    processed", txt)
1244     return txt
1245
1246
1247 def get_ws(line):
1248     # find whitespace
1249     ws = ''
1250     while line:
1251         if not line[0].isspace():
1252             break
1253         ws += line[0]
1254         line = line[1:]
1255     return ws, line
1256
1257
1258 def asm_process():
1259     # get an input file and an output file
1260     args = sys.argv[1:]
1261     if len(args) == 0:
1262         infile = sys.stdin
1263         outfile = sys.stdout
1264         # read the whole lot in advance in case of in-place
1265         lines = list(infile.readlines())
1266     elif len(args) != 2:
1267         print("pysvp64asm [infile | -] [outfile | -]", file=sys.stderr)
1268         exit(0)
1269     else:
1270         if args[0] == '--':
1271             infile = sys.stdin
1272         else:
1273             infile = open(args[0], "r")
1274         # read the whole lot in advance in case of in-place overwrite
1275         lines = list(infile.readlines())
1276
1277         if args[1] == '--':
1278             outfile = sys.stdout
1279         else:
1280             outfile = open(args[1], "w")
1281
1282     # read the line, look for "sv", process it
1283     macros = {}  # macros which start ".set"
1284     isa = SVP64Asm([])
1285     for line in lines:
1286         op = line.split("#")[0].strip()
1287         # identify macros
1288         if op.startswith(".set"):
1289             macro = op[4:].split(",")
1290             (macro, value) = map(str.strip, macro)
1291             macros[macro] = value
1292         if not (op.startswith("sv.") or
1293                 op.startswith("setvl") or
1294                 op.startswith("svshape")):
1295             outfile.write(line)
1296             continue
1297
1298         (ws, line) = get_ws(line)
1299         lst = isa.translate_one(op, macros)
1300         lst = '; '.join(lst)
1301         outfile.write("%s%s # %s\n" % (ws, lst, op))
1302
1303
1304 if __name__ == '__main__':
1305     lst = ['slw 3, 1, 4',
1306            'extsw 5, 3',
1307            'sv.extsw 5, 3',
1308            'sv.cmpi 5, 1, 3, 2',
1309            'sv.setb 5, 31',
1310            'sv.isel 64.v, 3, 2, 65.v',
1311            'sv.setb/dm=r3/sm=1<<r3 5, 31',
1312            'sv.setb/m=r3 5, 31',
1313            'sv.setb/vec2 5, 31',
1314            'sv.setb/sw=8/ew=16 5, 31',
1315            'sv.extsw./ff=eq 5, 31',
1316            'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
1317            'sv.extsw./pr=eq 5.v, 31',
1318            'sv.add. 5.v, 2.v, 1.v',
1319            'sv.add./m=r3 5.v, 2.v, 1.v',
1320            ]
1321     lst += [
1322         'sv.stw 5.v, 4(1.v)',
1323         'sv.ld 5.v, 4(1.v)',
1324         'setvl. 2, 3, 4, 0, 1, 1',
1325         'sv.setvl. 2, 3, 4, 0, 1, 1',
1326     ]
1327     lst = [
1328         "sv.stfsu 0.v, 16(4.v)",
1329     ]
1330     lst = [
1331         "sv.stfsu/els 0.v, 16(4)",
1332     ]
1333     lst = [
1334         'sv.add./mr 5.v, 2.v, 1.v',
1335     ]
1336     macros = {'win2': '50', 'win': '60'}
1337     lst = [
1338         'sv.addi win2.v, win.v, -1',
1339         'sv.add./mrr 5.v, 2.v, 1.v',
1340         #'sv.lhzsh 5.v, 11(9.v), 15',
1341         #'sv.lwzsh 5.v, 11(9.v), 15',
1342         'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
1343     ]
1344     lst = [
1345         #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
1346         #'sv.ffadds 0.v, 8.v, 4.v',
1347         'svremap 11, 0, 1, 2, 3, 2, 1',
1348         'svshape 8, 1, 1, 1, 0',
1349         'svshape 8, 1, 1, 1, 1',
1350     ]
1351     lst = [
1352         #'sv.lfssh 4.v, 11(8.v), 15',
1353         #'sv.lwzsh 4.v, 11(8.v), 15',
1354         #'sv.svstep. 2.v, 4, 0',
1355         #'sv.fcfids. 48.v, 64.v',
1356         'sv.fcoss. 80.v, 0.v',
1357         'sv.fcoss. 20.v, 0.v',
1358     ]
1359     lst = [
1360         'sv.bc/all 3,12,192',
1361         'sv.bclr/vsbi 3,81.v,192',
1362         'sv.ld 5.v, 4(1.v)',
1363         'sv.svstep. 2.v, 4, 0',
1364     ]
1365     lst = [
1366         'maxs 3,12,5',
1367         'maxs. 3,12,5',
1368         'avgadd 3,12,5',
1369         'absdu 3,12,5',
1370         'absds 3,12,5',
1371         'absdacu 3,12,5',
1372         'absdacs 3,12,5',
1373         'cprop 3,12,5',
1374     ]
1375     isa = SVP64Asm(lst, macros=macros)
1376     log("list", list(isa))
1377     asm_process()