e094392e5560774edd1e5a7969203a10ad5bccae
1 # SPDX-License-Identifier: LGPLv3+
2 # Copyright (C) 2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
3 # Funded by NLnet http://nlnet.nl
5 """SVP64 OpenPOWER v3.0B assembly translator
7 This class takes raw svp64 assembly mnemonics (aliases excluded) and creates
8 an EXT001-encoded "svp64 prefix" (as a .long) followed by a v3.0B opcode.
10 It is very simple and straightforward, the only weirdness being the
11 extraction of the register information and conversion to v3.0B numbering.
13 Encoding format of svp64: https://libre-soc.org/openpower/sv/svp64/
14 Encoding format of arithmetic: https://libre-soc.org/openpower/sv/normal/
15 Encoding format of LDST: https://libre-soc.org/openpower/sv/ldst/
16 **TODO format of branches: https://libre-soc.org/openpower/sv/branches/**
17 **TODO format of CRs: https://libre-soc.org/openpower/sv/cr_ops/**
18 Bugtracker: https://bugs.libre-soc.org/show_bug.cgi?id=578
24 from collections
import OrderedDict
27 from openpower
.decoder
.pseudo
.pagereader
import ISA
28 from openpower
.decoder
.power_svp64
import SVP64RM
, get_regtype
, decode_extra
29 from openpower
.decoder
.selectable_int
import SelectableInt
30 from openpower
.consts
import SVP64MODE
31 from openpower
.decoder
.power_insn
import SVP64Instruction
32 from openpower
.decoder
.power_insn
import Database
33 from openpower
.decoder
.power_enums
import find_wiki_dir
36 from openpower
.util
import log
39 def instruction(*fields
):
40 def instruction(insn
, desc
):
41 (value
, start
, end
) = desc
42 bits
= ((1,) * ((end
+ 1) - start
))
45 mask
= ((mask
<< 1) | bit
)
46 return (insn |
((value
& mask
) << (31 - end
)))
48 return functools
.reduce(instruction
, fields
, 0)
54 def _insn(name
, **kwargs
):
58 def _custom_insns(*insns
):
59 """ a decorator that adds the function to `CUSTOM_INSNS` """
64 insns_
= (fn
.__name
__, {}),
67 for name
, kwargs
in insns_
:
68 if not isinstance(name
, str):
69 raise TypeError("instruction name must be a str: {name!r}")
70 if name
in CUSTOM_INSNS
:
71 raise ValueError(f
"duplicate instruction mnemonic: {name!r}")
72 # use getcallargs to check that arguments work:
73 inspect
.getcallargs(fn
, FIELDS_ARG
, **kwargs
)
74 CUSTOM_INSNS
[name
] = functools
.partial(fn
, **kwargs
)
81 _insn("setvl.", Rc
=1),
83 def setvl(fields
, Rc
):
85 setvl is a *32-bit-only* instruction. It controls SVSTATE.
86 It is *not* a 64-bit-prefixed Vector instruction (no sv.setvl, yet),
87 it is a Vector *control* instruction.
89 * setvl RT,RA,SVi,vf,vs,ms
91 1.6.28 SVL-FORM - from fields.txt
92 |0 |6 |11 |16 |23 |24 |25 |26 |31 |
93 | PO | RT | RA | SVi |ms |vs |vf | XO |Rc |
97 # ARRRGH these are in a non-obvious order in openpower/isa/simplev.mdwn
98 # compared to the SVL-Form above. sigh
99 # setvl RT,RA,SVi,vf,vs,ms
100 (RT
, RA
, SVi
, vf
, vs
, ms
) = fields
116 _insn("svstep", Rc
=0),
117 _insn("svstep.", Rc
=1),
119 def svstep(fields
, Rc
):
121 svstep is a 32-bit instruction. It updates SVSTATE.
122 It *can* be SVP64-prefixed, to indicate that its registers
127 # 1.6.28 SVL-FORM - from fields.txt
128 # |0 |6 |11 |16 |23 |24 |25 |26 |31 |
129 # | PO | RT | / | SVi |/ |/ |vf | XO |Rc |
134 (RT
, SVi
, vf
) = fields
152 svshape is a *32-bit-only* instruction. It updates SVSHAPE and SVSTATE.
153 It is *not* a 64-bit-prefixed Vector instruction (no sv.svshape, yet),
154 it is a Vector *control* instruction.
156 https://libre-soc.org/openpower/sv/remap/#svshape
158 * svshape SVxd,SVyd,SVzd,SVrm,vf
160 # 1.6.33 SVM-FORM from fields.txt
161 # |0 |6 |11 |16 |21 |25 |26 |31 |
162 # | PO | SVxd | SVyd | SVzd | SVrm |vf | XO |
164 note that SVrm is not permitted to be 0b0111, 0b1000 or 0b1001.
165 0b0111 is reserved and 0b100- is for svshape2
170 (SVxd
, SVyd
, SVzd
, SVrm
, vf
) = fields
175 # check SVrm for reserved (and svshape2) values
176 assert SVrm
not in [0b0111, 0b1000, 0b1001], \
177 "svshape reserved SVrm value %s" % bin(SVrm
)
191 def svshape2(fields
):
193 svshape2 is a *32-bit-only* instruction. It updates SVSHAPE and SVSTATE.
194 It is *not* a 64-bit-prefixed Vector instruction (no sv.svshape2, yet),
195 it is a Vector *control* instruction, and is a sort-of hybrid of
196 svshape and svindex, with the key important feature being the "offset".
198 https://libre-soc.org/openpower/sv/remap/discussion
200 * svshape2 offs,yx,rmm,SVd,sk,mm
202 # 1.6.35.1 SVM2-FORM from fields.txt
203 # |0 |6 |10|11 |16 |21 |24|25 |26 |31 |
204 # | PO | offs |yx| rmm | SVd |XO |mm|sk | XO |
206 note that this fits into the space of svshape and that XO is
207 split across 2 areas.
212 XO2
= 0b100 # not really XO2 but hey
213 (offs
, yx
, rmm
, SVd
, sk
, mm
) = fields
214 SVd
-= 1 # offset by one
218 (offs
, 6, 9), # offset (the whole point of adding svshape2)
219 (yx
, 10, 10), # like svindex
220 (rmm
, 11, 15), # ditto svindex
221 (SVd
, 16, 20), # ditto svindex
222 (XO2
, 21, 23), # actually XO split across 2 places...
223 (mm
, 24, 24), # ditto svindex
224 (sk
, 25, 25), # ditto svindex
232 svindex is a *32-bit-only* instruction. It is a convenience
233 instruction that reduces instruction count for Indexed REMAP
235 It is *not* a 64-bit-prefixed Vector instruction (no sv.svindex, yet),
236 it is a Vector *control* instruction.
239 |0 |6 |11 |16 |21 |23|24|25|26 31|
240 | PO | SVG|rmm | SVd |ew |yx|mm|sk| XO |
242 # note that the dimension field one subtracted
245 (SVG
, rmm
, SVd
, ew
, yx
, mm
, sk
) = fields
263 this is a *32-bit-only* instruction. It updates the SVSHAPE SPR
264 it is *not* a 64-bit-prefixed Vector instruction (no sv.svremap),
265 it is a Vector *control* instruction.
267 * svremap SVme,mi0,mi1,mi2,mo0,mo1,pst
270 |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 |
271 | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO |
276 (SVme
, mi0
, mi1
, mi2
, mo0
, mo1
, pst
) = fields
291 # ok from here-on down these are added as 32-bit instructions
292 # and are here only because binutils (at present) doesn't have
293 # them (that's being fixed!)
294 # they can - if implementations then choose - be Vectorised
295 # because they are general-purpose scalar instructions
300 |0 |6 |11 |16 |21 |26 |27 31|
301 | PO | RT | RA | RB |bm |L | XO |
305 (RT
, RA
, RB
, bm
, L
) = fields
318 _insn("fsins", Rc
=0),
319 _insn("fsins.", Rc
=1),
321 def fsins(fields
, Rc
):
322 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
323 # however we are out of space with opcode 22
325 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
326 # | PO | FRT | /// | FRB | XO |Rc |
341 _insn("fcoss", Rc
=0),
342 _insn("fcoss.", Rc
=1),
344 def fcoss(fields
, Rc
):
345 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
346 # however we are out of space with opcode 22
348 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
349 # | PO | FRT | /// | FRB | XO |Rc |
364 _insn("ternlogi", Rc
=0),
365 _insn("ternlogi.", Rc
=1),
367 def ternlogi(fields
, Rc
):
368 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
369 # however we are out of space with opcode 22
371 # |0 |6 |11 |16 |21 |29 |31 |
372 # | PO | RT | RA | RB | TLI | XO |Rc |
375 (RT
, RA
, RB
, TLI
) = fields
388 _insn("grev", Rc
=0, imm
=0, word
=0),
389 _insn("grevw", Rc
=0, imm
=0, word
=1),
390 _insn("grevi", Rc
=0, imm
=1, word
=0),
391 _insn("grevwi", Rc
=0, imm
=1, word
=1),
392 _insn("grev.", Rc
=1, imm
=0, word
=0),
393 _insn("grevw.", Rc
=1, imm
=0, word
=1),
394 _insn("grevi.", Rc
=1, imm
=1, word
=0),
395 _insn("grevwi.", Rc
=1, imm
=1, word
=1),
397 def grev(fields
, Rc
, imm
, word
):
398 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
399 # however we are out of space with opcode 22
401 # _ matches fields in table at:
402 # https://libre-soc.org/openpower/sv/bitmanip/
408 (RT
, RA
, XBI
) = fields
409 insn
= (insn
<< 5) | RT
410 insn
= (insn
<< 5) | RA
413 insn
= (insn
<< 6) | XBI
414 insn
= (insn
<< 9) | XO
417 insn
= (insn
<< 5) | XBI
418 insn
= (insn
<< 10) | XO
419 insn
= (insn
<< 1) | Rc
424 _insn("maxs", XO
=0b0111001110, Rc
=0),
425 _insn("maxs.", XO
=0b0111001110, Rc
=1),
426 _insn("maxu", XO
=0b0011001110, Rc
=0),
427 _insn("maxu.", XO
=0b0011001110, Rc
=1),
428 _insn("minu", XO
=0b0001001110, Rc
=0),
429 _insn("minu.", XO
=0b0001001110, Rc
=1),
430 _insn("mins", XO
=0b0101001110, Rc
=0),
431 _insn("mins.", XO
=0b0101001110, Rc
=1),
432 _insn("absdu", XO
=0b1011110110, Rc
=0),
433 _insn("absdu.", XO
=0b1011110110, Rc
=1),
434 _insn("absds", XO
=0b1001110110, Rc
=0),
435 _insn("absds.", XO
=0b1001110110, Rc
=1),
436 _insn("avgadd", XO
=0b1101001110, Rc
=0),
437 _insn("avgadd.", XO
=0b1101001110, Rc
=1),
438 _insn("absdacu", XO
=0b1111110110, Rc
=0),
439 _insn("absdacu.", XO
=0b1111110110, Rc
=1),
440 _insn("absdacs", XO
=0b0111110110, Rc
=0),
441 _insn("absdacs.", XO
=0b0111110110, Rc
=1),
442 _insn("cprop", XO
=0b0110001110, Rc
=0),
443 _insn("cprop.", XO
=0b0110001110, Rc
=1),
445 def av(fields
, XO
, Rc
):
447 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |20|21 |31 |
448 # | PO | RT | RA | RB | XO |Rc |
450 (RT
, RA
, RB
) = fields
463 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
464 # V3.0B 1.6.6 DX-FORM
465 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |26|27 |31 |
466 # | PO | FRS | d1 | d0 | XO |d2 |
470 # first split imm into d1, d0 and d2. sigh
471 d2
= (imm
& 1) # LSB (0)
472 d1
= (imm
>> 1) & 0b11111 # bits 1-5
473 d0
= (imm
>> 6) # MSBs 6-15
486 # XXX WARNING THESE ARE NOT APPROVED BY OPF ISA WG
487 # V3.0B 1.6.6 DX-FORM
488 # |0 |6 |7|8|9 |10 |11|12|13 |15|16|17 |26|27 |31 |
489 # | PO | FRS | d1 | d0 | XO |d2 |
493 # first split imm into d1, d0 and d2. sigh
494 d2
= (imm
& 1) # LSB (0)
495 d1
= (imm
>> 1) & 0b11111 # bits 1-5
496 d0
= (imm
>> 6) # MSBs 6-15
507 # decode GPR into sv extra
508 def get_extra_gpr(etype
, regmode
, field
):
509 if regmode
== 'scalar':
510 # cut into 2-bits 5-bits SS FFFFF
511 sv_extra
= field
>> 5
512 field
= field
& 0b11111
514 # cut into 5-bits 2-bits FFFFF SS
515 sv_extra
= field
& 0b11
517 return sv_extra
, field
520 # decode 3-bit CR into sv extra
521 def get_extra_cr_3bit(etype
, regmode
, field
):
522 if regmode
== 'scalar':
523 # cut into 2-bits 3-bits SS FFF
524 sv_extra
= field
>> 3
525 field
= field
& 0b111
527 # cut into 3-bits 4-bits FFF SSSS but will cut 2 zeros off later
528 sv_extra
= field
& 0b1111
530 return sv_extra
, field
534 def decode_subvl(encoding
):
535 pmap
= {'2': 0b01, '3': 0b10, '4': 0b11}
536 assert encoding
in pmap
, \
537 "encoding %s for SUBVL not recognised" % encoding
538 return pmap
[encoding
]
542 def decode_elwidth(encoding
):
543 pmap
= {'8': 0b11, '16': 0b10, '32': 0b01}
544 assert encoding
in pmap
, \
545 "encoding %s for elwidth not recognised" % encoding
546 return pmap
[encoding
]
549 # decodes predicate register encoding
550 def decode_predicate(encoding
):
561 'nl': (1, 0b001), 'ge': (1, 0b001), # same value
563 'ng': (1, 0b011), 'le': (1, 0b011), # same value
566 'so': (1, 0b110), 'un': (1, 0b110), # same value
567 'ns': (1, 0b111), 'nu': (1, 0b111), # same value
569 assert encoding
in pmap
, \
570 "encoding %s for predicate not recognised" % encoding
571 return pmap
[encoding
]
574 # decodes "Mode" in similar way to BO field (supposed to, anyway)
575 def decode_bo(encoding
):
576 pmap
= { # TODO: double-check that these are the same as Branch BO
578 'nl': 0b001, 'ge': 0b001, # same value
580 'ng': 0b011, 'le': 0b011, # same value
583 'so': 0b110, 'un': 0b110, # same value
584 'ns': 0b111, 'nu': 0b111, # same value
586 assert encoding
in pmap
, \
587 "encoding %s for BO Mode not recognised" % encoding
588 return pmap
[encoding
]
591 # partial-decode fail-first mode
592 def decode_ffirst(encoding
):
593 if encoding
in ['RC1', '~RC1']:
595 return decode_bo(encoding
)
598 def decode_reg(field
, macros
=None):
601 # decode the field number. "5.v" or "3.s" or "9"
602 # and now also "*0", and "*%0". note: *NOT* to add "*%rNNN" etc.
603 # https://bugs.libre-soc.org/show_bug.cgi?id=884#c0
604 if field
.startswith(("*%", "*")):
605 if field
.startswith("*%"):
609 while field
in macros
:
610 field
= macros
[field
]
611 return int(field
), "vector" # actual register number
613 # try old convention (to be retired)
614 field
= field
.split(".")
615 regmode
= 'scalar' # default
619 elif field
[1] == 'v':
621 field
= int(field
[0]) # actual register number
622 return field
, regmode
625 def decode_imm(field
):
626 ldst_imm
= "(" in field
and field
[-1] == ')'
628 return field
[:-1].split("(")
633 def crf_extra(etype
, regmode
, field
, extras
):
634 """takes a CR Field number (CR0-CR127), splits into EXTRA2/3 and v3.0
635 the scalar/vector mode (crNN.v or crNN.s) changes both the format
636 of the EXTRA2/3 encoding as well as what range of registers is possible.
637 this function can be used for both BF/BFA and BA/BB/BT by first removing
638 the bottom 2 bits of BA/BB/BT then re-instating them after encoding.
639 see https://libre-soc.org/openpower/sv/svp64/appendix/#cr_extra
642 sv_extra
, field
= get_extra_cr_3bit(etype
, regmode
, field
)
643 # now sanity-check (and shrink afterwards)
644 if etype
== 'EXTRA2':
645 # 3-bit CR Field (BF, BFA) EXTRA2 encoding
646 if regmode
== 'scalar':
647 # range is CR0-CR15 in increments of 1
648 assert (sv_extra
>> 1) == 0, \
649 "scalar CR %s cannot fit into EXTRA2 %s" % \
650 (rname
, str(extras
[extra_idx
]))
651 # all good: encode as scalar
652 sv_extra
= sv_extra
& 0b01
654 # range is CR0-CR127 in increments of 16
655 assert sv_extra
& 0b111 == 0, \
656 "vector CR %s cannot fit into EXTRA2 %s" % \
657 (rname
, str(extras
[extra_idx
]))
658 # all good: encode as vector (bit 2 set)
659 sv_extra
= 0b10 |
(sv_extra
>> 3)
661 # 3-bit CR Field (BF, BFA) EXTRA3 encoding
662 if regmode
== 'scalar':
663 # range is CR0-CR31 in increments of 1
664 assert (sv_extra
>> 2) == 0, \
665 "scalar CR %s cannot fit into EXTRA3 %s" % \
666 (rname
, str(extras
[extra_idx
]))
667 # all good: encode as scalar
668 sv_extra
= sv_extra
& 0b11
670 # range is CR0-CR127 in increments of 8
671 assert sv_extra
& 0b11 == 0, \
672 "vector CR %s cannot fit into EXTRA3 %s" % \
673 (rname
, str(extras
[extra_idx
]))
674 # all good: encode as vector (bit 3 set)
675 sv_extra
= 0b100 |
(sv_extra
>> 2)
676 return sv_extra
, field
679 def to_number(field
):
680 if field
.startswith("0x"):
682 if field
.startswith("0b"):
687 # decodes svp64 assembly listings and creates EXT001 svp64 prefixes
689 def __init__(self
, lst
, bigendian
=False, macros
=None):
694 self
.trans
= self
.translate(lst
)
695 self
.isa
= ISA() # reads the v3.0B pseudo-code markdown files
696 self
.svp64
= SVP64RM() # reads the svp64 Remap entries for registers
697 assert bigendian
== False, "error, bigendian not supported yet"
700 yield from self
.trans
702 def translate_one(self
, insn
, macros
=None):
705 macros
.update(self
.macros
)
708 insn_no_comments
= insn
.partition('#')[0]
709 # find first space, to get opcode
710 ls
= insn_no_comments
.split(' ')
712 # now find opcode fields
713 fields
= ''.join(ls
[1:]).split(',')
714 mfields
= list(map(str.strip
, fields
))
715 log("opcode, fields", ls
, opcode
, mfields
)
718 for field
in mfields
:
719 fields
.append(macro_subst(macros
, field
))
720 log("opcode, fields substed", ls
, opcode
, fields
)
722 # identify if it is a special instruction
723 custom_insn_hook
= CUSTOM_INSNS
.get(opcode
)
724 if custom_insn_hook
is not None:
725 fields
= tuple(map(to_number
, fields
))
726 insn_num
= custom_insn_hook(fields
)
727 log(opcode
, bin(insn_num
))
728 yield ".long 0x%X # %s" % (insn_num
, insn
)
731 # identify if is a svp64 mnemonic
732 if not opcode
.startswith('sv.'):
733 yield insn
# unaltered
735 opcode
= opcode
[3:] # strip leading "sv"
737 # start working on decoding the svp64 op: sv.basev30Bop/vec2/mode
738 opmodes
= opcode
.split("/") # split at "/"
739 v30b_op_orig
= opmodes
.pop(0) # first is the v3.0B
740 # check instruction ends with dot
741 rc_mode
= v30b_op_orig
.endswith('.')
743 v30b_op
= v30b_op_orig
[:-1]
745 v30b_op
= v30b_op_orig
747 # look up the 32-bit op (original, with "." if it has it)
748 if v30b_op_orig
in isa
.instr
:
749 isa_instr
= isa
.instr
[v30b_op_orig
]
751 raise Exception("opcode %s of '%s' not supported" %
752 (v30b_op_orig
, insn
))
754 # look up the svp64 op, first the original (with "." if it has it)
755 if v30b_op_orig
in svp64
.instrs
:
756 rm
= svp64
.instrs
[v30b_op_orig
] # one row of the svp64 RM CSV
757 # then without the "." (if there was one)
758 elif v30b_op
in svp64
.instrs
:
759 rm
= svp64
.instrs
[v30b_op
] # one row of the svp64 RM CSV
761 raise Exception(f
"opcode {v30b_op_orig!r} of "
762 f
"{insn!r} not an svp64 instruction")
764 # get regs info e.g. "RT,RA,RB"
765 v30b_regs
= isa_instr
.regs
[0]
766 log("v3.0B op", v30b_op
, "Rc=1" if rc_mode
else '')
767 log("v3.0B regs", opcode
, v30b_regs
)
770 # right. the first thing to do is identify the ordering of
771 # the registers, by name. the EXTRA2/3 ordering is in
772 # rm['0']..rm['3'] but those fields contain the names RA, BB
773 # etc. we have to read the pseudocode to understand which
774 # reg is which in our instruction. sigh.
776 # first turn the svp64 rm into a "by name" dict, recording
777 # which position in the RM EXTRA it goes into
778 # also: record if the src or dest was a CR, for sanity-checking
779 # (elwidth overrides on CRs are banned)
780 decode
= decode_extra(rm
)
781 dest_reg_cr
, src_reg_cr
, svp64_src
, svp64_dest
= decode
783 log("EXTRA field index, src", svp64_src
)
784 log("EXTRA field index, dest", svp64_dest
)
786 # okaaay now we identify the field value (opcode N,N,N) with
787 # the pseudo-code info (opcode RT, RA, RB)
788 assert len(fields
) == len(v30b_regs
), \
789 "length of fields %s must match insn `%s` fields %s" % \
790 (str(v30b_regs
), insn
, str(fields
))
791 opregfields
= zip(fields
, v30b_regs
) # err that was easy
793 # now for each of those find its place in the EXTRA encoding
794 # note there is the possibility (for LD/ST-with-update) of
795 # RA occurring **TWICE**. to avoid it getting added to the
796 # v3.0B suffix twice, we spot it as a duplicate, here
797 extras
= OrderedDict()
798 for idx
, (field
, regname
) in enumerate(opregfields
):
799 imm
, regname
= decode_imm(regname
)
800 rtype
= get_regtype(regname
)
801 log(" idx find", rtype
, idx
, field
, regname
, imm
)
803 # probably an immediate field, append it straight
804 extras
[('imm', idx
, False)] = (idx
, field
, None, None, None)
806 extra
= svp64_src
.get(regname
, None)
807 if extra
is not None:
808 extra
= ('s', extra
, False) # not a duplicate
809 extras
[extra
] = (idx
, field
, regname
, rtype
, imm
)
810 log(" idx src", idx
, extra
, extras
[extra
])
811 dextra
= svp64_dest
.get(regname
, None)
812 log("regname in", regname
, dextra
)
813 if dextra
is not None:
814 is_a_duplicate
= extra
is not None # duplicate spotted
815 dextra
= ('d', dextra
, is_a_duplicate
)
816 extras
[dextra
] = (idx
, field
, regname
, rtype
, imm
)
817 log(" idx dst", idx
, extra
, extras
[dextra
])
819 # great! got the extra fields in their associated positions:
820 # also we know the register type. now to create the EXTRA encodings
821 etype
= rm
['Etype'] # Extra type: EXTRA3/EXTRA2
822 ptype
= rm
['Ptype'] # Predication type: Twin / Single
825 for extra_idx
, (idx
, field
, rname
, rtype
, iname
) in extras
.items():
826 # is it a field we don't alter/examine? if so just put it
829 v30b_newfields
.append(field
)
832 # identify if this is a ld/st immediate(reg) thing
833 ldst_imm
= "(" in field
and field
[-1] == ')'
835 immed
, field
= field
[:-1].split("(")
837 field
, regmode
= decode_reg(field
, macros
=macros
)
838 log(" ", extra_idx
, rname
, rtype
,
839 regmode
, iname
, field
, end
=" ")
841 # see Mode field https://libre-soc.org/openpower/sv/svp64/
842 # XXX TODO: the following is a bit of a laborious repeated
843 # mess, which could (and should) easily be parameterised.
844 # XXX also TODO: the LD/ST modes which are different
845 # https://libre-soc.org/openpower/sv/ldst/
847 # rright. SVP64 register numbering is from 0 to 127
848 # for GPRs, FPRs *and* CR Fields, where for v3.0 the GPRs and RPFs
849 # are 0-31 and CR Fields are only 0-7. the SVP64 RM "Extra"
850 # area is used to extend the numbering from the 32-bit
851 # instruction, and also to record whether the register
852 # is scalar or vector. on a per-operand basis. this
853 # results in a slightly finnicky encoding: here we go...
855 # encode SV-GPR and SV-FPR field into extra, v3.0field
856 if rtype
in ['GPR', 'FPR']:
857 sv_extra
, field
= get_extra_gpr(etype
, regmode
, field
)
858 # now sanity-check. EXTRA3 is ok, EXTRA2 has limits
859 # (and shrink to a single bit if ok)
860 if etype
== 'EXTRA2':
861 if regmode
== 'scalar':
862 # range is r0-r63 in increments of 1
863 assert (sv_extra
>> 1) == 0, \
864 "scalar GPR %s cannot fit into EXTRA2 %s" % \
865 (rname
, str(extras
[extra_idx
]))
866 # all good: encode as scalar
867 sv_extra
= sv_extra
& 0b01
869 # range is r0-r127 in increments of 2 (r0 r2 ... r126)
870 assert sv_extra
& 0b01 == 0, \
871 "%s: vector field %s cannot fit " \
873 (insn
, rname
, str(extras
[extra_idx
]))
874 # all good: encode as vector (bit 2 set)
875 sv_extra
= 0b10 |
(sv_extra
>> 1)
876 elif regmode
== 'vector':
877 # EXTRA3 vector bit needs marking
880 # encode SV-CR 3-bit field into extra, v3.0field.
881 # 3-bit is for things like BF and BFA
882 elif rtype
== 'CR_3bit':
883 sv_extra
, field
= crf_extra(etype
, regmode
, field
, extras
)
885 # encode SV-CR 5-bit field into extra, v3.0field
886 # 5-bit is for things like BA BB BC BT etc.
887 # *sigh* this is the same as 3-bit except the 2 LSBs of the
888 # 5-bit field are passed through unaltered.
889 elif rtype
== 'CR_5bit':
890 cr_subfield
= field
& 0b11 # record bottom 2 bits for later
891 field
= field
>> 2 # strip bottom 2 bits
892 # use the exact same 3-bit function for the top 3 bits
893 sv_extra
, field
= crf_extra(etype
, regmode
, field
, extras
)
894 # reconstruct the actual 5-bit CR field (preserving the
895 # bottom 2 bits, unaltered)
896 field
= (field
<< 2) | cr_subfield
899 raise Exception("no type match: %s" % rtype
)
901 # capture the extra field info
902 log("=>", "%5s" % bin(sv_extra
), field
)
903 extras
[extra_idx
] = sv_extra
905 # append altered field value to v3.0b, differs for LDST
906 # note that duplicates are skipped e.g. EXTRA2 contains
907 # *BOTH* s:RA *AND* d:RA which happens on LD/ST-with-update
908 srcdest
, idx
, duplicate
= extra_idx
909 if duplicate
: # skip adding to v3.0b fields, already added
912 v30b_newfields
.append(("%s(%s)" % (immed
, str(field
))))
914 v30b_newfields
.append(str(field
))
916 log("new v3.0B fields", v30b_op
, v30b_newfields
)
917 log("extras", extras
)
919 # rright. now we have all the info. start creating SVP64 instruction.
920 db
= Database(find_wiki_dir())
921 svp64_insn
= SVP64Instruction
.pair(prefix
=0, suffix
=0)
922 svp64_prefix
= svp64_insn
.prefix
923 svp64_rm
= svp64_insn
.prefix
.rm
925 # begin with EXTRA fields
926 for idx
, sv_extra
in extras
.items():
932 srcdest
, idx
, duplicate
= idx
933 if etype
== 'EXTRA2':
934 svp64_rm
.extra2
[idx
] = sv_extra
936 svp64_rm
.extra3
[idx
] = sv_extra
938 # identify if the op is a LD/ST. the "blegh" way. copied
939 # from power_enums. TODO, split the list _insns down.
941 "lbarx", "lbz", "lbzu", "lbzux", "lbzx", # load byte
942 "ld", "ldarx", "ldbrx", "ldu", "ldux", "ldx", # load double
943 "lfs", "lfsx", "lfsu", "lfsux", # FP load single
944 "lfd", "lfdx", "lfdu", "lfdux", "lfiwzx", "lfiwax", # FP load dbl
945 "lha", "lharx", "lhau", "lhaux", "lhax", # load half
946 "lhbrx", "lhz", "lhzu", "lhzux", "lhzx", # more load half
947 "lwa", "lwarx", "lwaux", "lwax", "lwbrx", # load word
948 "lwz", "lwzcix", "lwzu", "lwzux", "lwzx", # more load word
951 "stb", "stbcix", "stbcx", "stbu", "stbux", "stbx",
952 "std", "stdbrx", "stdcx", "stdu", "stdux", "stdx",
953 "stfs", "stfsx", "stfsu", "stfux", # FP store sgl
954 "stfd", "stfdx", "stfdu", "stfdux", "stfiwx", # FP store dbl
955 "sth", "sthbrx", "sthcx", "sthu", "sthux", "sthx",
956 "stw", "stwbrx", "stwcx", "stwu", "stwux", "stwx",
958 # use this to determine if the SVP64 RM format is different.
959 # see https://libre-soc.org/openpower/sv/ldst/
960 is_ldst
= is_ld
or is_st
962 # branch-conditional detection
970 destwid
= 0 # bits 4-5
971 srcwid
= 0 # bits 6-7
973 smask
= 0 # bits 16-18 but only for twin-predication
974 mode
= 0 # bits 19-23
976 mask_m_specified
= False
987 mapreduce_crm
= False
988 mapreduce_svm
= False
994 # branch-conditional bits
1004 # ok let's start identifying opcode augmentation fields
1005 for encmode
in opmodes
:
1006 # predicate mask (src and dest)
1007 if encmode
.startswith("m="):
1009 pmmode
, pmask
= decode_predicate(encmode
[2:])
1010 smmode
, smask
= pmmode
, pmask
1012 mask_m_specified
= True
1013 # predicate mask (dest)
1014 elif encmode
.startswith("dm="):
1016 pmmode
, pmask
= decode_predicate(encmode
[3:])
1019 # predicate mask (src, twin-pred)
1020 elif encmode
.startswith("sm="):
1022 smmode
, smask
= decode_predicate(encmode
[3:])
1026 elif encmode
.startswith("vec"):
1027 subvl
= decode_subvl(encmode
[3:])
1029 elif encmode
.startswith("ew="):
1030 destwid
= decode_elwidth(encmode
[3:])
1031 elif encmode
.startswith("sw="):
1032 srcwid
= decode_elwidth(encmode
[3:])
1033 # element-strided LD/ST
1034 elif encmode
== 'els':
1037 elif encmode
== 'sats':
1038 assert sv_mode
is None
1041 elif encmode
== 'satu':
1042 assert sv_mode
is None
1046 elif encmode
== 'sz':
1048 elif encmode
== 'dz':
1051 elif encmode
.startswith("ff="):
1052 assert sv_mode
is None
1054 failfirst
= decode_ffirst(encmode
[3:])
1055 # predicate-result, interestingly same as fail-first
1056 elif encmode
.startswith("pr="):
1057 assert sv_mode
is None
1059 predresult
= decode_ffirst(encmode
[3:])
1060 # map-reduce mode, reverse-gear
1061 elif encmode
== 'mrr':
1062 assert sv_mode
is None
1067 elif encmode
== 'mr':
1068 assert sv_mode
is None
1071 elif encmode
== 'crm': # CR on map-reduce
1072 assert sv_mode
is None
1074 mapreduce_crm
= True
1075 elif encmode
== 'svm': # sub-vector mode
1076 mapreduce_svm
= True
1078 if encmode
== 'all':
1080 elif encmode
== 'st': # svstep mode
1082 elif encmode
== 'sr': # svstep BRc mode
1085 elif encmode
== 'vs': # VLSET mode
1087 elif encmode
== 'vsi': # VLSET mode with VLI (VL inclusives)
1090 elif encmode
== 'vsb': # VLSET mode with VSb
1093 elif encmode
== 'vsbi': # VLSET mode with VLI and VSb
1097 elif encmode
== 'snz': # sz (only) already set above
1100 elif encmode
== 'lu': # LR update mode
1103 raise AssertionError("unknown encmode %s" % encmode
)
1105 raise AssertionError("unknown encmode %s" % encmode
)
1108 # since m=xx takes precedence (overrides) sm=xx and dm=xx,
1109 # treat them as mutually exclusive
1110 if mask_m_specified
:
1111 assert not has_smask
,\
1112 "cannot have both source-mask and predicate mask"
1113 assert not has_pmask
,\
1114 "cannot have both dest-mask and predicate mask"
1115 # since the default is INT predication (ALWAYS), if you
1116 # specify one CR mask, you must specify both, to avoid
1117 # mixing INT and CR reg types
1118 if has_pmask
and pmmode
== 1:
1120 "need explicit source-mask in CR twin predication"
1121 if has_smask
and smmode
== 1:
1123 "need explicit dest-mask in CR twin predication"
1124 # sanity-check that 2Pred mask is same mode
1125 if has_pmask
and has_smask
:
1126 assert smmode
== pmmode
, \
1127 "predicate masks %s and %s must be same reg type" % \
1130 # sanity-check that twin-predication mask only specified in 2P mode
1132 assert not has_smask
, \
1133 "source-mask can only be specified on Twin-predicate ops"
1134 assert not has_pmask
, \
1135 "dest-mask can only be specified on Twin-predicate ops"
1137 # construct the mode field, doing sanity-checking along the way
1139 assert sv_mode
== 0b00, "sub-vector mode in mapreduce only"
1140 assert subvl
!= 0, "sub-vector mode not possible on SUBVL=1"
1143 assert has_smask
or mask_m_specified
, \
1144 "src zeroing requires a source predicate"
1146 assert has_pmask
or mask_m_specified
, \
1147 "dest zeroing requires a dest predicate"
1149 # okaaay, so there are 4 different modes, here, which will be
1150 # partly-merged-in: is_ldst is merged in with "normal", but
1151 # is_bc is so different it's done separately. likewise is_cr
1152 # (when it is done). here are the maps:
1154 # for "normal" arithmetic: https://libre-soc.org/openpower/sv/normal/
1156 | 0-1 | 2 | 3 4 | description |
1157 | --- | --- |---------|-------------------------- |
1158 | 00 | 0 | dz sz | normal mode |
1159 | 00 | 1 | 0 RG | scalar reduce mode (mapreduce), SUBVL=1 |
1160 | 00 | 1 | 1 / | parallel reduce mode (mapreduce), SUBVL=1 |
1161 | 00 | 1 | SVM RG | subvector reduce mode, SUBVL>1 |
1162 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
1163 | 01 | inv | VLi RC1 | Rc=0: ffirst z/nonz |
1164 | 10 | N | dz sz | sat mode: N=0/1 u/s |
1165 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1166 | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
1169 # https://libre-soc.org/openpower/sv/ldst/
1170 # for LD/ST-immediate:
1172 | 0-1 | 2 | 3 4 | description |
1173 | --- | --- |---------|--------------------------- |
1174 | 00 | 0 | dz els | normal mode |
1175 | 00 | 1 | dz shf | shift mode |
1176 | 01 | inv | CR-bit | Rc=1: ffirst CR sel |
1177 | 01 | inv | els RC1 | Rc=0: ffirst z/nonz |
1178 | 10 | N | dz els | sat mode: N=0/1 u/s |
1179 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1180 | 11 | inv | els RC1 | Rc=0: pred-result z/nonz |
1183 # for LD/ST-indexed (RA+RB):
1185 | 0-1 | 2 | 3 4 | description |
1186 | --- | --- |---------|-------------------------- |
1187 | 00 | SEA | dz sz | normal mode |
1188 | 01 | SEA | dz sz | Strided (scalar only source) |
1189 | 10 | N | dz sz | sat mode: N=0/1 u/s |
1190 | 11 | inv | CR-bit | Rc=1: pred-result CR sel |
1191 | 11 | inv | dz RC1 | Rc=0: pred-result z/nonz |
1194 # and leaving out branches and cr_ops for now because they're
1196 """ TODO branches and cr_ops
1199 # now create mode and (overridden) src/dst widths
1200 # XXX TODO: sanity-check bc modes
1202 sv_mode
= ((bc_svstep
<< SVP64MODE
.MOD2_MSB
) |
1203 (bc_vlset
<< SVP64MODE
.MOD2_LSB
) |
1204 (bc_snz
<< SVP64MODE
.BC_SNZ
))
1205 srcwid
= (bc_vsb
<< 1) | bc_lru
1206 destwid
= (bc_lru
<< 1) | bc_all
1210 ######################################
1213 mode |
= src_zero
<< SVP64MODE
.SZ
# predicate zeroing
1214 mode |
= dst_zero
<< SVP64MODE
.DZ
# predicate zeroing
1216 # TODO: for now, LD/ST-indexed is ignored.
1217 mode |
= ldst_elstride
<< SVP64MODE
.ELS_NORMAL
# el-strided
1219 # TODO, reduce and subvector mode
1220 # 00 1 dz CRM reduce mode (mapreduce), SUBVL=1
1221 # 00 1 SVM CRM subvector reduce mode, SUBVL>1
1225 ######################################
1227 elif sv_mode
== 0b00:
1228 mode |
= (0b1 << SVP64MODE
.REDUCE
) # sets mapreduce
1229 assert dst_zero
== 0, "dest-zero not allowed in mapreduce mode"
1231 mode |
= (0b1 << SVP64MODE
.RG
) # sets Reverse-gear mode
1233 mode |
= (0b1 << SVP64MODE
.CRM
) # sets CRM mode
1234 assert rc_mode
, "CRM only allowed when Rc=1"
1235 # bit of weird encoding to jam zero-pred or SVM mode in.
1236 # SVM mode can be enabled only when SUBVL=2/3/4 (vec2/3/4)
1238 mode |
= dst_zero
<< SVP64MODE
.DZ
# predicate zeroing
1240 mode |
= (0b1 << SVP64MODE
.SVM
) # sets SVM mode
1242 ######################################
1244 elif sv_mode
== 0b01:
1245 assert src_zero
== 0, "dest-zero not allowed in failfirst mode"
1246 if failfirst
== 'RC1':
1247 mode |
= (0b1 << SVP64MODE
.RC1
) # sets RC1 mode
1248 mode |
= (dst_zero
<< SVP64MODE
.DZ
) # predicate dst-zeroing
1249 assert rc_mode
== False, "ffirst RC1 only ok when Rc=0"
1250 elif failfirst
== '~RC1':
1251 mode |
= (0b1 << SVP64MODE
.RC1
) # sets RC1 mode
1252 mode |
= (dst_zero
<< SVP64MODE
.DZ
) # predicate dst-zeroing
1253 mode |
= (0b1 << SVP64MODE
.INV
) # ... with inversion
1254 assert rc_mode
== False, "ffirst RC1 only ok when Rc=0"
1256 assert dst_zero
== 0, "dst-zero not allowed in ffirst BO"
1257 assert rc_mode
, "ffirst BO only possible when Rc=1"
1258 mode |
= (failfirst
<< SVP64MODE
.BO_LSB
) # set BO
1260 ######################################
1261 # "saturation" modes
1262 elif sv_mode
== 0b10:
1263 mode |
= src_zero
<< SVP64MODE
.SZ
# predicate zeroing
1264 mode |
= dst_zero
<< SVP64MODE
.DZ
# predicate zeroing
1265 mode |
= (saturation
<< SVP64MODE
.N
) # signed/us saturation
1267 ######################################
1268 # "predicate-result" modes. err... code-duplication from ffirst
1269 elif sv_mode
== 0b11:
1270 assert src_zero
== 0, "dest-zero not allowed in predresult mode"
1271 if predresult
== 'RC1':
1272 mode |
= (0b1 << SVP64MODE
.RC1
) # sets RC1 mode
1273 mode |
= (dst_zero
<< SVP64MODE
.DZ
) # predicate dst-zeroing
1274 assert rc_mode
== False, "pr-mode RC1 only ok when Rc=0"
1275 elif predresult
== '~RC1':
1276 mode |
= (0b1 << SVP64MODE
.RC1
) # sets RC1 mode
1277 mode |
= (dst_zero
<< SVP64MODE
.DZ
) # predicate dst-zeroing
1278 mode |
= (0b1 << SVP64MODE
.INV
) # ... with inversion
1279 assert rc_mode
== False, "pr-mode RC1 only ok when Rc=0"
1281 assert dst_zero
== 0, "dst-zero not allowed in pr-mode BO"
1282 assert rc_mode
, "pr-mode BO only possible when Rc=1"
1283 mode |
= (predresult
<< SVP64MODE
.BO_LSB
) # set BO
1285 # whewww.... modes all done :)
1286 # now put into svp64_rm
1289 svp64_rm
.mode
= mode
1291 # put in predicate masks into svp64_rm
1293 # source pred: bits 16-18
1294 svp64_rm
.smask
= smask
1296 svp64_rm
.mmode
= mmode
1298 svp64_rm
.mask
= pmask
1300 # and subvl: bits 8-9
1301 svp64_rm
.subvl
= subvl
1305 svp64_rm
.ewsrc
= srcwid
1307 svp64_rm
.elwidth
= destwid
1309 # nice debug printout. (and now for something completely different)
1310 # https://youtu.be/u0WOIwlXE9g?t=146
1311 svp64_rm_value
= int(svp64_rm
)
1312 log("svp64_rm", hex(svp64_rm_value
), bin(svp64_rm_value
))
1313 log(" mmode 0 :", bin(mmode
))
1314 log(" pmask 1-3 :", bin(pmask
))
1315 log(" dstwid 4-5 :", bin(destwid
))
1316 log(" srcwid 6-7 :", bin(srcwid
))
1317 log(" subvl 8-9 :", bin(subvl
))
1318 log(" mode 19-23:", bin(mode
))
1319 offs
= 2 if etype
== 'EXTRA2' else 3 # 2 or 3 bits
1320 for idx
, sv_extra
in extras
.items():
1325 srcdest
, idx
, duplicate
= idx
1326 start
= (10+idx
*offs
)
1327 end
= start
+ offs
-1
1328 log(" extra%d %2d-%2d:" % (idx
, start
, end
),
1331 log(" smask 16-17:", bin(smask
))
1334 # update prefix PO and ID (aka PID)
1335 svp64_prefix
.po
= 0x1
1336 svp64_prefix
.id = 0b11
1338 # fiinally yield the svp64 prefix and the thingy. v3.0b opcode
1339 rc
= '.' if rc_mode
else ''
1340 yield ".long 0x%08x" % int(svp64_prefix
)
1341 log(v30b_op
, v30b_newfields
)
1343 v30b_op_rc
= v30b_op
1344 if not v30b_op
.endswith('.'):
1348 # FIXME(lkcl): should sv.svstep be like svstep?
1349 if v30b_op_rc
in ("svstep", "svstep."):
1350 # compensate for `SVi -= 1` in svstep()
1351 v30b_newfields
[1] = str(int(v30b_newfields
[1]) + 1)
1353 custom_insn_hook
= CUSTOM_INSNS
.get(v30b_op_rc
)
1354 if custom_insn_hook
is not None:
1355 fields
= tuple(map(to_number
, v30b_newfields
))
1356 insn_num
= custom_insn_hook(fields
)
1357 log(opcode
, bin(insn_num
))
1358 yield ".long 0x%X # %s" % (insn_num
, insn
)
1360 # argh, sv.fmadds etc. need to be done manually
1361 elif v30b_op
== 'ffmadds':
1362 opcode
= 59 << (32-6) # bits 0..6 (MSB0)
1363 opcode |
= int(v30b_newfields
[0]) << (32-11) # FRT
1364 opcode |
= int(v30b_newfields
[1]) << (32-16) # FRA
1365 opcode |
= int(v30b_newfields
[2]) << (32-21) # FRB
1366 opcode |
= int(v30b_newfields
[3]) << (32-26) # FRC
1367 opcode |
= 0b00101 << (32-31) # bits 26-30
1369 opcode |
= 1 # Rc, bit 31.
1370 yield ".long 0x%x" % opcode
1371 # argh, sv.fdmadds need to be done manually
1372 elif v30b_op
== 'fdmadds':
1373 opcode
= 59 << (32-6) # bits 0..6 (MSB0)
1374 opcode |
= int(v30b_newfields
[0]) << (32-11) # FRT
1375 opcode |
= int(v30b_newfields
[1]) << (32-16) # FRA
1376 opcode |
= int(v30b_newfields
[2]) << (32-21) # FRB
1377 opcode |
= int(v30b_newfields
[3]) << (32-26) # FRC
1378 opcode |
= 0b01111 << (32-31) # bits 26-30
1380 opcode |
= 1 # Rc, bit 31.
1381 yield ".long 0x%x" % opcode
1382 # argh, sv.ffadds etc. need to be done manually
1383 elif v30b_op
== 'ffadds':
1384 opcode
= 59 << (32-6) # bits 0..6 (MSB0)
1385 opcode |
= int(v30b_newfields
[0]) << (32-11) # FRT
1386 opcode |
= int(v30b_newfields
[1]) << (32-16) # FRA
1387 opcode |
= int(v30b_newfields
[2]) << (32-21) # FRB
1388 opcode |
= 0b01101 << (32-31) # bits 26-30
1390 opcode |
= 1 # Rc, bit 31.
1391 yield ".long 0x%x" % opcode
1393 if not v30b_op
.endswith('.'):
1395 yield "%s %s" % (v30b_op
, ", ".join(v30b_newfields
))
1396 log("new v3.0B fields", v30b_op
, v30b_newfields
)
1398 def translate(self
, lst
):
1400 yield from self
.translate_one(insn
)
1403 def macro_subst(macros
, txt
):
1405 log("subst", txt
, macros
)
1408 for macro
, value
in macros
.items():
1411 replaced
= txt
.replace(macro
, value
)
1412 log("macro", txt
, "replaced", replaced
, macro
, value
)
1415 toreplace
= '%s.s' % macro
1416 if toreplace
== txt
:
1418 replaced
= txt
.replace(toreplace
, "%s.s" % value
)
1419 log("macro", txt
, "replaced", replaced
, toreplace
, value
)
1422 toreplace
= '%s.v' % macro
1423 if toreplace
== txt
:
1425 replaced
= txt
.replace(toreplace
, "%s.v" % value
)
1426 log("macro", txt
, "replaced", replaced
, toreplace
, value
)
1429 toreplace
= '(%s)' % macro
1430 if toreplace
in txt
:
1432 replaced
= txt
.replace(toreplace
, '(%s)' % value
)
1433 log("macro", txt
, "replaced", replaced
, toreplace
, value
)
1436 log(" processed", txt
)
1444 if not line
[0].isspace():
1452 # get an input file and an output file
1456 outfile
= sys
.stdout
1457 # read the whole lot in advance in case of in-place
1458 lines
= list(infile
.readlines())
1459 elif len(args
) != 2:
1460 print("pysvp64asm [infile | -] [outfile | -]", file=sys
.stderr
)
1466 infile
= open(args
[0], "r")
1467 # read the whole lot in advance in case of in-place overwrite
1468 lines
= list(infile
.readlines())
1471 outfile
= sys
.stdout
1473 outfile
= open(args
[1], "w")
1475 # read the line, look for custom insn, process it
1476 macros
= {} # macros which start ".set"
1479 op
= line
.split("#")[0].strip()
1481 if op
.startswith(".set"):
1482 macro
= op
[4:].split(",")
1483 (macro
, value
) = map(str.strip
, macro
)
1484 macros
[macro
] = value
1485 if not op
.startswith('sv.') and not op
.startswith(tuple(CUSTOM_INSNS
)):
1489 (ws
, line
) = get_ws(line
)
1490 lst
= isa
.translate_one(op
, macros
)
1491 lst
= '; '.join(lst
)
1492 outfile
.write("%s%s # %s\n" % (ws
, lst
, op
))
1495 if __name__
== '__main__':
1496 lst
= ['slw 3, 1, 4',
1499 'sv.cmpi 5, 1, 3, 2',
1501 'sv.isel 64.v, 3, 2, 65.v',
1502 'sv.setb/dm=r3/sm=1<<r3 5, 31',
1503 'sv.setb/m=r3 5, 31',
1504 'sv.setb/vec2 5, 31',
1505 'sv.setb/sw=8/ew=16 5, 31',
1506 'sv.extsw./ff=eq 5, 31',
1507 'sv.extsw./satu/sz/dz/sm=r3/dm=r3 5, 31',
1508 'sv.extsw./pr=eq 5.v, 31',
1509 'sv.add. 5.v, 2.v, 1.v',
1510 'sv.add./m=r3 5.v, 2.v, 1.v',
1513 'sv.stw 5.v, 4(1.v)',
1514 'sv.ld 5.v, 4(1.v)',
1515 'setvl. 2, 3, 4, 0, 1, 1',
1516 'sv.setvl. 2, 3, 4, 0, 1, 1',
1519 "sv.stfsu 0.v, 16(4.v)",
1522 "sv.stfsu/els 0.v, 16(4)",
1525 'sv.add./mr 5.v, 2.v, 1.v',
1527 macros
= {'win2': '50', 'win': '60'}
1529 'sv.addi win2.v, win.v, -1',
1530 'sv.add./mrr 5.v, 2.v, 1.v',
1531 #'sv.lhzsh 5.v, 11(9.v), 15',
1532 #'sv.lwzsh 5.v, 11(9.v), 15',
1533 'sv.ffmadds 6.v, 2.v, 4.v, 6.v',
1536 #'sv.fmadds 0.v, 8.v, 16.v, 4.v',
1537 #'sv.ffadds 0.v, 8.v, 4.v',
1538 'svremap 11, 0, 1, 2, 3, 2, 1',
1539 'svshape 8, 1, 1, 1, 0',
1540 'svshape 8, 1, 1, 1, 1',
1543 #'sv.lfssh 4.v, 11(8.v), 15',
1544 #'sv.lwzsh 4.v, 11(8.v), 15',
1545 #'sv.svstep. 2.v, 4, 0',
1546 #'sv.fcfids. 48.v, 64.v',
1547 'sv.fcoss. 80.v, 0.v',
1548 'sv.fcoss. 20.v, 0.v',
1551 'sv.bc/all 3,12,192',
1552 'sv.bclr/vsbi 3,81.v,192',
1553 'sv.ld 5.v, 4(1.v)',
1554 'sv.svstep. 2.v, 4, 0',
1565 'svindex 0,0,1,0,0,0,0',
1568 'sv.svstep./m=r3 2.v, 4, 0',
1569 'ternlogi 0,0,0,0x5',
1581 'sv.andi. *80, *80, 1',
1582 'sv.ffmadds. 6.v, 2.v, 4.v, 6.v', # incorrectly inserted 32-bit op
1583 'sv.ffmadds 6.v, 2.v, 4.v, 6.v', # correctly converted to .long
1584 'svshape2 8, 1, 31, 7, 1, 1',
1586 isa
= SVP64Asm(lst
, macros
=macros
)
1587 log("list:\n", "\n\t".join(list(isa
)))
1588 # running svp64.py is designed to test hard-coded lists
1589 # (above) - which strictly speaking should all be unit tests.
1590 # if you need to actually do assembler translation at the
1591 # commandline use "pysvp64asm" - see setup.py
1592 # XXX NO. asm_process()