src/openpower/sv/trans/test_pysvp64dis.py

   1 from openpower.simulator.program import Program
   2 from openpower.sv.trans.pysvp64dis import load, dump
   3 from openpower.sv.trans.svp64 import SVP64Asm
   4 from openpower.decoder.power_insn import Database, Verbosity
   5 from openpower.decoder.power_enums import find_wiki_dir
   6 from openpower.sv import sv_binutils_fptrans
   7 import unittest
   8 import itertools
   9 import sys
  10
  11 class SVSTATETestCase(unittest.TestCase):
  12
  13     def _do_tst(self, expected):
  14         isa = SVP64Asm(expected)
  15         lst = list(isa)
  16         with Program(lst, bigendian=False) as program:
  17             print ("ops", program._instructions)
  18             program.binfile.seek(0)
  19             insns = load(program.binfile)
  20             #for insn in insns:
  21                 #print ("insn", insn)
  22             insns = list(insns)
  23             print ("insns", insns)
  24             for i, line in enumerate(dump(insns, verbosity=Verbosity.SHORT)):
  25                 name = expected[i].split(" ")[0]
  26                 with self.subTest("%d:%s" % (i, name)):
  27                     print("instruction", repr(line), repr(expected[i]))
  28                     self.assertEqual(expected[i], line,
  29                                      "instruction does not match "
  30                                      "'%s' expected '%s'" % (line, expected[i]))
  31
  32
  33     def test_0_add(self):
  34         expected = ['addi 1,5,2',
  35                     'add 1,5,2',
  36                     'add. 1,5,2',
  37                     'addo 1,5,2',
  38                     'addo. 1,5,2',
  39                         ]
  40         self._do_tst(expected)
  41
  42     def test_1_svshape2(self):
  43         expected = [
  44                     'svshape2 12,1,15,5,0,0'
  45                         ]
  46         self._do_tst(expected)
  47
  48     def test_2_d_custom_op(self):
  49         expected = [
  50                     'fishmv 12,2',
  51                     'fmvis 12,97',
  52                     'addpcis 12,5',
  53                         ]
  54         self._do_tst(expected)
  55
  56     def test_3_sv_isel(self):
  57         expected = [
  58                     'sv.isel 12,2,3,33',
  59                     'sv.isel 12,2,3,*33',
  60                     'sv.isel 12,2,3,*483',
  61                     'sv.isel 12,2,3,63',
  62                     'sv.isel 12,2,3,*99',
  63                         ]
  64         self._do_tst(expected)
  65
  66     def test_4_sv_crand(self):
  67         expected = [
  68                     'sv.crand *16,*2,*33',
  69                     'sv.crand 12,2,33',
  70                     'sv.crand/ff=eq/m=r10 12,2,33',
  71                     'sv.crand/m=r10 12,2,33',
  72                     'sv.crand/m=r10/sz 12,2,33',
  73                     # XXX dz/sz is not the canonical way, must be zz
  74                     'sv.crand/dz/m=r10/sz 12,2,33', # NOT OK
  75                     'sv.crand/m=r10/zz 12,2,33',    # SHOULD PASS
  76                         ]
  77         self._do_tst(expected)
  78
  79     def test_5_setvl(self):
  80         expected = [
  81                     "setvl 5,4,5,0,1,1",
  82                     "setvl. 5,4,5,0,1,1",
  83                         ]
  84         self._do_tst(expected)
  85
  86     def test_6_sv_setvl(self):
  87         expected = [
  88                     "sv.setvl 5,4,5,0,1,1",
  89                     "sv.setvl 63,35,5,0,1,1",
  90                         ]
  91         self._do_tst(expected)
  92
  93     def test_7_batch(self):
  94         "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
  95         expected = [
  96                     "addi 2,2,0",
  97                     "addis 9,2,0",
  98                     "addi 9,9,0",
  99                     "rlwinm 7,7,2,0,29",
 100                     "mulli 0,7,31",
 101                     "add 10,6,0",
 102                     "setvl 0,0,8,1,1,0",
 103                     "addi 16,4,124",
 104                     "lfiwax 0,0,5",
 105                     "addi 5,3,64",
 106                     "sv.lfs *32,256(4)",
 107                     "sv.lfs *40,256(5)",
 108                     "sv.fmuls *32,*32,*40",
 109                     "sv.fadds 0,*32,0",
 110                     "addi 5,3,192",
 111                     "addi 4,4,128",
 112                     "sv.lfs *32,256(4)",
 113                     "sv.lfs *40,256(5)",
 114                     "sv.fmuls *32,*32,*40",
 115                     "sv.fsubs 0,0,*32",
 116                     "addi 4,4,-128",
 117                     "stfs 0,0(6)",
 118                     "add 6,6,7",
 119                     "addi 4,4,4",
 120                     "addi 0,0,15",
 121                     "mtspr 288,0",
 122                     "addi 8,0,4",
 123                     "lfiwax 0,0,9",
 124                     "lfiwax 1,0,9",
 125                     "addi 5,3,64",
 126                     "add 5,5,8",
 127                     "sv.lfs *32,256(5)",
 128                     "sv.lfs *40,256(4)",
 129                     "sv.lfs *48,256(16)",
 130                     "sv.fmuls *40,*32,*40",
 131                     "sv.fadds 0,0,*40",
 132                     "sv.fmuls *32,*32,*48",
 133                     "sv.fsubs 1,1,*32",
 134                     "addi 5,3,192",
 135                     "subf 5,8,5",
 136                     "addi 4,4,128",
 137                     "addi 16,16,128",
 138                     "sv.lfs *32,256(5)",
 139                     "sv.lfs *40,256(4)",
 140                     "sv.lfs *48,256(16)",
 141                     "sv.fmuls *40,*32,*40",
 142                     "sv.fsubs 0,0,*40",
 143                     "sv.fmuls *32,*32,*48",
 144                     "sv.fsubs 1,1,*32",
 145                     "addi 4,4,-128",
 146                     "addi 16,16,-128",
 147                     "stfs 0,0(6)",
 148                     "add 6,6,7",
 149                     "stfs 1,0(10)",
 150                     "subf 10,7,10",
 151                     "addi 8,8,4",
 152                     "addi 4,4,4",
 153                     "addi 16,16,-4",
 154                     "bc 16,0,-0xb4",
 155                     "addi 5,3,128",
 156                     "addi 4,4,128",
 157                     "lfiwax 0,0,9",
 158                     "sv.lfs *32,256(4)",
 159                     "sv.lfs *40,256(5)",
 160                     "sv.fmuls *32,*32,*40",
 161                     "sv.fsubs 0,0,*32",
 162                     "stfs 0,0(6)",
 163                     "bclr 20,0,0",
 164                         ]
 165         self._do_tst(expected)
 166
 167     def test_8_madd(self):
 168         expected = [
 169                     "maddhd 5,4,5,3",
 170                     "maddhdu 5,4,5,3",
 171                     "maddld 5,4,5,3",
 172                         ]
 173         self._do_tst(expected)
 174
 175     def test_9_fptrans(self):
 176         "enumerates a list of fptrans instruction disassembly entries"
 177         db = Database(find_wiki_dir())
 178         entries = sorted(sv_binutils_fptrans.collect(db))
 179         dis = lambda entry: sv_binutils_fptrans.dis(entry, binutils=False)
 180         lst = []
 181         for generator in map(dis, entries):
 182             for line in generator:
 183                 lst.append(line)
 184         self._do_tst(lst)
 185
 186     def test_10_vec(self):
 187         expected = [
 188                     "sv.add./vec2 *3,*7,*11",
 189                     "sv.add./vec3 *3,*7,*11",
 190                     "sv.add./vec4 *3,*7,*11",
 191                         ]
 192         self._do_tst(expected)
 193
 194     def test_11_elwidth(self):
 195         expected = [
 196                     "sv.add./dw=8 *3,*7,*11",
 197                     "sv.add./dw=16 *3,*7,*11",
 198                     "sv.add./dw=32 *3,*7,*11",
 199                     "sv.add./sw=8 *3,*7,*11",
 200                     "sv.add./sw=16 *3,*7,*11",
 201                     "sv.add./sw=32 *3,*7,*11",
 202                     "sv.add./dw=8/sw=16 *3,*7,*11",
 203                     "sv.add./dw=16/sw=32 *3,*7,*11",
 204                     "sv.add./dw=32/sw=8 *3,*7,*11",
 205                     "sv.add./w=32 *3,*7,*11",
 206                     "sv.add./w=8 *3,*7,*11",
 207                     "sv.add./w=16 *3,*7,*11",
 208                         ]
 209         self._do_tst(expected)
 210
 211     def test_12_sat(self):
 212         expected = [
 213                     "sv.add./satu *3,*7,*11",
 214                     "sv.add./sats *3,*7,*11",
 215                         ]
 216         self._do_tst(expected)
 217
 218     def test_12_mr_r(self):
 219         expected = [
 220                     "sv.add./mrr/vec2 *3,*7,*11",
 221                     "sv.add./mr/vec2 *3,*7,*11",
 222                     "sv.add./mrr *3,*7,*11",
 223                     "sv.add./mr *3,*7,*11",
 224                         ]
 225         self._do_tst(expected)
 226
 227     def test_13_RC1(self):
 228         expected = [
 229                     "sv.add/ff=RC1 *3,*7,*11",
 230                     "sv.add/pr=RC1 *3,*7,*11",
 231                     "sv.add/ff=~RC1 *3,*7,*11",
 232                     "sv.add/pr=~RC1 *3,*7,*11",
 233                         ]
 234         self._do_tst(expected)
 235
 236     def test_14_rc1_ff_pr(self):
 237         expected = [
 238                     "sv.add./ff=eq *3,*7,*11",
 239                     "sv.add./ff=ns *3,*7,*11",
 240                     "sv.add./ff=lt *3,*7,*11",
 241                     "sv.add./ff=ge *3,*7,*11",
 242                     "sv.add./ff=le *3,*7,*11",
 243                     "sv.add./ff=gt *3,*7,*11",
 244                     "sv.add./ff=ne *3,*7,*11",
 245                     "sv.add./pr=eq *3,*7,*11",
 246                     "sv.add./pr=ns *3,*7,*11",
 247                         ]
 248         self._do_tst(expected)
 249
 250     def test_15_predicates(self):
 251         expected = [
 252                     "sv.add./m=r3 *3,*7,*11",
 253                     "sv.add./m=1<<r3 *3,*7,*11",
 254                     "sv.add./m=~r10 *3,*7,*11",
 255                     "sv.add./m=so *3,*7,*11",
 256                     "sv.add./m=ne *3,*7,*11",
 257                     "sv.add./m=lt *3,*7,*11",
 258                     "sv.add. *3,*7,*11",
 259                     "sv.extsw/m=r30 3,7",
 260                     "sv.extsw/dm=~r30/sm=r30 3,7",
 261                     "sv.extsw/dm=eq/sm=gt 3,7",
 262                     "sv.extsw/sm=~r3 3,7",
 263                     "sv.extsw/dm=r30 3,7",
 264                         ]
 265         self._do_tst(expected)
 266
 267     def test_15_els(self):
 268         expected = [
 269                     "sv.stw/els *4,16(2)",
 270                     "sv.lfs/els *1,256(4)",
 271                         ]
 272         self._do_tst(expected)
 273
 274     def test_16_bc(self):
 275         """bigger list in test_pysvp64dis_branch.py, this one's "quick"
 276         """
 277         expected = [
 278                     "sv.bc/all 12,*1,0xc",
 279                     "sv.bc/snz 12,*1,0xc",
 280                     "sv.bc/m=r3/snz 12,*1,0xc",
 281                     "sv.bc/m=r3/sz 12,*1,0xc",
 282                     "sv.bc/all/sl/slu 12,*1,0xc",
 283                     "sv.bc/all/lru/sl/slu/snz 12,*1,0xc",
 284                     "sv.bc/all/lru/sl/slu/snz/vs 12,*1,0xc",
 285                     "sv.bc/all/lru/sl/slu/snz/vsi 12,*1,0xc",
 286                     "sv.bc/all/lru/sl/slu/snz/vsb 12,*1,0xc",
 287                     "sv.bc/all/lru/sl/slu/snz/vsbi 12,*1,0xc",
 288                     "sv.bc/all/ctr/lru/sl/slu/snz 12,*1,0xc",
 289                     "sv.bc/all/cti/lru/sl/slu/snz 12,*1,0xc",
 290                     "sv.bc/all/ctr/lru/sl/slu/snz/vsb 12,*1,0xc",
 291                         ]
 292         self._do_tst(expected)
 293
 294     def test_17_vli(self):
 295         expected = [
 296                     "sv.add/ff=RC1/vli 3,7,11",
 297                     "sv.add/ff=~RC1/vli 3,7,11",
 298                         ]
 299         self._do_tst(expected)
 300
 301     def test_18_sea(self):
 302         expected = [
 303                     "sv.ldux/sea 5,6,7",
 304                         ]
 305         self._do_tst(expected)
 306
 307     def test_19_ldst_idx_els(self):
 308         expected = [
 309                     "sv.stdx/els *4,16,2",
 310                     "sv.stdx/els/sea *4,16,2",
 311                     "sv.ldx/els *4,16,2",
 312                     "sv.ldx/els/sea *4,16,2",
 313                         ]
 314         self._do_tst(expected)
 315
 316     def test_20_cmp(self):
 317         expected = [
 318                     "sv.cmp *4,1,*0,1",
 319                     "sv.cmp/ff=RC1 *4,1,*0,1",
 320                     "sv.cmp/ff=RC1/vli *4,1,*0,1",
 321                     "sv.cmp/ff=~RC1 *4,1,*0,1",
 322                     "sv.cmp/ff=RC1/m=r3/sz *4,1,*0,1",
 323                     "sv.cmp/dz/ff=RC1/m=r3 *4,1,*0,1",
 324                     "sv.cmp/dz/ff=RC1/m=r3/sz *4,1,*0,1",
 325                         ]
 326         self._do_tst(expected)
 327
 328     def test_21_addex(self):
 329         expected = [
 330                     "addex 5,3,2,0",
 331                     "sv.addex 5,3,2,0",
 332                     "sv.addex *5,3,2,0",
 333                         ]
 334         self._do_tst(expected)
 335
 336     def test_22_ld(self):
 337         expected = [
 338                     "ld 4,0(5)",
 339                     "ld 4,16(5)",       # sigh, needs magic-shift (D||0b00)
 340                     "sv.ld 4,16(5)",    # ditto
 341                         ]
 342         self._do_tst(expected)
 343
 344     def test_23_lq(self):
 345         expected = [
 346                     "lq 4,0(5)",
 347                     "lq 4,16(5)",      # ditto, magic-shift (DQ||0b0000)
 348                     "lq 4,32(5)",      # ditto
 349                     "sv.lq 4,16(5)",   # ditto
 350                         ]
 351         self._do_tst(expected)
 352
 353     def test_24_bc(self):
 354         expected = [
 355                     "b 0x28",
 356                     "bc 16,0,-0xb4",
 357                         ]
 358         self._do_tst(expected)
 359
 360     def test_25_stq(self):
 361         expected = [
 362                     "stq 4,0(5)",
 363                     "stq 4,8(5)",
 364                     "stq 4,16(5)",
 365                     "sv.stq 4,16(*5)",
 366                         ]
 367         self._do_tst(expected)
 368
 369     def test_26_sv_stq_vector_name(self):
 370         expected = [
 371                     "sv.stq *4,16(*5)", # RSp not recognised as "vector" name
 372                         ]
 373         self._do_tst(expected)
 374
 375     def test_27_sc(self):
 376         expected = [
 377                     "sc 0",
 378                     "sc 1",
 379                     "scv 1",
 380                     "scv 2",
 381                         ]
 382         self._do_tst(expected)
 383
 384     def test_28_rfid(self):
 385         expected = [
 386                     "rfid",
 387                     "rfscv",
 388                         ]
 389         self._do_tst(expected)
 390
 391     def test_29_postinc(self):
 392         expected = [
 393                     "sv.ldu/pi 5,8(2)",
 394                     "sv.lwzu/pi *6,8(2)",
 395                     "sv.lwzu/pi *6,24(2)",
 396                     "sv.stwu/pi *6,24(2)",
 397                         ]
 398         self._do_tst(expected)
 399
 400     def test_29_dsld_dsrd(self):
 401         expected = [
 402                     "dsld 5,4,5,3",
 403                     "dsrd 5,4,5,3",
 404                     "dsld. 5,4,5,3",
 405                     "dsrd. 5,4,5,3",
 406                     "sv.dsld *6,4,5,3",
 407                     "sv.dsrd *6,4,5,3",
 408                     "sv.dsld. *6,4,5,3",
 409                     "sv.dsrd. *6,4,5,3",
 410                         ]
 411         self._do_tst(expected)
 412
 413     def test_30_divmod2du(self):
 414         expected = [
 415                     "divmod2du 5,4,5,3",
 416                     "maddedu 5,4,5,3",
 417                     "sv.divmod2du 5,4,5,3",
 418                     "sv.divmod2du *6,4,*0,3",
 419                     "sv.maddedu 5,4,5,3",
 420                     "sv.maddedu *6,4,5,3",
 421                         ]
 422         self._do_tst(expected)
 423
 424     def test_31_shadd_shadduw(self):
 425         expected = [
 426                     "shadd 31,0,0,0",
 427                     "shadd 0,31,0,0",
 428                     "shadd 0,0,31,0",
 429                     "shadd 0,0,0,3",
 430                     "shadd. 31,0,0,0",
 431                     "shadd. 0,31,0,0",
 432                     "shadd. 0,0,31,0",
 433                     "shadd. 0,0,0,3",
 434                     "shadduw 31,0,0,0",
 435                     "shadduw 0,31,0,0",
 436                     "shadduw 0,0,31,0",
 437                     "shadduw 0,0,0,3",
 438                     "shadduw. 31,0,0,0",
 439                     "shadduw. 0,31,0,0",
 440                     "shadduw. 0,0,31,0",
 441                     "shadduw. 0,0,0,3",
 442                         ]
 443         self._do_tst(expected)
 444
 445 if __name__ == "__main__":
 446     unittest.main()