d730582bf1aaac2b6c86595a62aef02c4688221f
1 from openpower
.simulator
.program
import Program
2 from openpower
.sv
.trans
.pysvp64dis
import load
, dump
3 from openpower
.sv
.trans
.svp64
import SVP64Asm
4 from openpower
.decoder
.power_insn
import Verbosity
8 class SVSTATETestCase(unittest
.TestCase
):
10 def _do_tst(self
, expected
):
11 isa
= SVP64Asm(expected
)
13 with
Program(lst
, bigendian
=False) as program
:
14 print ("ops", program
._instructions
)
15 program
.binfile
.seek(0)
16 insns
= load(program
.binfile
)
20 print ("insns", insns
)
21 for i
, line
in enumerate(dump(insns
, verbosity
=Verbosity
.SHORT
)):
22 name
= expected
[i
].split(" ")[0]
23 with self
.subTest("%d:%s" % (i
, name
)):
24 print("instruction", repr(line
), repr(expected
[i
]))
25 self
.assertEqual(expected
[i
], line
,
26 "instruction does not match "
27 "'%s' expected '%s'" % (line
, expected
[i
]))
31 expected
= ['addi 1,5,2',
37 self
._do
_tst
(expected
)
39 def test_1_svshape2(self
):
41 'svshape2 12,1,15,5,0,0'
43 self
._do
_tst
(expected
)
45 def test_2_d_custom_op(self
):
51 self
._do
_tst
(expected
)
53 def test_3_sv_isel(self
):
57 'sv.isel 12,2,3,*483',
61 self
._do
_tst
(expected
)
63 def test_4_sv_crand(self
):
65 'sv.crand *16,*2,*33',
68 self
._do
_tst
(expected
)
70 def test_5_setvl(self
):
75 self
._do
_tst
(expected
)
77 def test_6_sv_setvl(self
):
79 "sv.setvl 5,4,5,0,1,1",
80 "sv.setvl 63,35,5,0,1,1",
82 self
._do
_tst
(expected
)
84 def test_7_batch(self
):
85 "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
100 "sv.fmuls *32,*32,*40",
106 "sv.fmuls *32,*32,*40",
121 "sv.lfs *48,256(16)",
122 "sv.fmuls *40,*32,*40",
124 "sv.fmuls *32,*32,*48",
132 "sv.lfs *48,256(16)",
133 "sv.fmuls *40,*32,*40",
135 "sv.fmuls *32,*32,*48",
152 "sv.fmuls *32,*32,*40",
157 self
._do
_tst
(expected
)
159 if __name__
== "__main__":