d730582bf1aaac2b6c86595a62aef02c4688221f
[openpower-isa.git] / src / openpower / sv / trans / test_pysvp64dis.py
1 from openpower.simulator.program import Program
2 from openpower.sv.trans.pysvp64dis import load, dump
3 from openpower.sv.trans.svp64 import SVP64Asm
4 from openpower.decoder.power_insn import Verbosity
5 import unittest
6 import sys
7
8 class SVSTATETestCase(unittest.TestCase):
9
10 def _do_tst(self, expected):
11 isa = SVP64Asm(expected)
12 lst = list(isa)
13 with Program(lst, bigendian=False) as program:
14 print ("ops", program._instructions)
15 program.binfile.seek(0)
16 insns = load(program.binfile)
17 #for insn in insns:
18 #print ("insn", insn)
19 insns = list(insns)
20 print ("insns", insns)
21 for i, line in enumerate(dump(insns, verbosity=Verbosity.SHORT)):
22 name = expected[i].split(" ")[0]
23 with self.subTest("%d:%s" % (i, name)):
24 print("instruction", repr(line), repr(expected[i]))
25 self.assertEqual(expected[i], line,
26 "instruction does not match "
27 "'%s' expected '%s'" % (line, expected[i]))
28
29
30 def test_0_add(self):
31 expected = ['addi 1,5,2',
32 'add 1,5,2',
33 'add. 1,5,2',
34 'addo 1,5,2',
35 'addo. 1,5,2',
36 ]
37 self._do_tst(expected)
38
39 def test_1_svshape2(self):
40 expected = [
41 'svshape2 12,1,15,5,0,0'
42 ]
43 self._do_tst(expected)
44
45 def test_2_d_custom_op(self):
46 expected = [
47 'fishmv 12,2',
48 'fmvis 12,97',
49 'addpcis 12,5',
50 ]
51 self._do_tst(expected)
52
53 def test_3_sv_isel(self):
54 expected = [
55 'sv.isel 12,2,3,33',
56 'sv.isel 12,2,3,*33',
57 'sv.isel 12,2,3,*483',
58 'sv.isel 12,2,3,63',
59 'sv.isel 12,2,3,*99',
60 ]
61 self._do_tst(expected)
62
63 def test_4_sv_crand(self):
64 expected = [
65 'sv.crand *16,*2,*33',
66 'sv.crand 12,2,33',
67 ]
68 self._do_tst(expected)
69
70 def test_5_setvl(self):
71 expected = [
72 "setvl 5,4,5,0,1,1",
73 "setvl. 5,4,5,0,1,1",
74 ]
75 self._do_tst(expected)
76
77 def test_6_sv_setvl(self):
78 expected = [
79 "sv.setvl 5,4,5,0,1,1",
80 "sv.setvl 63,35,5,0,1,1",
81 ]
82 self._do_tst(expected)
83
84 def test_7_batch(self):
85 "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
86 expected = [
87 "addis 2,12,0",
88 "addi 2,2,0",
89 "addis 9,2,0",
90 "addi 9,9,0",
91 "rlwinm 7,7,2,0,29",
92 "mulli 0,7,31",
93 "add 10,6,0",
94 "setvl 0,0,8,1,1,0",
95 "addi 16,4,124",
96 "lfiwax 0,0,5",
97 "addi 5,3,64",
98 "sv.lfs *32,256(4)",
99 "sv.lfs *40,256(5)",
100 "sv.fmuls *32,*32,*40",
101 "sv.fadds 0,*32,0",
102 "addi 5,3,192",
103 "addi 4,4,128",
104 "sv.lfs *32,256(4)",
105 "sv.lfs *40,256(5)",
106 "sv.fmuls *32,*32,*40",
107 "sv.fsubs 0,0,*32",
108 "addi 4,4,65408",
109 "stfs 0,0(6)",
110 "add 6,6,7",
111 "addi 4,4,4",
112 "addi 0,0,15",
113 "mtspr 288,0",
114 "addi 8,0,4",
115 "lfiwax 0,0,9",
116 "lfiwax 1,0,9",
117 "addi 5,3,64",
118 "add 5,5,8",
119 "sv.lfs *32,256(5)",
120 "sv.lfs *40,256(4)",
121 "sv.lfs *48,256(16)",
122 "sv.fmuls *40,*32,*40",
123 "sv.fadds 0,0,*40",
124 "sv.fmuls *32,*32,*48",
125 "sv.fsubs 1,1,*32",
126 "addi 5,3,192",
127 "subf 5,8,5",
128 "addi 4,4,128",
129 "addi 16,16,128",
130 "sv.lfs *32,256(5)",
131 "sv.lfs *40,256(4)",
132 "sv.lfs *48,256(16)",
133 "sv.fmuls *40,*32,*40",
134 "sv.fsubs 0,0,*40",
135 "sv.fmuls *32,*32,*48",
136 "sv.fsubs 1,1,*32",
137 "addi 4,4,65408",
138 "addi 16,16,65408",
139 "stfs 0,0(6)",
140 "add 6,6,7",
141 "stfs 1,0(10)",
142 "subf 10,7,10",
143 "addi 8,8,4",
144 "addi 4,4,4",
145 "addi 16,16,65532",
146 "bc 16,0,0xff4c",
147 "addi 5,3,128",
148 "addi 4,4,128",
149 "lfiwax 0,0,9",
150 "sv.lfs *32,256(4)",
151 "sv.lfs *40,256(5)",
152 "sv.fmuls *32,*32,*40",
153 "sv.fsubs 0,0,*32",
154 "stfs 0,0(6)",
155 "bclr 20,0,0",
156 ]
157 self._do_tst(expected)
158
159 if __name__ == "__main__":
160 unittest.main()
161