src/openpower/sv/trans/test_pysvp64dis.py

   1 from openpower.simulator.program import Program
   2 from openpower.sv.trans.pysvp64dis import load, dump
   3 from openpower.sv.trans.svp64 import SVP64Asm
   4 from openpower.decoder.power_insn import Database, Verbosity
   5 from openpower.decoder.power_enums import find_wiki_dir
   6 from openpower.sv import sv_binutils_fptrans
   7 import unittest
   8 from io import BytesIO
   9 import itertools
  10 import sys
  11
  12 class SVSTATETestCase(unittest.TestCase):
  13
  14     def _do_tst(self, expected):
  15         isa = SVP64Asm(expected)
  16         lst = list(isa)
  17         with Program(lst, bigendian=False) as program:
  18             print ("ops", program._instructions)
  19             binfile = BytesIO()
  20             program.binfile.seek(0)
  21             binfile.write(program.binfile.read())
  22             program.binfile.seek(0)
  23             binfile.seek(0)
  24             insns = load(binfile)
  25             #for insn in insns:
  26                 #print ("insn", insn)
  27             insns = list(insns)
  28             print ("insns", insns)
  29             for i, line in enumerate(dump(insns, verbosity=Verbosity.SHORT)):
  30                 name = expected[i].split(" ")[0]
  31                 with self.subTest("%d:%s" % (i, name)):
  32                     print("instruction", repr(line), repr(expected[i]))
  33                     self.assertEqual(expected[i], line,
  34                                      "instruction does not match "
  35                                      "'%s' expected '%s'" % (line, expected[i]))
  36
  37
  38     def test_0_add(self):
  39         expected = ['addi 1,5,2',
  40                     'add 1,5,2',
  41                     'add. 1,5,2',
  42                     'addo 1,5,2',
  43                     'addo. 1,5,2',
  44                         ]
  45         self._do_tst(expected)
  46
  47     def test_1_svshape2(self):
  48         expected = [
  49                     'svshape2 12,1,15,5,0,0'
  50                         ]
  51         self._do_tst(expected)
  52
  53     def test_2_d_custom_op(self):
  54         expected = [
  55                     'fishmv 12,2',
  56                     'fmvis 12,97',
  57                     'addpcis 12,5',
  58                         ]
  59         self._do_tst(expected)
  60
  61     def test_3_sv_isel(self):
  62         expected = [
  63                     'sv.isel 12,2,3,33',
  64                     'sv.isel 12,2,3,*33',
  65                     'sv.isel 12,2,3,*483',
  66                     'sv.isel 12,2,3,63',
  67                     'sv.isel 12,2,3,*99',
  68                         ]
  69         self._do_tst(expected)
  70
  71     def test_4_sv_crand(self):
  72         expected = [
  73                     'sv.crand *16,*2,*33',
  74                     'sv.crand 12,2,33',
  75                     'sv.crand/ff=eq/m=r10 12,2,33',
  76                     'sv.crand/m=r10 12,2,33',
  77                     'sv.crand/m=r10/sz 12,2,33',
  78                     # XXX dz/sz is not the canonical way, must be zz
  79                     'sv.crand/dz/m=r10/sz 12,2,33', # NOT OK
  80                     'sv.crand/m=r10/zz 12,2,33',    # SHOULD PASS
  81                         ]
  82         self._do_tst(expected)
  83
  84     def test_5_setvl(self):
  85         expected = [
  86                     "setvl 5,4,5,0,1,1",
  87                     "setvl. 5,4,5,0,1,1",
  88                         ]
  89         self._do_tst(expected)
  90
  91     def test_6_sv_setvl(self):
  92         expected = [
  93                     "sv.setvl 5,4,5,0,1,1",
  94                     "sv.setvl 63,35,5,0,1,1",
  95                         ]
  96         self._do_tst(expected)
  97
  98     def test_7_batch(self):
  99         "these come from https://bugs.libre-soc.org/show_bug.cgi?id=917#c25"
 100         expected = [
 101                     "addi 2,2,0",
 102                     "addis 9,2,0",
 103                     "addi 9,9,0",
 104                     "rlwinm 7,7,2,0,29",
 105                     "mulli 0,7,31",
 106                     "add 10,6,0",
 107                     "setvl 0,0,8,1,1,0",
 108                     "addi 16,4,124",
 109                     "lfiwax 0,0,5",
 110                     "addi 5,3,64",
 111                     "sv.lfs *32,256(4)",
 112                     "sv.lfs *40,256(5)",
 113                     "sv.fmuls *32,*32,*40",
 114                     "sv.fadds 0,*32,0",
 115                     "addi 5,3,192",
 116                     "addi 4,4,128",
 117                     "sv.lfs *32,256(4)",
 118                     "sv.lfs *40,256(5)",
 119                     "sv.fmuls *32,*32,*40",
 120                     "sv.fsubs 0,0,*32",
 121                     "addi 4,4,-128",
 122                     "stfs 0,0(6)",
 123                     "add 6,6,7",
 124                     "addi 4,4,4",
 125                     "addi 0,0,15",
 126                     "mtspr 288,0",
 127                     "addi 8,0,4",
 128                     "lfiwax 0,0,9",
 129                     "lfiwax 1,0,9",
 130                     "addi 5,3,64",
 131                     "add 5,5,8",
 132                     "sv.lfs *32,256(5)",
 133                     "sv.lfs *40,256(4)",
 134                     "sv.lfs *48,256(16)",
 135                     "sv.fmuls *40,*32,*40",
 136                     "sv.fadds 0,0,*40",
 137                     "sv.fmuls *32,*32,*48",
 138                     "sv.fsubs 1,1,*32",
 139                     "addi 5,3,192",
 140                     "subf 5,8,5",
 141                     "addi 4,4,128",
 142                     "addi 16,16,128",
 143                     "sv.lfs *32,256(5)",
 144                     "sv.lfs *40,256(4)",
 145                     "sv.lfs *48,256(16)",
 146                     "sv.fmuls *40,*32,*40",
 147                     "sv.fsubs 0,0,*40",
 148                     "sv.fmuls *32,*32,*48",
 149                     "sv.fsubs 1,1,*32",
 150                     "addi 4,4,-128",
 151                     "addi 16,16,-128",
 152                     "stfs 0,0(6)",
 153                     "add 6,6,7",
 154                     "stfs 1,0(10)",
 155                     "subf 10,7,10",
 156                     "addi 8,8,4",
 157                     "addi 4,4,4",
 158                     "addi 16,16,-4",
 159                     "bc 16,0,-0xb4",
 160                     "addi 5,3,128",
 161                     "addi 4,4,128",
 162                     "lfiwax 0,0,9",
 163                     "sv.lfs *32,256(4)",
 164                     "sv.lfs *40,256(5)",
 165                     "sv.fmuls *32,*32,*40",
 166                     "sv.fsubs 0,0,*32",
 167                     "stfs 0,0(6)",
 168                     "bclr 20,0,0",
 169                         ]
 170         self._do_tst(expected)
 171
 172     def test_8_madd(self):
 173         expected = [
 174                     "maddhd 5,4,5,3",
 175                     "maddhdu 5,4,5,3",
 176                     "maddld 5,4,5,3",
 177                         ]
 178         self._do_tst(expected)
 179
 180     def test_9_fptrans(self):
 181         "enumerates a list of fptrans instruction disassembly entries"
 182         db = Database(find_wiki_dir())
 183         entries = sorted(sv_binutils_fptrans.collect(db))
 184         dis = lambda entry: sv_binutils_fptrans.dis(entry, binutils=False)
 185         lst = []
 186         for generator in map(dis, entries):
 187             for line in generator:
 188                 lst.append(line)
 189         self._do_tst(lst)
 190
 191     def test_10_vec(self):
 192         expected = [
 193                     "sv.add./vec2 *3,*7,*11",
 194                     "sv.add./vec3 *3,*7,*11",
 195                     "sv.add./vec4 *3,*7,*11",
 196                         ]
 197         self._do_tst(expected)
 198
 199     def test_11_elwidth(self):
 200         expected = [
 201                     "sv.add./dw=8 *3,*7,*11",
 202                     "sv.add./dw=16 *3,*7,*11",
 203                     "sv.add./dw=32 *3,*7,*11",
 204                     "sv.add./sw=8 *3,*7,*11",
 205                     "sv.add./sw=16 *3,*7,*11",
 206                     "sv.add./sw=32 *3,*7,*11",
 207                     "sv.add./dw=8/sw=16 *3,*7,*11",
 208                     "sv.add./dw=16/sw=32 *3,*7,*11",
 209                     "sv.add./dw=32/sw=8 *3,*7,*11",
 210                     "sv.add./w=32 *3,*7,*11",
 211                     "sv.add./w=8 *3,*7,*11",
 212                     "sv.add./w=16 *3,*7,*11",
 213                         ]
 214         self._do_tst(expected)
 215
 216     def test_12_sat(self):
 217         expected = [
 218                     "sv.add./satu *3,*7,*11",
 219                     "sv.add./sats *3,*7,*11",
 220                         ]
 221         self._do_tst(expected)
 222
 223     def test_12_mr_r(self):
 224         expected = [
 225                     "sv.add./mrr/vec2 *3,*7,*11",
 226                     "sv.add./mr/vec2 *3,*7,*11",
 227                     "sv.add./mrr *3,*7,*11",
 228                     "sv.add./mr *3,*7,*11",
 229                         ]
 230         self._do_tst(expected)
 231
 232     def test_13_RC1(self):
 233         expected = [
 234                     "sv.add/ff=RC1 *3,*7,*11",
 235                     "sv.add/pr=RC1 *3,*7,*11",
 236                     "sv.add/ff=~RC1 *3,*7,*11",
 237                     "sv.add/pr=~RC1 *3,*7,*11",
 238                         ]
 239         self._do_tst(expected)
 240
 241     def test_14_rc1_ff_pr(self):
 242         expected = [
 243                     "sv.add./ff=eq *3,*7,*11",
 244                     "sv.add./ff=ns *3,*7,*11",
 245                     "sv.add./ff=lt *3,*7,*11",
 246                     "sv.add./ff=ge *3,*7,*11",
 247                     "sv.add./ff=le *3,*7,*11",
 248                     "sv.add./ff=gt *3,*7,*11",
 249                     "sv.add./ff=ne *3,*7,*11",
 250                     "sv.add./pr=eq *3,*7,*11",
 251                     "sv.add./pr=ns *3,*7,*11",
 252                         ]
 253         self._do_tst(expected)
 254
 255     def test_15_predicates(self):
 256         expected = [
 257                     "sv.add./m=r3 *3,*7,*11",
 258                     "sv.add./m=1<<r3 *3,*7,*11",
 259                     "sv.add./m=~r10 *3,*7,*11",
 260                     "sv.add./m=so *3,*7,*11",
 261                     "sv.add./m=ne *3,*7,*11",
 262                     "sv.add./m=lt *3,*7,*11",
 263                     "sv.add. *3,*7,*11",
 264                     "sv.extsw/m=r30 3,7",
 265                     "sv.extsw/dm=~r30/sm=r30 3,7",
 266                     "sv.extsw/dm=eq/sm=gt 3,7",
 267                     "sv.extsw/sm=~r3 3,7",
 268                     "sv.extsw/dm=r30 3,7",
 269                         ]
 270         self._do_tst(expected)
 271
 272     def test_15_els(self):
 273         expected = [
 274                     "sv.stw/els *4,16(2)",
 275                     "sv.lfs/els *1,256(4)",
 276                         ]
 277         self._do_tst(expected)
 278
 279     def test_16_bc(self):
 280         """bigger list in test_pysvp64dis_branch.py, this one's "quick"
 281         """
 282         expected = [
 283                     "sv.bc/all 12,*1,0xc",
 284                     "sv.bc/snz 12,*1,0xc",
 285                     "sv.bc/m=r3/snz 12,*1,0xc",
 286                     "sv.bc/m=r3/sz 12,*1,0xc",
 287                     "sv.bc/all/sl/slu 12,*1,0xc",
 288                     "sv.bc/all/lru/sl/slu/snz 12,*1,0xc",
 289                     "sv.bc/all/lru/sl/slu/snz/vs 12,*1,0xc",
 290                     "sv.bc/all/lru/sl/slu/snz/vsi 12,*1,0xc",
 291                     "sv.bc/all/lru/sl/slu/snz/vsb 12,*1,0xc",
 292                     "sv.bc/all/lru/sl/slu/snz/vsbi 12,*1,0xc",
 293                     "sv.bc/all/ctr/lru/sl/slu/snz 12,*1,0xc",
 294                     "sv.bc/all/cti/lru/sl/slu/snz 12,*1,0xc",
 295                     "sv.bc/all/ctr/lru/sl/slu/snz/vsb 12,*1,0xc",
 296                         ]
 297         self._do_tst(expected)
 298
 299     def test_17_vli(self):
 300         expected = [
 301                     "sv.add/ff=RC1/vli 3,7,11",
 302                     "sv.add/ff=~RC1/vli 3,7,11",
 303                         ]
 304         self._do_tst(expected)
 305
 306     def test_18_sea(self):
 307         expected = [
 308                     "sv.ldux/sea 5,6,7",
 309                         ]
 310         self._do_tst(expected)
 311
 312     def test_19_ldst_idx_els(self):
 313         expected = [
 314                     "sv.stdx/els *4,16,2",
 315                     "sv.stdx/els/sea *4,16,2",
 316                     "sv.ldx/els *4,16,2",
 317                     "sv.ldx/els/sea *4,16,2",
 318                         ]
 319         self._do_tst(expected)
 320
 321     def test_20_cmp(self):
 322         expected = [
 323                     "sv.cmp *4,1,*0,1",
 324                     "sv.cmp/ff=RC1 *4,1,*0,1",
 325                     "sv.cmp/ff=RC1/vli *4,1,*0,1",
 326                     "sv.cmp/ff=~RC1 *4,1,*0,1",
 327                     "sv.cmp/ff=RC1/m=r3/sz *4,1,*0,1",
 328                     "sv.cmp/dz/ff=RC1/m=r3 *4,1,*0,1",
 329                     "sv.cmp/dz/ff=RC1/m=r3/sz *4,1,*0,1",
 330                         ]
 331         self._do_tst(expected)
 332
 333     def test_21_addex(self):
 334         expected = [
 335                     "addex 5,3,2,0",
 336                     "sv.addex 5,3,2,0",
 337                     "sv.addex *5,3,2,0",
 338                         ]
 339         self._do_tst(expected)
 340
 341     def test_22_ld(self):
 342         expected = [
 343                     "ld 4,0(5)",
 344                     "ld 4,16(5)",       # sigh, needs magic-shift (D||0b00)
 345                     "sv.ld 4,16(5)",    # ditto
 346                         ]
 347         self._do_tst(expected)
 348
 349     def test_23_lq(self):
 350         expected = [
 351                     "lq 4,0(5)",
 352                     "lq 4,16(5)",      # ditto, magic-shift (DQ||0b0000)
 353                     "lq 4,32(5)",      # ditto
 354                     "sv.lq 4,16(5)",   # ditto
 355                         ]
 356         self._do_tst(expected)
 357
 358     def test_24_bc(self):
 359         expected = [
 360                     "b 0x28",
 361                     "bc 16,0,-0xb4",
 362                         ]
 363         self._do_tst(expected)
 364
 365     def test_25_stq(self):
 366         expected = [
 367                     "stq 4,0(5)",
 368                     "stq 4,8(5)",
 369                     "stq 4,16(5)",
 370                     "sv.stq 4,16(*5)",
 371                         ]
 372         self._do_tst(expected)
 373
 374     def test_26_sv_stq_vector_name(self):
 375         expected = [
 376                     "sv.stq *4,16(*5)", # RSp not recognised as "vector" name
 377                         ]
 378         self._do_tst(expected)
 379
 380     def test_27_sc(self):
 381         expected = [
 382                     "sc 0",
 383                     "sc 1",
 384                     "scv 1",
 385                     "scv 2",
 386                         ]
 387         self._do_tst(expected)
 388
 389     def test_28_rfid(self):
 390         expected = [
 391                     "rfid",
 392                     "rfscv",
 393                         ]
 394         self._do_tst(expected)
 395
 396     def test_29_postinc(self):
 397         expected = [
 398                     "sv.ldu/pi 5,8(2)",
 399                     "sv.lwzu/pi *6,8(2)",
 400                     "sv.lwzu/pi *6,24(2)",
 401                     "sv.stwu/pi *6,24(2)",
 402                         ]
 403         self._do_tst(expected)
 404
 405     def test_29_dsld_dsrd(self):
 406         expected = [
 407                     "dsld 5,4,5,3",
 408                     "dsrd 5,4,5,3",
 409                     "dsld. 5,4,5,3",
 410                     "dsrd. 5,4,5,3",
 411                     "sv.dsld *6,4,5,3",
 412                     "sv.dsrd *6,4,5,3",
 413                     "sv.dsld. *6,4,5,3",
 414                     "sv.dsrd. *6,4,5,3",
 415                         ]
 416         self._do_tst(expected)
 417
 418     def test_30_divmod2du(self):
 419         expected = [
 420                     "divmod2du 5,4,5,3",
 421                     "maddedu 5,4,5,3",
 422                     "sv.divmod2du 5,4,5,3",
 423                     "sv.divmod2du *6,4,*0,3",
 424                     "sv.maddedu 5,4,5,3",
 425                     "sv.maddedu *6,4,5,3",
 426                         ]
 427         self._do_tst(expected)
 428
 429     def test_31_shadd_shadduw(self):
 430         expected = [
 431                     "shadd 31,0,0,0",
 432                     "shadd 0,31,0,0",
 433                     "shadd 0,0,31,0",
 434                     "shadd 0,0,0,3",
 435                     "shadd. 31,0,0,0",
 436                     "shadd. 0,31,0,0",
 437                     "shadd. 0,0,31,0",
 438                     "shadd. 0,0,0,3",
 439                     "shadduw 31,0,0,0",
 440                     "shadduw 0,31,0,0",
 441                     "shadduw 0,0,31,0",
 442                     "shadduw 0,0,0,3",
 443                     "shadduw. 31,0,0,0",
 444                     "shadduw. 0,31,0,0",
 445                     "shadduw. 0,0,31,0",
 446                     "shadduw. 0,0,0,3",
 447                         ]
 448         self._do_tst(expected)
 449
 450 if __name__ == "__main__":
 451     unittest.main()