src/openpower/test/alu/maddsubrs_cases.py

   1 from openpower.insndb.asm import SVP64Asm
   2 import random
   3 from openpower.test.common import TestAccumulatorBase, skip_case
   4 from openpower.endian import bigendian
   5 from openpower.simulator.program import Program
   6 from openpower.decoder.selectable_int import SelectableInt
   7 from openpower.decoder.power_enums import XER_bits
   8 from openpower.decoder.isa.caller import SVP64State
   9 from openpower.decoder.helpers import exts
  10 from openpower.test.state import ExpectedState
  11 import unittest
  12 import math
  13
  14
  15 class MADDSUBRSTestCase(TestAccumulatorBase):
  16
  17     def case_0_maddsubrs(self):
  18         isa = SVP64Asm(["maddsubrs 1,10,14,11"])
  19         lst = list(isa)
  20
  21         initial_regs = [0] * 32
  22         initial_regs[1] = 0x00000a71
  23         initial_regs[10] = 0x0000e6b8
  24         initial_regs[11] = 0x00002d41
  25
  26         e = ExpectedState(pc=4)
  27         e.intregs[1] = 0x0000aa86
  28         e.intregs[2] = 0xffffffffffff643e
  29         e.intregs[10] = 0x0000e6b8
  30         e.intregs[11] = 0x00002d41
  31         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  32
  33     def case_1_maddsubrs(self):
  34         isa = SVP64Asm(["maddsubrs 1,10,0,11"])
  35         lst = list(isa)
  36
  37         initial_regs = [0] * 32
  38         initial_regs[1] = 0x00000a71
  39         initial_regs[10] = 0x0000e6b8
  40         initial_regs[11] = 0x00002d41
  41
  42         e = ExpectedState(pc=4)
  43         e.intregs[1] = 0x2aa17069
  44         e.intregs[2] = 0xffffffffd90f96f9
  45         e.intregs[10] = 0x0000e6b8
  46         e.intregs[11] = 0x00002d41
  47         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  48
  49     def case_2_maddsubrs(self):
  50         isa = SVP64Asm(["maddsubrs 1,10,2,11"])
  51         lst = list(isa)
  52
  53         initial_regs = [0] * 32
  54         initial_regs[1] = 0x100000000
  55         initial_regs[10] = 0x000000003
  56         initial_regs[11] = 0x10000000
  57
  58         e = ExpectedState(pc=4)
  59         e.intregs[1] = 0x40000000c000000
  60         e.intregs[2] = 0x3fffffff4000000
  61         e.intregs[10] = 0x00000003
  62         e.intregs[11] = 0x10000000
  63         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  64
  65     def case_3_maddsubrs(self):
  66         isa = SVP64Asm(["maddsubrs 1,10,16,11"])
  67         lst = list(isa)
  68
  69         initial_regs = [0] * 32
  70         initial_regs[1] = 0x100000000
  71         initial_regs[10] = 0x000000003
  72         initial_regs[11] = 0x10000000
  73
  74         e = ExpectedState(pc=4)
  75         e.intregs[1] = 0x100000003000
  76         e.intregs[2] = 0x0fffffffd000
  77         e.intregs[10] = 0x00000003
  78         e.intregs[11] = 0x10000000
  79         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  80
  81     def case_4_maddsubrs(self):
  82         isa = SVP64Asm(["maddsubrs 1,10,1,11"])
  83         lst = list(isa)
  84
  85         initial_regs = [0] * 32
  86         initial_regs[1] = 0x100000000
  87         initial_regs[10] = 0x000000003
  88         initial_regs[11] = 0xff0000000
  89
  90         e = ExpectedState(pc=4)
  91         e.intregs[1] = 0xf8000017e8000000
  92         e.intregs[2] = 0xf7ffffe818000000
  93         e.intregs[10] = 0x000000003
  94         e.intregs[11] = 0xff0000000
  95         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
  96
  97     def case_maddsubrs_16bit_s14(self):
  98         p = Program(list(SVP64Asm([
  99             "sv.maddsubrs/w=16 *10,*20,14,*30",
 100         ])), bigendian)
 101
 102         initial_regs = [0] * 32
 103
 104         # use somewhat reasonable i16 values since we're working in
 105         # 2.14-bit fixed-point
 106
 107         initial_regs[10] = 0x1000_2000_3000_4000  # 0x0.4, 0x0.8, 0x0.c, 0x1.0
 108
 109         # 0x0.48d0, -0x0.0490, 0x0.d158, -0x0.48d4
 110         initial_regs[20] = 0x1234_fedc_3456_edcb
 111         cospi_16_64 = 11585  # from libvpx -- 0x0.b504 ~ 0.70709 ~ cos(pi/4)
 112         initial_regs[30] = cospi_16_64 * 0x1_0001_0001_0001  # splat 4x
 113
 114         svstate = SVP64State()
 115         svstate.vl = 4
 116         svstate.maxvl = 4
 117
 118         e = ExpectedState(pc=8, int_regs=initial_regs)
 119         e.intregs[10] = 0
 120         e.intregs[11] = 0
 121         for i in range(svstate.vl):
 122             rt = (initial_regs[10] >> (i * 16)) & 0xFFFF  # extract element
 123             rt -= (rt & 0x8000) << 1  # sign extend rt
 124             ra = (initial_regs[20] >> (i * 16)) & 0xFFFF
 125             ra -= (ra & 0x8000) << 1  # sign extend ra
 126             rb = (initial_regs[30] >> (i * 16)) & 0xFFFF
 127             rb -= (rb & 0x8000) << 1  # sign extend rb
 128             s = rt + ra
 129             d = rt - ra
 130             # f64 is big enough to represent all relevant values exactly,
 131             # so we can use float
 132             rt = math.floor((s * rb) / (2 ** 14) + 0.5)  # mul & round & shr
 133             rs = math.floor((d * rb) / (2 ** 14) + 0.5)
 134             e.intregs[10] |= (rt & 0xFFFF) << (16 * i)  # insert element
 135             e.intregs[11] |= (rs & 0xFFFF) << (16 * i)
 136
 137         # asserts so you can read the expected values
 138         assert e.intregs[10] == 0x182f_15d2_46f2_2061
 139         assert e.intregs[11] == 0xfe71_176f_fcef_3a21
 140
 141         self.add_case(p, initial_regs, expected=e, initial_svstate=svstate)
 142
 143     def case_0_maddrs(self):
 144         isa = SVP64Asm(["maddsubrs 1,10,0,11",
 145                         "maddrs 1,10,0,12"])
 146         lst = list(isa)
 147
 148         initial_regs = [0] * 32
 149         initial_regs[1] = 0x00000a71
 150         initial_regs[10] = 0x0000e6b8
 151         initial_regs[11] = 0x00002d41
 152         initial_regs[12] = 0x00000d00
 153
 154         e = ExpectedState(pc=8)
 155         e.intregs[1] = 0x3658c869
 156         e.intregs[2] = 0xffffffffcd583ef9
 157         e.intregs[10] = 0x0000e6b8
 158         e.intregs[11] = 0x00002d41
 159         e.intregs[12] = 0x00000d00
 160         self.add_case(Program(lst, bigendian), initial_regs, expected=e)
 161
 162     def case_1_maddrs(self):
 163         isa = SVP64Asm(["maddsubrs 1,10,0,11",
 164                         "maddrs 1,10,14,12"])
 165         lst = list(isa)
 166
 167         initial_regs = [0] * 32
 168         initial_regs[1] = 0x00000a71
 169         initial_regs[10] = 0x0000e6b8
 170         initial_regs[11] = 0x00002d41
 171         initial_regs[12] = 0x00000d00
 172
 173         e = ExpectedState(pc=8)
 174         e.intregs[1] = 0x0000d963
 175         e.intregs[2] = 0xffffffffffff3561
 176         e.intregs[10] = 0x0000e6b8
 177         e.intregs[11] = 0x00002d41
 178         e.intregs[12] = 0x00000d00
 179         self.add_case(Program(lst, bigendian), initial_regs, expected=e)