55f2f3727a86eab14a6f4d407fee7c054d3a071d
1 """TestRunner class, part of the Test API
5 Copyright (C) 2020,2021 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
6 Copyright (C) 2021 Kyle Lehman <klehman9@comcast.net>
7 Copyright (C) 2021 Jonathan Neuschäfer <j.neuschaefer@gmx.net>
8 Copyright (C) 2021 Tobias Platen <tplaten@posteo.de>
9 Copyright (C) 2021 Cesar Strauss <cestrauss@gmail.com>
13 * https://bugs.libre-soc.org/show_bug.cgi?id=363
14 * https://bugs.libre-soc.org/show_bug.cgi?id=686#c51
17 from nmigen
import Module
, ClockSignal
18 from copy
import copy
, deepcopy
19 from pprint
import pprint
21 # NOTE: to use cxxsim, export NMIGEN_SIM_MODE=cxxsim from the shell
22 # Also, check out the cxxsim nmigen branch, and latest yosys from git
23 from nmutil
.sim_tmp_alternative
import Simulator
, Settle
25 from nmutil
.formaltest
import FHDLTestCase
26 from nmutil
.gtkw
import write_gtkw
27 from openpower
.decoder
.isa
.all
import ISA
28 from openpower
.endian
import bigendian
30 from openpower
.decoder
.power_decoder2
import PowerDecode2
32 from soc
.config
.test
.test_loadstore
import TestMemPspec
33 from nmutil
.util
import wrap
34 from openpower
.test
.wb_get
import wb_get
35 import openpower
.test
.wb_get
as wbget
36 from openpower
.test
.state
import TestState
, StateRunner
, ExpectedState
39 class SimRunner(StateRunner
):
40 """SimRunner: Implements methods for the setup, preparation, and
41 running of tests using ISACaller simulation
43 def __init__(self
, dut
, m
, pspec
):
44 super().__init
__("sim", SimRunner
)
47 self
.mmu
= pspec
.mmu
== True
48 regreduce_en
= pspec
.regreduce_en
== True
49 self
.simdec2
= simdec2
= PowerDecode2(None, regreduce_en
=regreduce_en
)
50 m
.submodules
.simdec2
= simdec2
# pain in the neck
52 def prepare_for_test(self
, test
):
57 def run_test(self
, instructions
, gen
, insncode
):
58 """run_sim_state - runs an ISACaller simulation
61 dut
, test
, simdec2
= self
.dut
, self
.test
, self
.simdec2
64 # set up the Simulator (which must track TestIssuer exactly)
65 sim
= ISA(simdec2
, test
.regs
, test
.sprs
, test
.cr
, test
.mem
,
67 initial_insns
=gen
, respect_pc
=True,
70 initial_svstate
=test
.svstate
,
73 # run the loop of the instructions on the current test
74 index
= sim
.pc
.CIA
.value
//4
75 while index
< len(instructions
):
76 ins
, code
= instructions
[index
]
78 print("sim instr: 0x{:X}".format(ins
& 0xffffffff))
81 # set up simulated instruction (in simdec2)
83 yield from sim
.setup_one()
84 except KeyError: # instruction not in imem: stop
88 # call simulated operation
90 yield from sim
.execute_one()
92 index
= sim
.pc
.CIA
.value
//4
94 # get sim register and memory TestState, add to list
95 state
= yield from TestState("sim", sim
, dut
, code
)
96 sim_states
.append(state
)
98 if self
.dut
.allow_overlap
:
99 # get last state, at end of run
100 state
= yield from TestState("sim", sim
, dut
, code
)
101 sim_states
.append(state
)
106 class TestRunnerBase(FHDLTestCase
):
107 """TestRunnerBase: Sets up and executes the running of tests
108 contained in tst_data. run_hdl (if provided) is an HDLRunner
109 object. If not provided, hdl simulation is skipped.
111 ISACaller simulation can be skipped by setting run_sim=False.
113 When using an Expected state to test with, the expected state
114 is passed in with tst_data.
116 def __init__(self
, tst_data
, microwatt_mmu
=False, rom
=None,
117 svp64
=True, run_hdl
=None, run_sim
=True,
118 allow_overlap
=False):
119 super().__init
__("run_all")
120 self
.test_data
= tst_data
121 self
.microwatt_mmu
= microwatt_mmu
124 self
.allow_overlap
= allow_overlap
125 self
.run_hdl
= run_hdl
126 self
.run_sim
= run_sim
131 if self
.microwatt_mmu
:
132 # do not wire these up to anything if wb_get is to be used
133 if self
.rom
is not None:
134 ldst_ifacetype
= 'mmu_cache_wb'
135 imem_ifacetype
= 'mmu_cache_wb'
137 ldst_ifacetype
= 'test_mmu_cache_wb'
138 imem_ifacetype
= 'test_bare_wb'
140 ldst_ifacetype
= 'test_bare_wb'
141 imem_ifacetype
= 'test_bare_wb'
143 pspec
= TestMemPspec(ldst_ifacetype
=ldst_ifacetype
,
144 imem_ifacetype
=imem_ifacetype
,
153 regreduce
=not self
.allow_overlap
,
154 core_domain
="sync", # no alternative domain
156 allow_overlap
=self
.allow_overlap
,
157 mmu
=self
.microwatt_mmu
,
160 ###### SETUP PHASE #######
161 # Determine the simulations needed and add to state_list
162 # for setup and running
163 # The methods contained in the respective Runner classes are
164 # called using this list when possible
166 # allow wb_get to run
167 if self
.rom
is not None:
173 hdlrun
= self
.run_hdl(self
, m
, pspec
)
174 state_list
.append(hdlrun
)
177 simrun
= SimRunner(self
, m
, pspec
)
178 state_list
.append(simrun
)
180 # run core clock at same rate as test clock
181 # XXX this has to stay here! TODO, work out why,
182 # but Simulation-only fails without it
183 intclk
= ClockSignal("coresync")
184 comb
+= intclk
.eq(ClockSignal())
185 dbgclk
= ClockSignal("dbgsync")
186 comb
+= dbgclk
.eq(ClockSignal())
188 # nmigen Simulation - everything runs around this, so it
189 # still has to be created.
195 ###### PREPARATION PHASE AT START OF RUNNING #######
197 for runner
in state_list
:
198 yield from runner
.setup_during_test()
200 # get each test, completely reset the core, and run it
202 for test
in self
.test_data
:
204 with self
.subTest(test
.name
):
206 ###### PREPARATION PHASE AT START OF TEST #######
208 # HACK: if there is test memory and wb_get is in use,
209 # overwrite (reset) the wb_get memory dictionary with
210 # the test's memory contents (oh, and put the wb_get
211 # memory back in as well)
212 self
.default_mem
.clear()
213 if self
.rom
is not None:
214 self
.default_mem
.update(deepcopy(self
.rom
))
215 if test
.mem
is not None:
216 self
.default_mem
.update(deepcopy(test
.mem
))
218 for runner
in state_list
:
219 yield from runner
.prepare_for_test(test
)
222 program
= test
.program
223 print("regs", test
.regs
)
224 print("sprs", test
.sprs
)
226 print("mem", test
.mem
)
227 print("msr", test
.msr
)
228 print("assem", program
.assembly
)
229 gen
= list(program
.generate_instructions())
230 insncode
= program
.assembly
.splitlines()
231 instructions
= list(zip(gen
, insncode
))
233 ###### RUNNING OF EACH TEST #######
234 # StateRunner.step_test()
236 # Run two tests (TODO, move these to functions)
237 # * first the Simulator, collate a batch of results
238 # * then the HDL, likewise
239 # (actually, the other way round because running
240 # Simulator somehow modifies the test state!)
241 # * finally, compare all the results
243 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
249 hdl_states
= yield from hdlrun
.run_test(instructions
)
256 sim_states
= yield from simrun
.run_test(
260 ###### COMPARING THE TESTS #######
266 # TODO: here just grab one entry from list_of_sim_runners
267 # (doesn't matter which one, honestly)
268 # TODO https://bugs.libre-soc.org/show_bug.cgi?id=686#c73
271 last_sim
= copy(sim_states
[-1])
273 last_sim
= copy(hdl_states
[-1])
275 last_sim
= None # err what are you doing??
279 for state
in hdl_states
:
284 for state
in sim_states
:
288 if self
.run_hdl
and self
.run_sim
:
289 # if allow_overlap is enabled, because allow_overlap
290 # can commit out-of-order, only compare the last ones
291 if self
.allow_overlap
:
292 print ("allow_overlap: truncating %d %d "
293 "states to last" % (len(sim_states
),
295 sim_states
= sim_states
[-1:]
296 hdl_states
= hdl_states
[-1:]
297 sim_states
[-1].dump_state_tofile()
298 print ("allow_overlap: last hdl_state")
299 hdl_states
[-1].dump_state_tofile()
300 for simstate
, hdlstate
in zip(sim_states
, hdl_states
):
301 simstate
.compare(hdlstate
) # register check
302 simstate
.compare_mem(hdlstate
) # memory check
304 # if no expected, create /tmp/case_name.py with code
305 # setting expected state to last_sim
306 if test
.expected
is None:
307 last_sim
.dump_state_tofile(test
.name
, test
.test_file
)
309 # compare against expected results
310 if test
.expected
is not None:
311 # have to put these in manually
312 test
.expected
.to_test
= test
.expected
313 test
.expected
.dut
= self
314 test
.expected
.state_type
= "expected"
315 test
.expected
.code
= 0
316 # do actual comparison, against last item
317 last_sim
.compare(test
.expected
)
319 # check number of instructions run (sanity)
320 if self
.run_hdl
and self
.run_sim
:
321 n_hdl
= len(hdl_states
)
322 n_sim
= len(sim_states
)
323 self
.assertTrue(n_hdl
== n_sim
,
324 "number of instructions %d %d "
325 "run not the same" % (n_hdl
, n_sim
))
327 ###### END OF A TEST #######
328 # StateRunner.end_test()
330 for runner
in state_list
:
331 yield from runner
.end_test() # TODO, some arguments?
333 ###### END OF EVERYTHING (but none needs doing, still call fn) ####
334 # StateRunner.cleanup()
336 for runner
in state_list
:
337 yield from runner
.cleanup() # TODO, some arguments?
339 # finally stop wb_get from going
340 if self
.rom
is not None:
344 'dec': {'base': 'dec'},
345 'bin': {'base': 'bin'},
346 'closed': {'closed': True}
351 ('state machines', 'closed', [
352 'fetch_pc_i_valid', 'fetch_pc_o_ready',
354 'fetch_insn_o_valid', 'fetch_insn_i_ready',
355 'pred_insn_i_valid', 'pred_insn_o_ready',
356 'fetch_predicate_state',
357 'pred_mask_o_valid', 'pred_mask_i_ready',
359 'exec_insn_i_valid', 'exec_insn_o_ready',
361 'exec_pc_o_valid', 'exec_pc_i_ready',
362 'insn_done', 'core_stop_o', 'pc_i_ok', 'pc_changed',
363 'is_last', 'dec2.no_out_vec']),
364 {'comment': 'fetch and decode'},
366 'cia[63:0]', 'nia[63:0]', 'pc[63:0]', 'msr[63:0]',
367 'cur_pc[63:0]', 'core_core_cia[63:0]']),
369 'raw_opcode_in[31:0]', 'insn_type', 'dec2.dec2_exc_happened',
370 ('svp64 decoding', 'closed', [
371 'svp64_rm[23:0]', ('dec2.extra[8:0]', 'bin'),
372 'dec2.sv_rm_dec.mode', 'dec2.sv_rm_dec.predmode',
373 'dec2.sv_rm_dec.ptype_in',
374 'dec2.sv_rm_dec.dstpred[2:0]', 'dec2.sv_rm_dec.srcpred[2:0]',
375 'dstmask[63:0]', 'srcmask[63:0]',
376 'dregread[4:0]', 'dinvert',
377 'sregread[4:0]', 'sinvert',
378 'core.int.pred__addr[4:0]', 'core.int.pred__data_o[63:0]',
379 'core.int.pred__ren']),
380 ('register augmentation', 'dec', 'closed', [
381 {'comment': 'v3.0b registers'},
382 'dec2.dec_o.RT[4:0]',
383 'dec2.dec_a.RA[4:0]',
384 'dec2.dec_b.RB[4:0]',
386 'dec2.o_svdec.reg_in[4:0]',
387 ('dec2.o_svdec.spec[2:0]', 'bin'),
388 'dec2.o_svdec.reg_out[6:0]']),
390 'dec2.in1_svdec.reg_in[4:0]',
391 ('dec2.in1_svdec.spec[2:0]', 'bin'),
392 'dec2.in1_svdec.reg_out[6:0]']),
394 'dec2.in2_svdec.reg_in[4:0]',
395 ('dec2.in2_svdec.spec[2:0]', 'bin'),
396 'dec2.in2_svdec.reg_out[6:0]']),
397 {'comment': 'SVP64 registers'},
398 'dec2.rego[6:0]', 'dec2.reg1[6:0]', 'dec2.reg2[6:0]'
400 {'comment': 'svp64 context'},
401 'core_core_vl[6:0]', 'core_core_maxvl[6:0]',
402 'core_core_srcstep[6:0]', 'next_srcstep[6:0]',
403 'core_core_dststep[6:0]',
404 {'comment': 'issue and execute'},
405 'core.core_core_insn_type',
407 'core_rego[6:0]', 'core_reg1[6:0]', 'core_reg2[6:0]']),
410 'dbg.dmi_req_i', 'dbg.dmi_ack_o',
411 {'comment': 'instruction memory'},
412 'imem.sram.rdport.memory(0)[63:0]',
413 {'comment': 'registers'},
414 # match with soc.regfile.regfiles.IntRegs port names
415 'core.int.rp_src1.memory(0)[63:0]',
416 'core.int.rp_src1.memory(1)[63:0]',
417 'core.int.rp_src1.memory(2)[63:0]',
418 'core.int.rp_src1.memory(3)[63:0]',
419 'core.int.rp_src1.memory(4)[63:0]',
420 'core.int.rp_src1.memory(5)[63:0]',
421 'core.int.rp_src1.memory(6)[63:0]',
422 'core.int.rp_src1.memory(7)[63:0]',
423 'core.int.rp_src1.memory(9)[63:0]',
424 'core.int.rp_src1.memory(10)[63:0]',
425 'core.int.rp_src1.memory(13)[63:0]',
426 # Exceptions: see list archive for description of the chain
427 # http://lists.libre-soc.org/pipermail/libre-soc-dev/2021-December/004220.html
428 ('exceptions', 'closed', [
430 'pdecode2.exc_happened',
432 'core.fus.ldst0.exc_o_happened']),
435 # PortInterface module path varies depending on MMU option
436 if self
.microwatt_mmu
:
437 pi_module
= 'core.ldst0'
439 pi_module
= 'core.fus.ldst0'
441 traces
+= [('ld/st port interface', {'submodule': pi_module
}, [
444 'ldst_port0_is_ld_i',
445 'ldst_port0_is_st_i',
447 'ldst_port0_addr_i[47:0]',
448 'ldst_port0_addr_i_ok',
449 'ldst_port0_addr_ok_o',
450 'ldst_port0_exc_happened',
451 'ldst_port0_st_data_i[63:0]',
452 'ldst_port0_st_data_i_ok',
453 'ldst_port0_ld_data_o[63:0]',
454 'ldst_port0_ld_data_o_ok',
460 if self
.microwatt_mmu
:
462 {'comment': 'microwatt_mmu'},
463 'core.fus.mmu0.alu_mmu0.illegal',
464 'core.fus.mmu0.alu_mmu0.debug0[3:0]',
465 'core.fus.mmu0.alu_mmu0.mmu.state',
466 'core.fus.mmu0.alu_mmu0.mmu.pid[31:0]',
467 'core.fus.mmu0.alu_mmu0.mmu.prtbl[63:0]',
468 {'comment': 'wishbone_memory'},
469 'core.l0.pimem.bus__ack',
470 'core.l0.pimem.bus__adr[4:0]',
471 'core.l0.pimem.bus__bte',
472 'core.l0.pimem.bus__cti',
473 'core.l0.pimem.bus__cyc',
474 'core.l0.pimem.bus__dat_r[63:0]',
475 'core.l0.pimem.bus__dat_w[63:0]',
476 'core.l0.pimem.bus__dat_err',
477 'core.l0.pimem.bus__dat_sel[7:0]',
478 'core.l0.pimem.bus__dat_stb',
479 'core.l0.pimem.bus__dat_we',
482 gtkname
= "issuer_simulator"
486 write_gtkw("%s.gtkw" % gtkname
,
488 traces
, styles
, module
='top.issuer')
490 # add run of instructions
491 sim
.add_sync_process(process
)
493 # ARGH oh whoops. TODO, core is not passed in!
494 # urrr... work out a hacky-way to sort this (access run_hdl
495 # core directly for now)
497 # optionally, if a wishbone-based ROM is passed in, run that as an
498 # extra emulated process
499 if self
.rom
is not None:
500 print ("TestRunner with MMU ROM")
502 dcache
= hdlrun
.issuer
.core
.fus
.fus
["mmu0"].alu
.dcache
503 icache
= hdlrun
.issuer
.core
.fus
.fus
["mmu0"].alu
.icache
504 self
.default_mem
= deepcopy(self
.rom
)
505 sim
.add_sync_process(wrap(wb_get(dcache
.bus
,
506 self
.default_mem
, "DCACHE")))
507 sim
.add_sync_process(wrap(wb_get(icache
.ibus
,
508 self
.default_mem
, "ICACHE")))
510 with sim
.write_vcd("%s.vcd" % gtkname
):