src/panfrost/bifrost/bi_lower_combine.c

   1 /*
   2  * Copyright (C) 2020 Collabora, Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #include "compiler.h"
  25
  26 /* NIR creates vectors as vecN ops, which we represent by a synthetic
  27  * BI_COMBINE instruction, e.g.:
  28  *
  29  *      v = combine x, y, z, w
  30  *
  31  * These combines need to be lowered by the pass in this file. Fix a given
  32  * source at component c.
  33  *
  34  * First suppose the source is SSA. If it is also scalar, then we may rewrite
  35  * the destination of the generating instruction (unique by SSA+scalar) to
  36  * write to v.c, and rewrite each of its uses to swizzle out .c instead of .x
  37  * (the original by scalar). If it is vector, there are two cases. If the
  38  * component c is `x`, we are accessing v.x, and each of the succeeding
  39  * components y, z... up to the last component of the vector are accessed
  40  * sequentially, then we may perform the same rewrite. If this is not the case,
  41  * rewriting would require more complex vector features, so we fallback on a
  42  * move.
  43  *
  44  * Otherwise is the source is not SSA, we also fallback on a move. We could
  45  * probably do better.
  46  */
  47
  48 static void
  49 bi_combine_mov32(bi_context *ctx, bi_instruction *parent, unsigned comp, unsigned R)
  50 {
  51         bi_instruction move = {
  52                 .type = BI_MOV,
  53                 .dest = R,
  54                 .dest_type = nir_type_uint32,
  55                 .dest_offset = comp,
  56                 .src = { parent->src[comp] },
  57                 .src_types = { nir_type_uint32 },
  58                 .swizzle = { { parent->swizzle[comp][0] } }
  59         };
  60
  61         bi_emit_before(ctx, parent, move);
  62 }
  63
  64 /* Gets the instruction generating a given source. Combine lowering is
  65  * accidentally O(n^2) right now because this function is O(n) instead of O(1).
  66  * If this pass is slow, this cost can be avoided in favour for better
  67  * bookkeeping. */
  68
  69 static bi_instruction *
  70 bi_get_parent(bi_context *ctx, unsigned idx)
  71 {
  72         bi_foreach_instr_global(ctx, ins) {
  73                 if (ins->dest == idx)
  74                         return ins;
  75         }
  76
  77         return NULL;
  78 }
  79
  80 /* Rewrites uses of an index. Again, this could be O(n) to the program but is
  81  * currently O(nc) to the program and number of combines, so the pass becomes
  82  * effectively O(n^2). Better bookkeeping would bring down to linear if that's
  83  * an issue. */
  84
  85 static void
  86 bi_rewrite_uses(bi_context *ctx,
  87                 unsigned old, unsigned oldc,
  88                 unsigned new, unsigned newc)
  89 {
  90         bi_foreach_instr_global(ctx, ins) {
  91                 bi_foreach_src(ins, s) {
  92                         if (ins->src[s] != old) continue;
  93
  94                         for (unsigned i = 0; i < 16; ++i)
  95                                 ins->swizzle[s][i] += (newc - oldc);
  96
  97                         ins->src[s] = new;
  98                 }
  99         }
 100 }
 101
 102 /* Checks if we have a nicely aligned vector prefix */
 103
 104 static bool
 105 bi_is_aligned_vec32(bi_instruction *combine, unsigned s, bi_instruction *io,
 106                 unsigned *count)
 107 {
 108         /* We only support prefixes */
 109         if (s != 0)
 110                 return false;
 111
 112         if (!(bi_class_props[io->type] & BI_VECTOR))
 113                 return false;
 114
 115         if (nir_alu_type_get_type_size(combine->dest_type) != 32)
 116                 return false;
 117
 118         if (nir_alu_type_get_type_size(io->dest_type) != 32)
 119                 return false;
 120
 121         unsigned components = io->vector_channels;
 122
 123         /* Are we contiguous like that? */
 124
 125         for (unsigned i = 0; i < components; ++i) {
 126                 if (combine->src[i] != io->dest)
 127                         return false;
 128
 129                 if (combine->swizzle[i][0] != i)
 130                         return false;
 131         }
 132
 133         /* We're good to go */
 134         *count = components;
 135         return true;
 136 }
 137
 138 #if 0
 139 /* Tries to lower a given source of a combine to an appropriate rewrite,
 140  * returning true if successful, and false with no changes otherwise. */
 141
 142 static bool
 143 bi_lower_combine_src(bi_context *ctx, bi_instruction *ins, unsigned s, unsigned R,
 144                 unsigned *vec_count)
 145 {
 146         unsigned src = ins->src[s];
 147
 148         /* We currently only handle SSA */
 149
 150         if (!src) return false;
 151         if (src & (BIR_SPECIAL | BIR_IS_REG)) return false;
 152
 153         /* We are SSA. Lookup the generating instruction. */
 154         unsigned bytes = nir_alu_type_get_type_size(ins->dest_type) / 8;
 155
 156         bi_instruction *parent = bi_get_parent(ctx, src,
 157                          0xF << (ins->swizzle[s][0] * bytes));
 158
 159         if (!parent) return false;
 160
 161         /* We have a parent instuction, sanity check the typesize */
 162         unsigned pbytes = nir_alu_type_get_type_size(parent->dest_type) / 8;
 163         if (pbytes != bytes) return false;
 164
 165         bool scalar = parent->vector_channels != 0;
 166         if (!(scalar || bi_is_aligned_vec(ins, s, parent, vec_count))) return false;
 167
 168         if (!bi_shift_mask(parent, bytes * s)) return false;
 169         bi_rewrite_uses(ctx, parent->dest, 0, R, s);
 170         parent->dest = R;
 171         return true;
 172 }
 173 #endif
 174
 175 void
 176 bi_lower_combine(bi_context *ctx, bi_block *block)
 177 {
 178         bi_foreach_instr_in_block_safe(block, ins) {
 179                 if (ins->type != BI_COMBINE) continue;
 180
 181                 unsigned R = bi_make_temp_reg(ctx);
 182
 183                 bi_foreach_src(ins, s) {
 184                         /* We're done early for vec2/3 */
 185                         if (!ins->src[s])
 186                                 continue;
 187
 188 #if 0
 189                         unsigned vec_count = 0;
 190
 191                         if (bi_lower_combine_src(ctx, ins, s, R, &vec_count)) {
 192                                 /* Skip vectored sources */
 193                                 if (vec_count)
 194                                         s += (vec_count - 1);
 195                         } else {
 196                                 bi_insert_combine_mov(ctx, ins, s, R);
 197                         }
 198 #endif
 199                         bi_combine_mov32(ctx, ins, s, R);
 200                 }
 201
 202
 203                 bi_rewrite_uses(ctx, ins->dest, 0, R, 0);
 204                 bi_remove_instruction(ins);
 205         }
 206 }