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pan/bi: Add missing BI_VECTOR
[mesa.git] / src / panfrost / bifrost / bifrost_compile.c
1 /*
2 * Copyright (C) 2020 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #include "main/mtypes.h"
28 #include "compiler/glsl/glsl_to_nir.h"
29 #include "compiler/nir_types.h"
30 #include "compiler/nir/nir_builder.h"
31
32 #include "disassemble.h"
33 #include "bifrost_compile.h"
34 #include "bifrost_nir.h"
35 #include "compiler.h"
36 #include "bi_quirks.h"
37 #include "bi_print.h"
38
39 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
40 static bi_instruction *bi_emit_branch(bi_context *ctx);
41 static void bi_schedule_barrier(bi_context *ctx);
42
43 static void
44 emit_jump(bi_context *ctx, nir_jump_instr *instr)
45 {
46 bi_instruction *branch = bi_emit_branch(ctx);
47
48 switch (instr->type) {
49 case nir_jump_break:
50 branch->branch.target = ctx->break_block;
51 break;
52 case nir_jump_continue:
53 branch->branch.target = ctx->continue_block;
54 break;
55 default:
56 unreachable("Unhandled jump type");
57 }
58
59 pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
60 }
61
62 /* Gets a bytemask for a complete vecN write */
63 static unsigned
64 bi_mask_for_channels_32(unsigned i)
65 {
66 return (1 << (4 * i)) - 1;
67 }
68
69 static bi_instruction
70 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
71 {
72 bi_instruction load = {
73 .type = T,
74 .writemask = bi_mask_for_channels_32(instr->num_components),
75 .src = { BIR_INDEX_CONSTANT },
76 .src_types = { nir_type_uint32 },
77 .constant = { .u64 = nir_intrinsic_base(instr) },
78 };
79
80 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
81
82 if (info->has_dest)
83 load.dest = bir_dest_index(&instr->dest);
84
85 if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
86 load.dest_type = nir_intrinsic_type(instr);
87
88 nir_src *offset = nir_get_io_offset_src(instr);
89
90 if (nir_src_is_const(*offset))
91 load.constant.u64 += nir_src_as_uint(*offset);
92 else
93 load.src[0] = bir_src_index(offset);
94
95 return load;
96 }
97
98 static void
99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
100 {
101 bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
102 ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
103 ins.load_vary.reuse = false; /* TODO */
104 ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
105 ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
106
107 if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
108 /* Zero it out for direct */
109 ins.src[1] = BIR_INDEX_ZERO;
110 } else {
111 /* R61 contains sample mask stuff, TODO RA XXX */
112 ins.src[1] = BIR_INDEX_REGISTER | 61;
113 }
114
115 bi_emit(ctx, ins);
116 }
117
118 static void
119 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
120 {
121 if (!ctx->emitted_atest) {
122 bi_instruction ins = {
123 .type = BI_ATEST,
124 .src = {
125 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
126 bir_src_index(&instr->src[0])
127 },
128 .src_types = {
129 nir_type_uint32,
130 nir_intrinsic_type(instr)
131 },
132 .swizzle = {
133 { 0 },
134 { 3, 0 } /* swizzle out the alpha */
135 },
136 .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
137 .dest_type = nir_type_uint32,
138 .writemask = 0xF
139 };
140
141 bi_emit(ctx, ins);
142 bi_schedule_barrier(ctx);
143 ctx->emitted_atest = true;
144 }
145
146 bi_instruction blend = {
147 .type = BI_BLEND,
148 .blend_location = nir_intrinsic_base(instr),
149 .src = {
150 bir_src_index(&instr->src[0]),
151 BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
152 },
153 .src_types = {
154 nir_intrinsic_type(instr),
155 nir_type_uint32
156 },
157 .swizzle = {
158 { 0, 1, 2, 3 },
159 { 0 }
160 },
161 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
162 .dest_type = nir_type_uint32,
163 .writemask = 0xF
164 };
165
166 assert(blend.blend_location < 8);
167 assert(ctx->blend_types);
168 ctx->blend_types[blend.blend_location] = blend.src_types[0];
169
170 bi_emit(ctx, blend);
171 bi_schedule_barrier(ctx);
172 }
173
174 static bi_instruction
175 bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
176 {
177 bi_instruction ld = bi_load(T, instr);
178 ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
179 ld.src[2] = BIR_INDEX_REGISTER | 62;
180 ld.src[3] = 0;
181 ld.src_types[1] = nir_type_uint32;
182 ld.src_types[2] = nir_type_uint32;
183 ld.src_types[3] = nir_intrinsic_type(instr);
184 return ld;
185 }
186
187 static void
188 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
189 {
190 bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
191 address.dest = bi_make_temp(ctx);
192 address.dest_type = nir_type_uint32;
193 address.writemask = (1 << 12) - 1;
194
195 unsigned nr = nir_intrinsic_src_components(instr, 0);
196 assert(nir_intrinsic_write_mask(instr) == ((1 << nr) - 1));
197
198 bi_instruction st = {
199 .type = BI_STORE_VAR,
200 .src = {
201 bir_src_index(&instr->src[0]),
202 address.dest, address.dest, address.dest,
203 },
204 .src_types = {
205 nir_type_uint32,
206 nir_type_uint32, nir_type_uint32, nir_type_uint32,
207 },
208 .swizzle = {
209 { 0 },
210 { 0 }, { 1 }, { 2}
211 },
212 .store_channels = nr,
213 };
214
215 for (unsigned i = 0; i < nr; ++i)
216 st.swizzle[0][i] = i;
217
218 bi_emit(ctx, address);
219 bi_emit(ctx, st);
220 }
221
222 static void
223 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
224 {
225 bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
226 ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
227
228 /* TODO: Indirect access, since we need to multiply by the element
229 * size. I believe we can get this lowering automatically via
230 * nir_lower_io (as mul instructions) with the proper options, but this
231 * is TODO */
232 assert(ld.src[0] & BIR_INDEX_CONSTANT);
233 ld.constant.u64 += ctx->sysvals.sysval_count;
234 ld.constant.u64 *= 16;
235
236 bi_emit(ctx, ld);
237 }
238
239 static void
240 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
241 unsigned nr_components, unsigned offset)
242 {
243 nir_dest nir_dest;
244
245 /* Figure out which uniform this is */
246 int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
247 void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
248
249 /* Sysvals are prefix uniforms */
250 unsigned uniform = ((uintptr_t) val) - 1;
251
252 /* Emit the read itself -- this is never indirect */
253
254 bi_instruction load = {
255 .type = BI_LOAD_UNIFORM,
256 .writemask = (1 << (nr_components * 4)) - 1,
257 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
258 .src_types = { nir_type_uint32, nir_type_uint32 },
259 .constant = { (uniform * 16) + offset },
260 .dest = bir_dest_index(&nir_dest),
261 .dest_type = nir_type_uint32, /* TODO */
262 };
263
264 bi_emit(ctx, load);
265 }
266
267 static void
268 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
269 {
270
271 switch (instr->intrinsic) {
272 case nir_intrinsic_load_barycentric_pixel:
273 /* stub */
274 break;
275 case nir_intrinsic_load_interpolated_input:
276 case nir_intrinsic_load_input:
277 if (ctx->stage == MESA_SHADER_FRAGMENT)
278 bi_emit_ld_vary(ctx, instr);
279 else if (ctx->stage == MESA_SHADER_VERTEX)
280 bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
281 else {
282 unreachable("Unsupported shader stage");
283 }
284 break;
285
286 case nir_intrinsic_store_output:
287 if (ctx->stage == MESA_SHADER_FRAGMENT)
288 bi_emit_frag_out(ctx, instr);
289 else if (ctx->stage == MESA_SHADER_VERTEX)
290 bi_emit_st_vary(ctx, instr);
291 else
292 unreachable("Unsupported shader stage");
293 break;
294
295 case nir_intrinsic_load_uniform:
296 bi_emit_ld_uniform(ctx, instr);
297 break;
298
299 case nir_intrinsic_load_ssbo_address:
300 bi_emit_sysval(ctx, &instr->instr, 1, 0);
301 break;
302
303 case nir_intrinsic_get_buffer_size:
304 bi_emit_sysval(ctx, &instr->instr, 1, 8);
305 break;
306
307 case nir_intrinsic_load_viewport_scale:
308 case nir_intrinsic_load_viewport_offset:
309 case nir_intrinsic_load_num_work_groups:
310 case nir_intrinsic_load_sampler_lod_parameters_pan:
311 bi_emit_sysval(ctx, &instr->instr, 3, 0);
312 break;
313
314 default:
315 /* todo */
316 break;
317 }
318 }
319
320 static void
321 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
322 {
323 /* Make sure we've been lowered */
324 assert(instr->def.num_components == 1);
325
326 bi_instruction move = {
327 .type = BI_MOV,
328 .dest = bir_ssa_index(&instr->def),
329 .dest_type = instr->def.bit_size | nir_type_uint,
330 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
331 .src = {
332 BIR_INDEX_CONSTANT
333 },
334 .src_types = {
335 instr->def.bit_size | nir_type_uint,
336 },
337 .constant = {
338 .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
339 }
340 };
341
342 bi_emit(ctx, move);
343 }
344
345 #define BI_CASE_CMP(op) \
346 case op##8: \
347 case op##16: \
348 case op##32: \
349
350 static enum bi_class
351 bi_class_for_nir_alu(nir_op op)
352 {
353 switch (op) {
354 case nir_op_iadd:
355 case nir_op_fadd:
356 case nir_op_fsub:
357 return BI_ADD;
358 case nir_op_isub:
359 return BI_ISUB;
360
361 BI_CASE_CMP(nir_op_flt)
362 BI_CASE_CMP(nir_op_fge)
363 BI_CASE_CMP(nir_op_feq)
364 BI_CASE_CMP(nir_op_fne)
365 BI_CASE_CMP(nir_op_ilt)
366 BI_CASE_CMP(nir_op_ige)
367 BI_CASE_CMP(nir_op_ieq)
368 BI_CASE_CMP(nir_op_ine)
369 return BI_CMP;
370
371 case nir_op_b8csel:
372 case nir_op_b16csel:
373 case nir_op_b32csel:
374 return BI_CSEL;
375
376 case nir_op_i2i8:
377 case nir_op_i2i16:
378 case nir_op_i2i32:
379 case nir_op_i2i64:
380 case nir_op_u2u8:
381 case nir_op_u2u16:
382 case nir_op_u2u32:
383 case nir_op_u2u64:
384 case nir_op_f2i16:
385 case nir_op_f2i32:
386 case nir_op_f2i64:
387 case nir_op_f2u16:
388 case nir_op_f2u32:
389 case nir_op_f2u64:
390 case nir_op_i2f16:
391 case nir_op_i2f32:
392 case nir_op_i2f64:
393 case nir_op_u2f16:
394 case nir_op_u2f32:
395 case nir_op_u2f64:
396 case nir_op_f2f16:
397 case nir_op_f2f32:
398 case nir_op_f2f64:
399 case nir_op_f2fmp:
400 return BI_CONVERT;
401
402 case nir_op_vec2:
403 case nir_op_vec3:
404 case nir_op_vec4:
405 return BI_COMBINE;
406
407 case nir_op_vec8:
408 case nir_op_vec16:
409 unreachable("should've been lowered");
410
411 case nir_op_ffma:
412 case nir_op_fmul:
413 return BI_FMA;
414
415 case nir_op_imin:
416 case nir_op_imax:
417 case nir_op_umin:
418 case nir_op_umax:
419 case nir_op_fmin:
420 case nir_op_fmax:
421 return BI_MINMAX;
422
423 case nir_op_fsat:
424 case nir_op_fneg:
425 case nir_op_fabs:
426 return BI_FMOV;
427 case nir_op_mov:
428 return BI_MOV;
429
430 case nir_op_fround_even:
431 case nir_op_fceil:
432 case nir_op_ffloor:
433 case nir_op_ftrunc:
434 return BI_ROUND;
435
436 case nir_op_frcp:
437 case nir_op_frsq:
438 return BI_SPECIAL;
439
440 default:
441 unreachable("Unknown ALU op");
442 }
443 }
444
445 /* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
446 * return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
447 * optimizations). Otherwise it will bail (when used for primary code
448 * generation). */
449
450 static enum bi_cond
451 bi_cond_for_nir(nir_op op, bool soft)
452 {
453 switch (op) {
454 BI_CASE_CMP(nir_op_flt)
455 BI_CASE_CMP(nir_op_ilt)
456 return BI_COND_LT;
457
458 BI_CASE_CMP(nir_op_fge)
459 BI_CASE_CMP(nir_op_ige)
460 return BI_COND_GE;
461
462 BI_CASE_CMP(nir_op_feq)
463 BI_CASE_CMP(nir_op_ieq)
464 return BI_COND_EQ;
465
466 BI_CASE_CMP(nir_op_fne)
467 BI_CASE_CMP(nir_op_ine)
468 return BI_COND_NE;
469 default:
470 if (soft)
471 return BI_COND_ALWAYS;
472 else
473 unreachable("Invalid compare");
474 }
475 }
476
477 static void
478 bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
479 unsigned *constants_left, unsigned *constant_shift)
480 {
481 unsigned bits = nir_src_bit_size(instr->src[i].src);
482 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
483
484 alu->src_types[to] = nir_op_infos[instr->op].input_types[i]
485 | bits;
486
487 /* Try to inline a constant */
488 if (nir_src_is_const(instr->src[i].src) && *constants_left && (dest_bits == bits)) {
489 uint64_t mask = (1ull << dest_bits) - 1;
490 uint64_t cons = nir_src_as_uint(instr->src[i].src);
491
492 /* Try to reuse a constant */
493 for (unsigned i = 0; i < (*constant_shift); i += dest_bits) {
494 if (((alu->constant.u64 >> i) & mask) == cons) {
495 alu->src[to] = BIR_INDEX_CONSTANT | i;
496 return;
497 }
498 }
499
500 alu->constant.u64 |= cons << *constant_shift;
501 alu->src[to] = BIR_INDEX_CONSTANT | (*constant_shift);
502 --(*constants_left);
503 (*constant_shift) += MAX2(dest_bits, 32); /* lo/hi */
504 return;
505 }
506
507 alu->src[to] = bir_src_index(&instr->src[i].src);
508
509 /* We assert scalarization above */
510 alu->swizzle[to][0] = instr->src[i].swizzle[0];
511 }
512
513 static void
514 bi_fuse_csel_cond(bi_instruction *csel, nir_alu_src cond,
515 unsigned *constants_left, unsigned *constant_shift)
516 {
517 /* Bail for vector weirdness */
518 if (cond.swizzle[0] != 0)
519 return;
520
521 if (!cond.src.is_ssa)
522 return;
523
524 nir_ssa_def *def = cond.src.ssa;
525 nir_instr *parent = def->parent_instr;
526
527 if (parent->type != nir_instr_type_alu)
528 return;
529
530 nir_alu_instr *alu = nir_instr_as_alu(parent);
531
532 /* Try to match a condition */
533 enum bi_cond bcond = bi_cond_for_nir(alu->op, true);
534
535 if (bcond == BI_COND_ALWAYS)
536 return;
537
538 /* We found one, let's fuse it in */
539 csel->csel_cond = bcond;
540 bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift);
541 bi_copy_src(csel, alu, 1, 1, constants_left, constant_shift);
542 }
543
544 static void
545 emit_alu(bi_context *ctx, nir_alu_instr *instr)
546 {
547 /* Try some special functions */
548 switch (instr->op) {
549 case nir_op_fexp2:
550 bi_emit_fexp2(ctx, instr);
551 return;
552 case nir_op_flog2:
553 bi_emit_flog2(ctx, instr);
554 return;
555 default:
556 break;
557 }
558
559 /* Otherwise, assume it's something we can handle normally */
560 bi_instruction alu = {
561 .type = bi_class_for_nir_alu(instr->op),
562 .dest = bir_dest_index(&instr->dest.dest),
563 .dest_type = nir_op_infos[instr->op].output_type
564 | nir_dest_bit_size(instr->dest.dest),
565 };
566
567 /* TODO: Implement lowering of special functions for older Bifrost */
568 assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
569
570 if (instr->dest.dest.is_ssa) {
571 /* Construct a writemask */
572 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
573 unsigned comps = instr->dest.dest.ssa.num_components;
574
575 if (alu.type != BI_COMBINE)
576 assert(comps == 1);
577
578 unsigned bits = bits_per_comp * comps;
579 unsigned bytes = bits / 8;
580 alu.writemask = (1 << bytes) - 1;
581 } else {
582 unsigned comp_mask = instr->dest.write_mask;
583
584 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
585 comp_mask);
586 }
587
588 /* We inline constants as we go. This tracks how many constants have
589 * been inlined, since we're limited to 64-bits of constants per
590 * instruction */
591
592 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
593 unsigned constants_left = (64 / dest_bits);
594 unsigned constant_shift = 0;
595
596 if (alu.type == BI_COMBINE)
597 constants_left = 0;
598
599 /* Copy sources */
600
601 unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
602 assert(num_inputs <= ARRAY_SIZE(alu.src));
603
604 for (unsigned i = 0; i < num_inputs; ++i) {
605 unsigned f = 0;
606
607 if (i && alu.type == BI_CSEL)
608 f++;
609
610 bi_copy_src(&alu, instr, i, i + f, &constants_left, &constant_shift);
611 }
612
613 /* Op-specific fixup */
614 switch (instr->op) {
615 case nir_op_fmul:
616 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
617 alu.src_types[2] = alu.src_types[1];
618 break;
619 case nir_op_fsat:
620 alu.outmod = BIFROST_SAT; /* FMOV */
621 break;
622 case nir_op_fneg:
623 alu.src_neg[0] = true; /* FMOV */
624 break;
625 case nir_op_fabs:
626 alu.src_abs[0] = true; /* FMOV */
627 break;
628 case nir_op_fsub:
629 alu.src_neg[1] = true; /* FADD */
630 break;
631 case nir_op_fmax:
632 case nir_op_imax:
633 case nir_op_umax:
634 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
635 break;
636 case nir_op_frcp:
637 alu.op.special = BI_SPECIAL_FRCP;
638 break;
639 case nir_op_frsq:
640 alu.op.special = BI_SPECIAL_FRSQ;
641 break;
642 BI_CASE_CMP(nir_op_flt)
643 BI_CASE_CMP(nir_op_ilt)
644 BI_CASE_CMP(nir_op_fge)
645 BI_CASE_CMP(nir_op_ige)
646 BI_CASE_CMP(nir_op_feq)
647 BI_CASE_CMP(nir_op_ieq)
648 BI_CASE_CMP(nir_op_fne)
649 BI_CASE_CMP(nir_op_ine)
650 alu.op.compare = bi_cond_for_nir(instr->op, false);
651 break;
652 case nir_op_fround_even:
653 alu.op.round = BI_ROUND_MODE;
654 alu.roundmode = BIFROST_RTE;
655 break;
656 case nir_op_fceil:
657 alu.op.round = BI_ROUND_MODE;
658 alu.roundmode = BIFROST_RTP;
659 break;
660 case nir_op_ffloor:
661 alu.op.round = BI_ROUND_MODE;
662 alu.roundmode = BIFROST_RTN;
663 break;
664 case nir_op_ftrunc:
665 alu.op.round = BI_ROUND_MODE;
666 alu.roundmode = BIFROST_RTZ;
667 break;
668 default:
669 break;
670 }
671
672 if (alu.type == BI_CSEL) {
673 /* Default to csel3 */
674 alu.csel_cond = BI_COND_NE;
675 alu.src[1] = BIR_INDEX_ZERO;
676 alu.src_types[1] = alu.src_types[0];
677
678 bi_fuse_csel_cond(&alu, instr->src[0],
679 &constants_left, &constant_shift);
680 }
681
682 bi_emit(ctx, alu);
683 }
684
685 /* TEX_COMPACT instructions assume normal 2D f32 operation but are more
686 * space-efficient and with simpler RA/scheduling requirements*/
687
688 static void
689 emit_tex_compact(bi_context *ctx, nir_tex_instr *instr)
690 {
691 /* TODO: Pipe through indices */
692 assert(instr->texture_index == 0);
693 assert(instr->sampler_index == 0);
694
695 bi_instruction tex = {
696 .type = BI_TEX,
697 .op = { .texture = BI_TEX_COMPACT },
698 .dest = bir_dest_index(&instr->dest),
699 .dest_type = instr->dest_type,
700 .src_types = { nir_type_float32, nir_type_float32 },
701 .writemask = instr->dest_type == nir_type_float32 ?
702 0xFFFF : 0xFF,
703 };
704
705 for (unsigned i = 0; i < instr->num_srcs; ++i) {
706 int index = bir_src_index(&instr->src[i].src);
707 assert (instr->src[i].src_type == nir_tex_src_coord);
708
709 tex.src[0] = index;
710 tex.src[1] = index;
711 tex.swizzle[0][0] = 0;
712 tex.swizzle[1][0] = 1;
713 }
714
715 bi_emit(ctx, tex);
716 }
717
718 static void
719 emit_tex_full(bi_context *ctx, nir_tex_instr *instr)
720 {
721 unreachable("stub");
722 }
723
724 static void
725 emit_tex(bi_context *ctx, nir_tex_instr *instr)
726 {
727 nir_alu_type base = nir_alu_type_get_base_type(instr->dest_type);
728 unsigned sz = nir_dest_bit_size(instr->dest);
729 instr->dest_type = base | sz;
730
731 bool is_normal = instr->op == nir_texop_tex;
732 bool is_2d = instr->sampler_dim == GLSL_SAMPLER_DIM_2D ||
733 instr->sampler_dim == GLSL_SAMPLER_DIM_EXTERNAL;
734 bool is_f = base == nir_type_float && (sz == 16 || sz == 32);
735
736 bool is_compact = is_normal && is_2d && is_f && !instr->is_shadow;
737
738 if (is_compact)
739 emit_tex_compact(ctx, instr);
740 else
741 emit_tex_full(ctx, instr);
742 }
743
744 static void
745 emit_instr(bi_context *ctx, struct nir_instr *instr)
746 {
747 switch (instr->type) {
748 case nir_instr_type_load_const:
749 emit_load_const(ctx, nir_instr_as_load_const(instr));
750 break;
751
752 case nir_instr_type_intrinsic:
753 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
754 break;
755
756 case nir_instr_type_alu:
757 emit_alu(ctx, nir_instr_as_alu(instr));
758 break;
759
760 case nir_instr_type_tex:
761 emit_tex(ctx, nir_instr_as_tex(instr));
762 break;
763
764 case nir_instr_type_jump:
765 emit_jump(ctx, nir_instr_as_jump(instr));
766 break;
767
768 case nir_instr_type_ssa_undef:
769 /* Spurious */
770 break;
771
772 default:
773 unreachable("Unhandled instruction type");
774 break;
775 }
776 }
777
778
779
780 static bi_block *
781 create_empty_block(bi_context *ctx)
782 {
783 bi_block *blk = rzalloc(ctx, bi_block);
784
785 blk->base.predecessors = _mesa_set_create(blk,
786 _mesa_hash_pointer,
787 _mesa_key_pointer_equal);
788
789 blk->base.name = ctx->block_name_count++;
790
791 return blk;
792 }
793
794 static void
795 bi_schedule_barrier(bi_context *ctx)
796 {
797 bi_block *temp = ctx->after_block;
798 ctx->after_block = create_empty_block(ctx);
799 list_addtail(&ctx->after_block->base.link, &ctx->blocks);
800 list_inithead(&ctx->after_block->base.instructions);
801 pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
802 ctx->current_block = ctx->after_block;
803 ctx->after_block = temp;
804 }
805
806 static bi_block *
807 emit_block(bi_context *ctx, nir_block *block)
808 {
809 if (ctx->after_block) {
810 ctx->current_block = ctx->after_block;
811 ctx->after_block = NULL;
812 } else {
813 ctx->current_block = create_empty_block(ctx);
814 }
815
816 list_addtail(&ctx->current_block->base.link, &ctx->blocks);
817 list_inithead(&ctx->current_block->base.instructions);
818
819 nir_foreach_instr(instr, block) {
820 emit_instr(ctx, instr);
821 ++ctx->instruction_count;
822 }
823
824 return ctx->current_block;
825 }
826
827 /* Emits an unconditional branch to the end of the current block, returning a
828 * pointer so the user can fill in details */
829
830 static bi_instruction *
831 bi_emit_branch(bi_context *ctx)
832 {
833 bi_instruction branch = {
834 .type = BI_BRANCH,
835 .branch = {
836 .cond = BI_COND_ALWAYS
837 }
838 };
839
840 return bi_emit(ctx, branch);
841 }
842
843 /* Sets a condition for a branch by examing the NIR condition. If we're
844 * familiar with the condition, we unwrap it to fold it into the branch
845 * instruction. Otherwise, we consume the condition directly. We
846 * generally use 1-bit booleans which allows us to use small types for
847 * the conditions.
848 */
849
850 static void
851 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
852 {
853 /* TODO: Try to unwrap instead of always bailing */
854 branch->src[0] = bir_src_index(cond);
855 branch->src[1] = BIR_INDEX_ZERO;
856 branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
857 branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
858 }
859
860 static void
861 emit_if(bi_context *ctx, nir_if *nif)
862 {
863 bi_block *before_block = ctx->current_block;
864
865 /* Speculatively emit the branch, but we can't fill it in until later */
866 bi_instruction *then_branch = bi_emit_branch(ctx);
867 bi_set_branch_cond(then_branch, &nif->condition, true);
868
869 /* Emit the two subblocks. */
870 bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
871 bi_block *end_then_block = ctx->current_block;
872
873 /* Emit a jump from the end of the then block to the end of the else */
874 bi_instruction *then_exit = bi_emit_branch(ctx);
875
876 /* Emit second block, and check if it's empty */
877
878 int count_in = ctx->instruction_count;
879 bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
880 bi_block *end_else_block = ctx->current_block;
881 ctx->after_block = create_empty_block(ctx);
882
883 /* Now that we have the subblocks emitted, fix up the branches */
884
885 assert(then_block);
886 assert(else_block);
887
888 if (ctx->instruction_count == count_in) {
889 /* The else block is empty, so don't emit an exit jump */
890 bi_remove_instruction(then_exit);
891 then_branch->branch.target = ctx->after_block;
892 } else {
893 then_branch->branch.target = else_block;
894 then_exit->branch.target = ctx->after_block;
895 pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
896 }
897
898 /* Wire up the successors */
899
900 pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
901
902 pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
903 pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
904 }
905
906 static void
907 emit_loop(bi_context *ctx, nir_loop *nloop)
908 {
909 /* Remember where we are */
910 bi_block *start_block = ctx->current_block;
911
912 bi_block *saved_break = ctx->break_block;
913 bi_block *saved_continue = ctx->continue_block;
914
915 ctx->continue_block = create_empty_block(ctx);
916 ctx->break_block = create_empty_block(ctx);
917 ctx->after_block = ctx->continue_block;
918
919 /* Emit the body itself */
920 emit_cf_list(ctx, &nloop->body);
921
922 /* Branch back to loop back */
923 bi_instruction *br_back = bi_emit_branch(ctx);
924 br_back->branch.target = ctx->continue_block;
925 pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
926 pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
927
928 ctx->after_block = ctx->break_block;
929
930 /* Pop off */
931 ctx->break_block = saved_break;
932 ctx->continue_block = saved_continue;
933 ++ctx->loop_count;
934 }
935
936 static bi_block *
937 emit_cf_list(bi_context *ctx, struct exec_list *list)
938 {
939 bi_block *start_block = NULL;
940
941 foreach_list_typed(nir_cf_node, node, node, list) {
942 switch (node->type) {
943 case nir_cf_node_block: {
944 bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
945
946 if (!start_block)
947 start_block = block;
948
949 break;
950 }
951
952 case nir_cf_node_if:
953 emit_if(ctx, nir_cf_node_as_if(node));
954 break;
955
956 case nir_cf_node_loop:
957 emit_loop(ctx, nir_cf_node_as_loop(node));
958 break;
959
960 default:
961 unreachable("Unknown control flow");
962 }
963 }
964
965 return start_block;
966 }
967
968 static int
969 glsl_type_size(const struct glsl_type *type, bool bindless)
970 {
971 return glsl_count_attribute_slots(type, false);
972 }
973
974 static void
975 bi_optimize_nir(nir_shader *nir)
976 {
977 bool progress;
978 unsigned lower_flrp = 16 | 32 | 64;
979
980 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
981 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
982
983 nir_lower_tex_options lower_tex_options = {
984 .lower_txs_lod = true,
985 .lower_txp = ~0,
986 .lower_tex_without_implicit_lod = true,
987 .lower_txd = true,
988 };
989
990 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
991 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
992 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
993
994 do {
995 progress = false;
996
997 NIR_PASS(progress, nir, nir_lower_var_copies);
998 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
999
1000 NIR_PASS(progress, nir, nir_copy_prop);
1001 NIR_PASS(progress, nir, nir_opt_remove_phis);
1002 NIR_PASS(progress, nir, nir_opt_dce);
1003 NIR_PASS(progress, nir, nir_opt_dead_cf);
1004 NIR_PASS(progress, nir, nir_opt_cse);
1005 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
1006 NIR_PASS(progress, nir, nir_opt_algebraic);
1007 NIR_PASS(progress, nir, nir_opt_constant_folding);
1008
1009 if (lower_flrp != 0) {
1010 bool lower_flrp_progress = false;
1011 NIR_PASS(lower_flrp_progress,
1012 nir,
1013 nir_lower_flrp,
1014 lower_flrp,
1015 false /* always_precise */,
1016 nir->options->lower_ffma);
1017 if (lower_flrp_progress) {
1018 NIR_PASS(progress, nir,
1019 nir_opt_constant_folding);
1020 progress = true;
1021 }
1022
1023 /* Nothing should rematerialize any flrps, so we only
1024 * need to do this lowering once.
1025 */
1026 lower_flrp = 0;
1027 }
1028
1029 NIR_PASS(progress, nir, nir_opt_undef);
1030 NIR_PASS(progress, nir, nir_opt_loop_unroll,
1031 nir_var_shader_in |
1032 nir_var_shader_out |
1033 nir_var_function_temp);
1034 } while (progress);
1035
1036 NIR_PASS(progress, nir, nir_opt_algebraic_late);
1037 NIR_PASS(progress, nir, nir_lower_bool_to_int32);
1038 NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
1039 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
1040 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
1041
1042 /* Take us out of SSA */
1043 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
1044 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
1045 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
1046 }
1047
1048 void
1049 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
1050 {
1051 bi_context *ctx = rzalloc(NULL, bi_context);
1052 ctx->nir = nir;
1053 ctx->stage = nir->info.stage;
1054 ctx->quirks = bifrost_get_quirks(product_id);
1055 list_inithead(&ctx->blocks);
1056
1057 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
1058 * (so we don't accidentally duplicate the epilogue since mesa/st has
1059 * messed with our I/O quite a bit already) */
1060
1061 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1062
1063 if (ctx->stage == MESA_SHADER_VERTEX) {
1064 NIR_PASS_V(nir, nir_lower_viewport_transform);
1065 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
1066 }
1067
1068 NIR_PASS_V(nir, nir_split_var_copies);
1069 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
1070 NIR_PASS_V(nir, nir_lower_var_copies);
1071 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
1072 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
1073 NIR_PASS_V(nir, nir_lower_ssbo);
1074
1075 bi_optimize_nir(nir);
1076 nir_print_shader(nir, stdout);
1077
1078 panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
1079 program->sysval_count = ctx->sysvals.sysval_count;
1080 memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
1081 ctx->blend_types = program->blend_types;
1082
1083 nir_foreach_function(func, nir) {
1084 if (!func->impl)
1085 continue;
1086
1087 ctx->impl = func->impl;
1088 emit_cf_list(ctx, &func->impl->body);
1089 break; /* TODO: Multi-function shaders */
1090 }
1091
1092 bi_foreach_block(ctx, _block) {
1093 bi_block *block = (bi_block *) _block;
1094 bi_lower_combine(ctx, block);
1095 }
1096
1097 bool progress = false;
1098
1099 do {
1100 progress = false;
1101
1102 bi_foreach_block(ctx, _block) {
1103 bi_block *block = (bi_block *) _block;
1104 progress |= bi_opt_dead_code_eliminate(ctx, block);
1105 }
1106 } while(progress);
1107
1108 bi_print_shader(ctx, stdout);
1109 bi_schedule(ctx);
1110 bi_register_allocate(ctx);
1111 bi_print_shader(ctx, stdout);
1112 bi_pack(ctx, &program->compiled);
1113 disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
1114
1115 ralloc_free(ctx);
1116 }