pan/bi: Add isub op
[mesa.git] / src / panfrost / bifrost / bifrost_compile.c
1 /*
2 * Copyright (C) 2020 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #include "main/mtypes.h"
28 #include "compiler/glsl/glsl_to_nir.h"
29 #include "compiler/nir_types.h"
30 #include "main/imports.h"
31 #include "compiler/nir/nir_builder.h"
32
33 #include "disassemble.h"
34 #include "bifrost_compile.h"
35 #include "compiler.h"
36 #include "bi_quirks.h"
37 #include "bi_print.h"
38
39 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
40 static bi_instruction *bi_emit_branch(bi_context *ctx);
41 static void bi_block_add_successor(bi_block *block, bi_block *successor);
42 static void bi_schedule_barrier(bi_context *ctx);
43
44 static void
45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
46 {
47 bi_instruction *branch = bi_emit_branch(ctx);
48
49 switch (instr->type) {
50 case nir_jump_break:
51 branch->branch.target = ctx->break_block;
52 break;
53 case nir_jump_continue:
54 branch->branch.target = ctx->continue_block;
55 break;
56 default:
57 unreachable("Unhandled jump type");
58 }
59
60 bi_block_add_successor(ctx->current_block, branch->branch.target);
61 }
62
63 /* Gets a bytemask for a complete vecN write */
64 static unsigned
65 bi_mask_for_channels_32(unsigned i)
66 {
67 return (1 << (4 * i)) - 1;
68 }
69
70 static bi_instruction
71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
72 {
73 bi_instruction load = {
74 .type = T,
75 .writemask = bi_mask_for_channels_32(instr->num_components),
76 .src = { BIR_INDEX_CONSTANT },
77 .constant = { .u64 = nir_intrinsic_base(instr) },
78 };
79
80 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
81
82 if (info->has_dest)
83 load.dest = bir_dest_index(&instr->dest);
84
85 if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
86 load.dest_type = nir_intrinsic_type(instr);
87
88 nir_src *offset = nir_get_io_offset_src(instr);
89
90 if (nir_src_is_const(*offset))
91 load.constant.u64 += nir_src_as_uint(*offset);
92 else
93 load.src[0] = bir_src_index(offset);
94
95 return load;
96 }
97
98 static void
99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
100 {
101 bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
102 ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
103 ins.load_vary.reuse = false; /* TODO */
104 ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
105 ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest),
106 bi_emit(ctx, ins);
107 }
108
109 static void
110 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
111 {
112 if (!ctx->emitted_atest) {
113 bi_instruction ins = {
114 .type = BI_ATEST
115 };
116
117 bi_emit(ctx, ins);
118 bi_schedule_barrier(ctx);
119 ctx->emitted_atest = true;
120 }
121
122 bi_instruction blend = {
123 .type = BI_BLEND,
124 .blend_location = nir_intrinsic_base(instr),
125 .src = {
126 bir_src_index(&instr->src[0])
127 },
128 .swizzle = {
129 { 0, 1, 2, 3 }
130 }
131 };
132
133 bi_emit(ctx, blend);
134 bi_schedule_barrier(ctx);
135 }
136
137 static void
138 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
139 {
140 bi_instruction address = bi_load(BI_LOAD_VAR_ADDRESS, instr);
141 address.dest = bi_make_temp(ctx);
142 address.dest_type = nir_type_uint64;
143 address.writemask = (1 << 8) - 1;
144
145 bi_instruction st = {
146 .type = BI_STORE_VAR,
147 .src = {
148 address.dest,
149 bir_src_index(&instr->src[0])
150 },
151 .swizzle = {
152 { 0, 1, 2, 3 }
153 }
154 };
155
156 bi_emit(ctx, address);
157 bi_emit(ctx, st);
158 }
159
160 static void
161 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
162 {
163 bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
164 ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
165 bi_emit(ctx, ld);
166 }
167
168 static void
169 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
170 {
171
172 switch (instr->intrinsic) {
173 case nir_intrinsic_load_barycentric_pixel:
174 /* stub */
175 break;
176 case nir_intrinsic_load_interpolated_input:
177 case nir_intrinsic_load_input:
178 if (ctx->stage == MESA_SHADER_FRAGMENT)
179 bi_emit_ld_vary(ctx, instr);
180 else if (ctx->stage == MESA_SHADER_VERTEX)
181 bi_emit(ctx, bi_load(BI_LOAD_ATTR, instr));
182 else {
183 unreachable("Unsupported shader stage");
184 }
185 break;
186
187 case nir_intrinsic_store_output:
188 if (ctx->stage == MESA_SHADER_FRAGMENT)
189 bi_emit_frag_out(ctx, instr);
190 else if (ctx->stage == MESA_SHADER_VERTEX)
191 bi_emit_st_vary(ctx, instr);
192 else
193 unreachable("Unsupported shader stage");
194 break;
195
196 case nir_intrinsic_load_uniform:
197 bi_emit_ld_uniform(ctx, instr);
198 break;
199
200 default:
201 /* todo */
202 break;
203 }
204 }
205
206 static void
207 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
208 {
209 /* Make sure we've been lowered */
210 assert(instr->def.num_components == 1);
211
212 bi_instruction move = {
213 .type = BI_MOV,
214 .dest = bir_ssa_index(&instr->def),
215 .dest_type = instr->def.bit_size | nir_type_uint,
216 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
217 .src = {
218 BIR_INDEX_CONSTANT
219 },
220 .constant = {
221 .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
222 }
223 };
224
225 bi_emit(ctx, move);
226 }
227
228 static enum bi_class
229 bi_class_for_nir_alu(nir_op op)
230 {
231 switch (op) {
232 case nir_op_iadd:
233 case nir_op_fadd:
234 case nir_op_fsub:
235 return BI_ADD;
236 case nir_op_isub:
237 return BI_ISUB;
238
239 case nir_op_i2i8:
240 case nir_op_i2i16:
241 case nir_op_i2i32:
242 case nir_op_i2i64:
243 case nir_op_u2u8:
244 case nir_op_u2u16:
245 case nir_op_u2u32:
246 case nir_op_u2u64:
247 case nir_op_f2i16:
248 case nir_op_f2i32:
249 case nir_op_f2i64:
250 case nir_op_f2u16:
251 case nir_op_f2u32:
252 case nir_op_f2u64:
253 case nir_op_i2f16:
254 case nir_op_i2f32:
255 case nir_op_i2f64:
256 case nir_op_u2f16:
257 case nir_op_u2f32:
258 case nir_op_u2f64:
259 return BI_CONVERT;
260
261 case nir_op_fmul:
262 return BI_FMA;
263
264 case nir_op_imin:
265 case nir_op_imax:
266 case nir_op_umin:
267 case nir_op_umax:
268 case nir_op_fmin:
269 case nir_op_fmax:
270 return BI_MINMAX;
271
272 case nir_op_fsat:
273 case nir_op_fneg:
274 case nir_op_fabs:
275 case nir_op_mov:
276 return BI_MOV;
277
278 case nir_op_frcp:
279 case nir_op_frsq:
280 case nir_op_fsin:
281 case nir_op_fcos:
282 return BI_SPECIAL;
283
284 default:
285 unreachable("Unknown ALU op");
286 }
287 }
288
289 static void
290 emit_alu(bi_context *ctx, nir_alu_instr *instr)
291 {
292 /* Assume it's something we can handle normally */
293 bi_instruction alu = {
294 .type = bi_class_for_nir_alu(instr->op),
295 .dest = bir_dest_index(&instr->dest.dest),
296 .dest_type = nir_op_infos[instr->op].output_type
297 | nir_dest_bit_size(instr->dest.dest),
298 };
299
300 /* TODO: Implement lowering of special functions for older Bifrost */
301 assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
302
303 if (instr->dest.dest.is_ssa) {
304 /* Construct a writemask */
305 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
306 unsigned comps = instr->dest.dest.ssa.num_components;
307 assert(comps == 1);
308 unsigned bits = bits_per_comp * comps;
309 unsigned bytes = MAX2(bits / 8, 1);
310 alu.writemask = (1 << bytes) - 1;
311 } else {
312 unsigned comp_mask = instr->dest.write_mask;
313
314 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
315 comp_mask);
316 }
317
318 /* We inline constants as we go. This tracks how many constants have
319 * been inlined, since we're limited to 64-bits of constants per
320 * instruction */
321
322 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
323 unsigned constants_left = (64 / dest_bits);
324 unsigned constant_shift = 0;
325
326 /* Copy sources */
327
328 unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
329 assert(num_inputs <= ARRAY_SIZE(alu.src));
330
331 for (unsigned i = 0; i < num_inputs; ++i) {
332 unsigned bits = nir_src_bit_size(instr->src[i].src);
333 alu.src_types[i] = nir_op_infos[instr->op].input_types[i]
334 | bits;
335
336 /* Try to inline a constant */
337 if (nir_src_is_const(instr->src[i].src) && constants_left && (dest_bits == bits)) {
338 alu.constant.u64 |=
339 (nir_src_as_uint(instr->src[i].src)) << constant_shift;
340
341 alu.src[i] = BIR_INDEX_CONSTANT | constant_shift;
342 --constants_left;
343 constant_shift += dest_bits;
344 continue;
345 }
346
347 alu.src[i] = bir_src_index(&instr->src[i].src);
348
349 /* We assert scalarization above */
350 alu.swizzle[i][0] = instr->src[i].swizzle[0];
351 }
352
353 /* Op-specific fixup */
354 switch (instr->op) {
355 case nir_op_fmul:
356 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
357 break;
358 case nir_op_fsat:
359 alu.outmod = BIFROST_SAT; /* MOV */
360 break;
361 case nir_op_fneg:
362 alu.src_neg[0] = true; /* MOV */
363 break;
364 case nir_op_fabs:
365 alu.src_abs[0] = true; /* MOV */
366 break;
367 case nir_op_fsub:
368 alu.src_neg[1] = true; /* ADD */
369 break;
370 case nir_op_fmax:
371 case nir_op_imax:
372 case nir_op_umax:
373 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
374 break;
375 case nir_op_frcp:
376 alu.op.special = BI_SPECIAL_FRCP;
377 break;
378 case nir_op_frsq:
379 alu.op.special = BI_SPECIAL_FRSQ;
380 break;
381 case nir_op_fsin:
382 alu.op.special = BI_SPECIAL_FSIN;
383 break;
384 case nir_op_fcos:
385 alu.op.special = BI_SPECIAL_FCOS;
386 break;
387 default:
388 break;
389 }
390
391 bi_emit(ctx, alu);
392 }
393
394 static void
395 emit_instr(bi_context *ctx, struct nir_instr *instr)
396 {
397 switch (instr->type) {
398 case nir_instr_type_load_const:
399 emit_load_const(ctx, nir_instr_as_load_const(instr));
400 break;
401
402 case nir_instr_type_intrinsic:
403 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
404 break;
405
406 case nir_instr_type_alu:
407 emit_alu(ctx, nir_instr_as_alu(instr));
408 break;
409
410 #if 0
411 case nir_instr_type_tex:
412 emit_tex(ctx, nir_instr_as_tex(instr));
413 break;
414 #endif
415
416 case nir_instr_type_jump:
417 emit_jump(ctx, nir_instr_as_jump(instr));
418 break;
419
420 case nir_instr_type_ssa_undef:
421 /* Spurious */
422 break;
423
424 default:
425 //unreachable("Unhandled instruction type");
426 break;
427 }
428 }
429
430
431
432 static bi_block *
433 create_empty_block(bi_context *ctx)
434 {
435 bi_block *blk = rzalloc(ctx, bi_block);
436
437 blk->predecessors = _mesa_set_create(blk,
438 _mesa_hash_pointer,
439 _mesa_key_pointer_equal);
440
441 blk->name = ctx->block_name_count++;
442
443 return blk;
444 }
445
446 static void
447 bi_block_add_successor(bi_block *block, bi_block *successor)
448 {
449 assert(block);
450 assert(successor);
451
452 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); ++i) {
453 if (block->successors[i]) {
454 if (block->successors[i] == successor)
455 return;
456 else
457 continue;
458 }
459
460 block->successors[i] = successor;
461 _mesa_set_add(successor->predecessors, block);
462 return;
463 }
464
465 unreachable("Too many successors");
466 }
467
468 static void
469 bi_schedule_barrier(bi_context *ctx)
470 {
471 bi_block *temp = ctx->after_block;
472 ctx->after_block = create_empty_block(ctx);
473 list_addtail(&ctx->after_block->link, &ctx->blocks);
474 list_inithead(&ctx->after_block->instructions);
475 bi_block_add_successor(ctx->current_block, ctx->after_block);
476 ctx->current_block = ctx->after_block;
477 ctx->after_block = temp;
478 }
479
480 static bi_block *
481 emit_block(bi_context *ctx, nir_block *block)
482 {
483 if (ctx->after_block) {
484 ctx->current_block = ctx->after_block;
485 ctx->after_block = NULL;
486 } else {
487 ctx->current_block = create_empty_block(ctx);
488 }
489
490 list_addtail(&ctx->current_block->link, &ctx->blocks);
491 list_inithead(&ctx->current_block->instructions);
492
493 nir_foreach_instr(instr, block) {
494 emit_instr(ctx, instr);
495 ++ctx->instruction_count;
496 }
497
498 return ctx->current_block;
499 }
500
501 /* Emits an unconditional branch to the end of the current block, returning a
502 * pointer so the user can fill in details */
503
504 static bi_instruction *
505 bi_emit_branch(bi_context *ctx)
506 {
507 bi_instruction branch = {
508 .type = BI_BRANCH,
509 .branch = {
510 .cond = BI_COND_ALWAYS
511 }
512 };
513
514 return bi_emit(ctx, branch);
515 }
516
517 /* Sets a condition for a branch by examing the NIR condition. If we're
518 * familiar with the condition, we unwrap it to fold it into the branch
519 * instruction. Otherwise, we consume the condition directly. We
520 * generally use 1-bit booleans which allows us to use small types for
521 * the conditions.
522 */
523
524 static void
525 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
526 {
527 /* TODO: Try to unwrap instead of always bailing */
528 branch->src[0] = bir_src_index(cond);
529 branch->src[1] = BIR_INDEX_ZERO;
530 branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
531 branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
532 }
533
534 static void
535 emit_if(bi_context *ctx, nir_if *nif)
536 {
537 bi_block *before_block = ctx->current_block;
538
539 /* Speculatively emit the branch, but we can't fill it in until later */
540 bi_instruction *then_branch = bi_emit_branch(ctx);
541 bi_set_branch_cond(then_branch, &nif->condition, true);
542
543 /* Emit the two subblocks. */
544 bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
545 bi_block *end_then_block = ctx->current_block;
546
547 /* Emit a jump from the end of the then block to the end of the else */
548 bi_instruction *then_exit = bi_emit_branch(ctx);
549
550 /* Emit second block, and check if it's empty */
551
552 int count_in = ctx->instruction_count;
553 bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
554 bi_block *end_else_block = ctx->current_block;
555 ctx->after_block = create_empty_block(ctx);
556
557 /* Now that we have the subblocks emitted, fix up the branches */
558
559 assert(then_block);
560 assert(else_block);
561
562 if (ctx->instruction_count == count_in) {
563 /* The else block is empty, so don't emit an exit jump */
564 bi_remove_instruction(then_exit);
565 then_branch->branch.target = ctx->after_block;
566 } else {
567 then_branch->branch.target = else_block;
568 then_exit->branch.target = ctx->after_block;
569 bi_block_add_successor(end_then_block, then_exit->branch.target);
570 }
571
572 /* Wire up the successors */
573
574 bi_block_add_successor(before_block, then_branch->branch.target); /* then_branch */
575
576 bi_block_add_successor(before_block, then_block); /* fallthrough */
577 bi_block_add_successor(end_else_block, ctx->after_block); /* fallthrough */
578 }
579
580 static void
581 emit_loop(bi_context *ctx, nir_loop *nloop)
582 {
583 /* Remember where we are */
584 bi_block *start_block = ctx->current_block;
585
586 bi_block *saved_break = ctx->break_block;
587 bi_block *saved_continue = ctx->continue_block;
588
589 ctx->continue_block = create_empty_block(ctx);
590 ctx->break_block = create_empty_block(ctx);
591 ctx->after_block = ctx->continue_block;
592
593 /* Emit the body itself */
594 emit_cf_list(ctx, &nloop->body);
595
596 /* Branch back to loop back */
597 bi_instruction *br_back = bi_emit_branch(ctx);
598 br_back->branch.target = ctx->continue_block;
599 bi_block_add_successor(start_block, ctx->continue_block);
600 bi_block_add_successor(ctx->current_block, ctx->continue_block);
601
602 ctx->after_block = ctx->break_block;
603
604 /* Pop off */
605 ctx->break_block = saved_break;
606 ctx->continue_block = saved_continue;
607 ++ctx->loop_count;
608 }
609
610 static bi_block *
611 emit_cf_list(bi_context *ctx, struct exec_list *list)
612 {
613 bi_block *start_block = NULL;
614
615 foreach_list_typed(nir_cf_node, node, node, list) {
616 switch (node->type) {
617 case nir_cf_node_block: {
618 bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
619
620 if (!start_block)
621 start_block = block;
622
623 break;
624 }
625
626 case nir_cf_node_if:
627 emit_if(ctx, nir_cf_node_as_if(node));
628 break;
629
630 case nir_cf_node_loop:
631 emit_loop(ctx, nir_cf_node_as_loop(node));
632 break;
633
634 default:
635 unreachable("Unknown control flow");
636 }
637 }
638
639 return start_block;
640 }
641
642 static int
643 glsl_type_size(const struct glsl_type *type, bool bindless)
644 {
645 return glsl_count_attribute_slots(type, false);
646 }
647
648 static void
649 bi_optimize_nir(nir_shader *nir)
650 {
651 bool progress;
652 unsigned lower_flrp = 16 | 32 | 64;
653
654 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
655 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
656
657 nir_lower_tex_options lower_tex_options = {
658 .lower_txs_lod = true,
659 .lower_txp = ~0,
660 .lower_tex_without_implicit_lod = true,
661 .lower_txd = true,
662 };
663
664 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
665 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
666 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
667
668 do {
669 progress = false;
670
671 NIR_PASS(progress, nir, nir_lower_var_copies);
672 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
673
674 NIR_PASS(progress, nir, nir_copy_prop);
675 NIR_PASS(progress, nir, nir_opt_remove_phis);
676 NIR_PASS(progress, nir, nir_opt_dce);
677 NIR_PASS(progress, nir, nir_opt_dead_cf);
678 NIR_PASS(progress, nir, nir_opt_cse);
679 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
680 NIR_PASS(progress, nir, nir_opt_algebraic);
681 NIR_PASS(progress, nir, nir_opt_constant_folding);
682
683 if (lower_flrp != 0) {
684 bool lower_flrp_progress = false;
685 NIR_PASS(lower_flrp_progress,
686 nir,
687 nir_lower_flrp,
688 lower_flrp,
689 false /* always_precise */,
690 nir->options->lower_ffma);
691 if (lower_flrp_progress) {
692 NIR_PASS(progress, nir,
693 nir_opt_constant_folding);
694 progress = true;
695 }
696
697 /* Nothing should rematerialize any flrps, so we only
698 * need to do this lowering once.
699 */
700 lower_flrp = 0;
701 }
702
703 NIR_PASS(progress, nir, nir_opt_undef);
704 NIR_PASS(progress, nir, nir_opt_loop_unroll,
705 nir_var_shader_in |
706 nir_var_shader_out |
707 nir_var_function_temp);
708 } while (progress);
709
710 NIR_PASS(progress, nir, nir_opt_algebraic_late);
711 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
712 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
713
714 /* Take us out of SSA */
715 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
716 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
717
718 /* We're a primary scalar architecture but there's enough vector that
719 * we use a vector IR so let's not also deal with scalar hacks on top
720 * of the vector hacks */
721
722 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
723 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
724 NIR_PASS(progress, nir, nir_opt_dce);
725 }
726
727 void
728 bifrost_compile_shader_nir(nir_shader *nir, bifrost_program *program, unsigned product_id)
729 {
730 bi_context *ctx = rzalloc(NULL, bi_context);
731 ctx->nir = nir;
732 ctx->stage = nir->info.stage;
733 ctx->quirks = bifrost_get_quirks(product_id);
734 list_inithead(&ctx->blocks);
735
736 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
737 * (so we don't accidentally duplicate the epilogue since mesa/st has
738 * messed with our I/O quite a bit already) */
739
740 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
741
742 if (ctx->stage == MESA_SHADER_VERTEX) {
743 NIR_PASS_V(nir, nir_lower_viewport_transform);
744 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
745 }
746
747 NIR_PASS_V(nir, nir_split_var_copies);
748 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
749 NIR_PASS_V(nir, nir_lower_var_copies);
750 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
751 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
752 NIR_PASS_V(nir, nir_lower_ssbo);
753
754 bi_optimize_nir(nir);
755 nir_print_shader(nir, stdout);
756
757 nir_foreach_function(func, nir) {
758 if (!func->impl)
759 continue;
760
761 ctx->impl = func->impl;
762 emit_cf_list(ctx, &func->impl->body);
763 break; /* TODO: Multi-function shaders */
764 }
765
766 bi_print_shader(ctx, stdout);
767 bi_schedule(ctx);
768
769 ralloc_free(ctx);
770 }