bbc3398602c9ced476ae5aa3427515169ef134ca
[mesa.git] / src / panfrost / bifrost / bifrost_compile.c
1 /*
2 * Copyright (C) 2020 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #include "main/mtypes.h"
28 #include "compiler/glsl/glsl_to_nir.h"
29 #include "compiler/nir_types.h"
30 #include "main/imports.h"
31 #include "compiler/nir/nir_builder.h"
32
33 #include "disassemble.h"
34 #include "bifrost_compile.h"
35 #include "compiler.h"
36 #include "bi_quirks.h"
37 #include "bi_print.h"
38
39 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
40 static bi_instruction *bi_emit_branch(bi_context *ctx);
41 static void bi_block_add_successor(bi_block *block, bi_block *successor);
42 static void bi_schedule_barrier(bi_context *ctx);
43
44 static void
45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
46 {
47 bi_instruction *branch = bi_emit_branch(ctx);
48
49 switch (instr->type) {
50 case nir_jump_break:
51 branch->branch.target = ctx->break_block;
52 break;
53 case nir_jump_continue:
54 branch->branch.target = ctx->continue_block;
55 break;
56 default:
57 unreachable("Unhandled jump type");
58 }
59
60 bi_block_add_successor(ctx->current_block, branch->branch.target);
61 }
62
63 /* Gets a bytemask for a complete vecN write */
64 static unsigned
65 bi_mask_for_channels_32(unsigned i)
66 {
67 return (1 << (4 * i)) - 1;
68 }
69
70 static bi_instruction
71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
72 {
73 bi_instruction load = {
74 .type = T,
75 .writemask = bi_mask_for_channels_32(instr->num_components),
76 .src = { BIR_INDEX_CONSTANT },
77 .constant = { .u64 = nir_intrinsic_base(instr) },
78 };
79
80 const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
81
82 if (info->has_dest)
83 load.dest = bir_dest_index(&instr->dest);
84
85 if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
86 load.dest_type = nir_intrinsic_type(instr);
87
88 nir_src *offset = nir_get_io_offset_src(instr);
89
90 if (nir_src_is_const(*offset))
91 load.constant.u64 += nir_src_as_uint(*offset);
92 else
93 load.src[0] = bir_src_index(offset);
94
95 return load;
96 }
97
98 static void
99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
100 {
101 bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
102 ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
103 ins.load_vary.reuse = false; /* TODO */
104 ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
105 ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest),
106 bi_emit(ctx, ins);
107 }
108
109 static void
110 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
111 {
112 if (!ctx->emitted_atest) {
113 bi_instruction ins = {
114 .type = BI_ATEST
115 };
116
117 bi_emit(ctx, ins);
118 bi_schedule_barrier(ctx);
119 ctx->emitted_atest = true;
120 }
121
122 bi_instruction blend = {
123 .type = BI_BLEND,
124 .blend_location = nir_intrinsic_base(instr),
125 .src = {
126 bir_src_index(&instr->src[0])
127 },
128 .swizzle = {
129 { 0, 1, 2, 3 }
130 }
131 };
132
133 bi_emit(ctx, blend);
134 bi_schedule_barrier(ctx);
135 }
136
137 static void
138 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
139 {
140 bi_instruction address = bi_load(BI_LOAD_VAR_ADDRESS, instr);
141 address.dest = bi_make_temp(ctx);
142 address.dest_type = nir_type_uint64;
143 address.writemask = (1 << 8) - 1;
144
145 bi_instruction st = {
146 .type = BI_STORE_VAR,
147 .src = {
148 address.dest,
149 bir_src_index(&instr->src[0])
150 },
151 .swizzle = {
152 { 0, 1, 2, 3 }
153 }
154 };
155
156 bi_emit(ctx, address);
157 bi_emit(ctx, st);
158 }
159
160 static void
161 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
162 {
163 bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
164 ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
165 bi_emit(ctx, ld);
166 }
167
168 static void
169 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
170 {
171
172 switch (instr->intrinsic) {
173 case nir_intrinsic_load_barycentric_pixel:
174 /* stub */
175 break;
176 case nir_intrinsic_load_interpolated_input:
177 case nir_intrinsic_load_input:
178 if (ctx->stage == MESA_SHADER_FRAGMENT)
179 bi_emit_ld_vary(ctx, instr);
180 else if (ctx->stage == MESA_SHADER_VERTEX)
181 bi_emit(ctx, bi_load(BI_LOAD_ATTR, instr));
182 else {
183 unreachable("Unsupported shader stage");
184 }
185 break;
186
187 case nir_intrinsic_store_output:
188 if (ctx->stage == MESA_SHADER_FRAGMENT)
189 bi_emit_frag_out(ctx, instr);
190 else if (ctx->stage == MESA_SHADER_VERTEX)
191 bi_emit_st_vary(ctx, instr);
192 else
193 unreachable("Unsupported shader stage");
194 break;
195
196 case nir_intrinsic_load_uniform:
197 bi_emit_ld_uniform(ctx, instr);
198 break;
199
200 default:
201 /* todo */
202 break;
203 }
204 }
205
206 static void
207 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
208 {
209 /* Make sure we've been lowered */
210 assert(instr->def.num_components == 1);
211
212 bi_instruction move = {
213 .type = BI_MOV,
214 .dest = bir_ssa_index(&instr->def),
215 .dest_type = instr->def.bit_size | nir_type_uint,
216 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
217 .src = {
218 BIR_INDEX_CONSTANT
219 },
220 .constant = {
221 .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
222 }
223 };
224
225 bi_emit(ctx, move);
226 }
227
228 static enum bi_class
229 bi_class_for_nir_alu(nir_op op)
230 {
231 switch (op) {
232 case nir_op_fadd: return BI_ADD;
233 case nir_op_fmul: return BI_FMA;
234 case nir_op_fsat:
235 case nir_op_mov: return BI_MOV;
236 default: unreachable("Unknown ALU op");
237 }
238 }
239
240 static void
241 emit_alu(bi_context *ctx, nir_alu_instr *instr)
242 {
243 /* Assume it's something we can handle normally */
244 bi_instruction alu = {
245 .type = bi_class_for_nir_alu(instr->op),
246 .dest = bir_dest_index(&instr->dest.dest),
247 .dest_type = nir_op_infos[instr->op].output_type
248 | nir_dest_bit_size(instr->dest.dest),
249 };
250
251 if (instr->dest.dest.is_ssa) {
252 /* Construct a writemask */
253 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
254 unsigned comps = instr->dest.dest.ssa.num_components;
255 assert(comps == 1);
256 unsigned bits = bits_per_comp * comps;
257 unsigned bytes = MAX2(bits / 8, 1);
258 alu.writemask = (1 << bytes) - 1;
259 } else {
260 unsigned comp_mask = instr->dest.write_mask;
261
262 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
263 comp_mask);
264 }
265
266 /* We inline constants as we go. This tracks how many constants have
267 * been inlined, since we're limited to 64-bits of constants per
268 * instruction */
269
270 unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
271 unsigned constants_left = (64 / dest_bits);
272 unsigned constant_shift = 0;
273
274 /* Copy sources */
275
276 unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
277 assert(num_inputs <= ARRAY_SIZE(alu.src));
278
279 for (unsigned i = 0; i < num_inputs; ++i) {
280 unsigned bits = nir_src_bit_size(instr->src[i].src);
281 alu.src_types[i] = nir_op_infos[instr->op].input_types[i]
282 | bits;
283
284 /* Try to inline a constant */
285 if (nir_src_is_const(instr->src[i].src) && constants_left && (dest_bits == bits)) {
286 alu.constant.u64 |=
287 (nir_src_as_uint(instr->src[i].src)) << constant_shift;
288
289 alu.src[i] = BIR_INDEX_CONSTANT | constant_shift;
290 --constants_left;
291 constant_shift += dest_bits;
292 continue;
293 }
294
295 alu.src[i] = bir_src_index(&instr->src[i].src);
296
297 /* We assert scalarization above */
298 alu.swizzle[i][0] = instr->src[i].swizzle[0];
299 }
300
301 /* Op-specific fixup */
302 switch (instr->op) {
303 case nir_op_fmul:
304 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
305 break;
306 case nir_op_fsat:
307 alu.outmod = BIFROST_SAT; /* MOV */
308 break;
309 default:
310 break;
311 }
312
313 bi_emit(ctx, alu);
314 }
315
316 static void
317 emit_instr(bi_context *ctx, struct nir_instr *instr)
318 {
319 switch (instr->type) {
320 case nir_instr_type_load_const:
321 emit_load_const(ctx, nir_instr_as_load_const(instr));
322 break;
323
324 case nir_instr_type_intrinsic:
325 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
326 break;
327
328 case nir_instr_type_alu:
329 emit_alu(ctx, nir_instr_as_alu(instr));
330 break;
331
332 #if 0
333 case nir_instr_type_tex:
334 emit_tex(ctx, nir_instr_as_tex(instr));
335 break;
336 #endif
337
338 case nir_instr_type_jump:
339 emit_jump(ctx, nir_instr_as_jump(instr));
340 break;
341
342 case nir_instr_type_ssa_undef:
343 /* Spurious */
344 break;
345
346 default:
347 //unreachable("Unhandled instruction type");
348 break;
349 }
350 }
351
352
353
354 static bi_block *
355 create_empty_block(bi_context *ctx)
356 {
357 bi_block *blk = rzalloc(ctx, bi_block);
358
359 blk->predecessors = _mesa_set_create(blk,
360 _mesa_hash_pointer,
361 _mesa_key_pointer_equal);
362
363 blk->name = ctx->block_name_count++;
364
365 return blk;
366 }
367
368 static void
369 bi_block_add_successor(bi_block *block, bi_block *successor)
370 {
371 assert(block);
372 assert(successor);
373
374 for (unsigned i = 0; i < ARRAY_SIZE(block->successors); ++i) {
375 if (block->successors[i]) {
376 if (block->successors[i] == successor)
377 return;
378 else
379 continue;
380 }
381
382 block->successors[i] = successor;
383 _mesa_set_add(successor->predecessors, block);
384 return;
385 }
386
387 unreachable("Too many successors");
388 }
389
390 static void
391 bi_schedule_barrier(bi_context *ctx)
392 {
393 bi_block *temp = ctx->after_block;
394 ctx->after_block = create_empty_block(ctx);
395 list_addtail(&ctx->after_block->link, &ctx->blocks);
396 list_inithead(&ctx->after_block->instructions);
397 bi_block_add_successor(ctx->current_block, ctx->after_block);
398 ctx->current_block = ctx->after_block;
399 ctx->after_block = temp;
400 }
401
402 static bi_block *
403 emit_block(bi_context *ctx, nir_block *block)
404 {
405 if (ctx->after_block) {
406 ctx->current_block = ctx->after_block;
407 ctx->after_block = NULL;
408 } else {
409 ctx->current_block = create_empty_block(ctx);
410 }
411
412 list_addtail(&ctx->current_block->link, &ctx->blocks);
413 list_inithead(&ctx->current_block->instructions);
414
415 nir_foreach_instr(instr, block) {
416 emit_instr(ctx, instr);
417 ++ctx->instruction_count;
418 }
419
420 return ctx->current_block;
421 }
422
423 /* Emits an unconditional branch to the end of the current block, returning a
424 * pointer so the user can fill in details */
425
426 static bi_instruction *
427 bi_emit_branch(bi_context *ctx)
428 {
429 bi_instruction branch = {
430 .type = BI_BRANCH,
431 .branch = {
432 .cond = BI_COND_ALWAYS
433 }
434 };
435
436 return bi_emit(ctx, branch);
437 }
438
439 /* Sets a condition for a branch by examing the NIR condition. If we're
440 * familiar with the condition, we unwrap it to fold it into the branch
441 * instruction. Otherwise, we consume the condition directly. We
442 * generally use 1-bit booleans which allows us to use small types for
443 * the conditions.
444 */
445
446 static void
447 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
448 {
449 /* TODO: Try to unwrap instead of always bailing */
450 branch->src[0] = bir_src_index(cond);
451 branch->src[1] = BIR_INDEX_ZERO;
452 branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
453 branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
454 }
455
456 static void
457 emit_if(bi_context *ctx, nir_if *nif)
458 {
459 bi_block *before_block = ctx->current_block;
460
461 /* Speculatively emit the branch, but we can't fill it in until later */
462 bi_instruction *then_branch = bi_emit_branch(ctx);
463 bi_set_branch_cond(then_branch, &nif->condition, true);
464
465 /* Emit the two subblocks. */
466 bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
467 bi_block *end_then_block = ctx->current_block;
468
469 /* Emit a jump from the end of the then block to the end of the else */
470 bi_instruction *then_exit = bi_emit_branch(ctx);
471
472 /* Emit second block, and check if it's empty */
473
474 int count_in = ctx->instruction_count;
475 bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
476 bi_block *end_else_block = ctx->current_block;
477 ctx->after_block = create_empty_block(ctx);
478
479 /* Now that we have the subblocks emitted, fix up the branches */
480
481 assert(then_block);
482 assert(else_block);
483
484 if (ctx->instruction_count == count_in) {
485 /* The else block is empty, so don't emit an exit jump */
486 bi_remove_instruction(then_exit);
487 then_branch->branch.target = ctx->after_block;
488 } else {
489 then_branch->branch.target = else_block;
490 then_exit->branch.target = ctx->after_block;
491 bi_block_add_successor(end_then_block, then_exit->branch.target);
492 }
493
494 /* Wire up the successors */
495
496 bi_block_add_successor(before_block, then_branch->branch.target); /* then_branch */
497
498 bi_block_add_successor(before_block, then_block); /* fallthrough */
499 bi_block_add_successor(end_else_block, ctx->after_block); /* fallthrough */
500 }
501
502 static void
503 emit_loop(bi_context *ctx, nir_loop *nloop)
504 {
505 /* Remember where we are */
506 bi_block *start_block = ctx->current_block;
507
508 bi_block *saved_break = ctx->break_block;
509 bi_block *saved_continue = ctx->continue_block;
510
511 ctx->continue_block = create_empty_block(ctx);
512 ctx->break_block = create_empty_block(ctx);
513 ctx->after_block = ctx->continue_block;
514
515 /* Emit the body itself */
516 emit_cf_list(ctx, &nloop->body);
517
518 /* Branch back to loop back */
519 bi_instruction *br_back = bi_emit_branch(ctx);
520 br_back->branch.target = ctx->continue_block;
521 bi_block_add_successor(start_block, ctx->continue_block);
522 bi_block_add_successor(ctx->current_block, ctx->continue_block);
523
524 ctx->after_block = ctx->break_block;
525
526 /* Pop off */
527 ctx->break_block = saved_break;
528 ctx->continue_block = saved_continue;
529 ++ctx->loop_count;
530 }
531
532 static bi_block *
533 emit_cf_list(bi_context *ctx, struct exec_list *list)
534 {
535 bi_block *start_block = NULL;
536
537 foreach_list_typed(nir_cf_node, node, node, list) {
538 switch (node->type) {
539 case nir_cf_node_block: {
540 bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
541
542 if (!start_block)
543 start_block = block;
544
545 break;
546 }
547
548 case nir_cf_node_if:
549 emit_if(ctx, nir_cf_node_as_if(node));
550 break;
551
552 case nir_cf_node_loop:
553 emit_loop(ctx, nir_cf_node_as_loop(node));
554 break;
555
556 default:
557 unreachable("Unknown control flow");
558 }
559 }
560
561 return start_block;
562 }
563
564 static int
565 glsl_type_size(const struct glsl_type *type, bool bindless)
566 {
567 return glsl_count_attribute_slots(type, false);
568 }
569
570 static void
571 bi_optimize_nir(nir_shader *nir)
572 {
573 bool progress;
574 unsigned lower_flrp = 16 | 32 | 64;
575
576 NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
577 NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
578
579 nir_lower_tex_options lower_tex_options = {
580 .lower_txs_lod = true,
581 .lower_txp = ~0,
582 .lower_tex_without_implicit_lod = true,
583 .lower_txd = true,
584 };
585
586 NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
587 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
588 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
589
590 do {
591 progress = false;
592
593 NIR_PASS(progress, nir, nir_lower_var_copies);
594 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
595
596 NIR_PASS(progress, nir, nir_copy_prop);
597 NIR_PASS(progress, nir, nir_opt_remove_phis);
598 NIR_PASS(progress, nir, nir_opt_dce);
599 NIR_PASS(progress, nir, nir_opt_dead_cf);
600 NIR_PASS(progress, nir, nir_opt_cse);
601 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
602 NIR_PASS(progress, nir, nir_opt_algebraic);
603 NIR_PASS(progress, nir, nir_opt_constant_folding);
604
605 if (lower_flrp != 0) {
606 bool lower_flrp_progress = false;
607 NIR_PASS(lower_flrp_progress,
608 nir,
609 nir_lower_flrp,
610 lower_flrp,
611 false /* always_precise */,
612 nir->options->lower_ffma);
613 if (lower_flrp_progress) {
614 NIR_PASS(progress, nir,
615 nir_opt_constant_folding);
616 progress = true;
617 }
618
619 /* Nothing should rematerialize any flrps, so we only
620 * need to do this lowering once.
621 */
622 lower_flrp = 0;
623 }
624
625 NIR_PASS(progress, nir, nir_opt_undef);
626 NIR_PASS(progress, nir, nir_opt_loop_unroll,
627 nir_var_shader_in |
628 nir_var_shader_out |
629 nir_var_function_temp);
630 } while (progress);
631
632 NIR_PASS(progress, nir, nir_opt_algebraic_late);
633 NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
634 NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
635
636 /* Take us out of SSA */
637 NIR_PASS(progress, nir, nir_lower_locals_to_regs);
638 NIR_PASS(progress, nir, nir_convert_from_ssa, true);
639
640 /* We're a primary scalar architecture but there's enough vector that
641 * we use a vector IR so let's not also deal with scalar hacks on top
642 * of the vector hacks */
643
644 NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
645 NIR_PASS(progress, nir, nir_lower_vec_to_movs);
646 NIR_PASS(progress, nir, nir_opt_dce);
647 }
648
649 void
650 bifrost_compile_shader_nir(nir_shader *nir, bifrost_program *program, unsigned product_id)
651 {
652 bi_context *ctx = rzalloc(NULL, bi_context);
653 ctx->nir = nir;
654 ctx->stage = nir->info.stage;
655 ctx->quirks = bifrost_get_quirks(product_id);
656 list_inithead(&ctx->blocks);
657
658 /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
659 * (so we don't accidentally duplicate the epilogue since mesa/st has
660 * messed with our I/O quite a bit already) */
661
662 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
663
664 if (ctx->stage == MESA_SHADER_VERTEX) {
665 NIR_PASS_V(nir, nir_lower_viewport_transform);
666 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
667 }
668
669 NIR_PASS_V(nir, nir_split_var_copies);
670 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
671 NIR_PASS_V(nir, nir_lower_var_copies);
672 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
673 NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
674 NIR_PASS_V(nir, nir_lower_ssbo);
675
676 bi_optimize_nir(nir);
677 nir_print_shader(nir, stdout);
678
679 nir_foreach_function(func, nir) {
680 if (!func->impl)
681 continue;
682
683 ctx->impl = func->impl;
684 emit_cf_list(ctx, &func->impl->body);
685 break; /* TODO: Multi-function shaders */
686 }
687
688 bi_print_shader(ctx, stdout);
689 bi_schedule(ctx);
690
691 ralloc_free(ctx);
692 }