src/panfrost/bifrost/bifrost_compile.c

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #include "main/mtypes.h"
  28 #include "compiler/glsl/glsl_to_nir.h"
  29 #include "compiler/nir_types.h"
  30 #include "util/imports.h"
  31 #include "compiler/nir/nir_builder.h"
  32
  33 #include "disassemble.h"
  34 #include "bifrost_compile.h"
  35 #include "bifrost_nir.h"
  36 #include "compiler.h"
  37 #include "bi_quirks.h"
  38 #include "bi_print.h"
  39
  40 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
  41 static bi_instruction *bi_emit_branch(bi_context *ctx);
  42 static void bi_schedule_barrier(bi_context *ctx);
  43
  44 static void
  45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
  46 {
  47         bi_instruction *branch = bi_emit_branch(ctx);
  48
  49         switch (instr->type) {
  50         case nir_jump_break:
  51                 branch->branch.target = ctx->break_block;
  52                 break;
  53         case nir_jump_continue:
  54                 branch->branch.target = ctx->continue_block;
  55                 break;
  56         default:
  57                 unreachable("Unhandled jump type");
  58         }
  59
  60         pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
  61 }
  62
  63 /* Gets a bytemask for a complete vecN write */
  64 static unsigned
  65 bi_mask_for_channels_32(unsigned i)
  66 {
  67         return (1 << (4 * i)) - 1;
  68 }
  69
  70 static bi_instruction
  71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
  72 {
  73         bi_instruction load = {
  74                 .type = T,
  75                 .writemask = bi_mask_for_channels_32(instr->num_components),
  76                 .src = { BIR_INDEX_CONSTANT },
  77                 .constant = { .u64 = nir_intrinsic_base(instr) },
  78         };
  79
  80         const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
  81
  82         if (info->has_dest)
  83                 load.dest = bir_dest_index(&instr->dest);
  84
  85         if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
  86                 load.dest_type = nir_intrinsic_type(instr);
  87
  88         nir_src *offset = nir_get_io_offset_src(instr);
  89
  90         if (nir_src_is_const(*offset))
  91                 load.constant.u64 += nir_src_as_uint(*offset);
  92         else
  93                 load.src[0] = bir_src_index(offset);
  94
  95         return load;
  96 }
  97
  98 static void
  99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 100 {
 101         bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
 102         ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
 103         ins.load_vary.reuse = false; /* TODO */
 104         ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
 105         ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
 106
 107         if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
 108                 /* Zero it out for direct */
 109                 ins.src[1] = BIR_INDEX_ZERO;
 110         } else {
 111                 /* R61 contains sample mask stuff, TODO RA XXX */
 112                 ins.src[1] = BIR_INDEX_REGISTER | 61;
 113         }
 114
 115         bi_emit(ctx, ins);
 116 }
 117
 118 static void
 119 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
 120 {
 121         if (!ctx->emitted_atest) {
 122                 bi_instruction ins = {
 123                         .type = BI_ATEST,
 124                         .src = {
 125                                 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 126                                 bir_src_index(&instr->src[0])
 127                         },
 128                         .src_types = {
 129                                 nir_type_uint32,
 130                                 nir_type_float32
 131                         },
 132                         .swizzle = {
 133                                 { 0 },
 134                                 { 3, 0 } /* swizzle out the alpha */
 135                         },
 136                         .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 137                         .dest_type = nir_type_uint32,
 138                         .writemask = 0xF
 139                 };
 140
 141                 bi_emit(ctx, ins);
 142                 bi_schedule_barrier(ctx);
 143                 ctx->emitted_atest = true;
 144         }
 145
 146         bi_instruction blend = {
 147                 .type = BI_BLEND,
 148                 .blend_location = nir_intrinsic_base(instr),
 149                 .src = {
 150                         bir_src_index(&instr->src[0]),
 151                         BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
 152                 },
 153                 .src_types = {
 154                         nir_type_float32,
 155                         nir_type_uint32
 156                 },
 157                 .swizzle = {
 158                         { 0, 1, 2, 3 },
 159                         { 0 }
 160                 },
 161                 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
 162                 .dest_type = nir_type_uint32,
 163                 .writemask = 0xF
 164         };
 165
 166         bi_emit(ctx, blend);
 167         bi_schedule_barrier(ctx);
 168 }
 169
 170 static bi_instruction
 171 bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
 172 {
 173         bi_instruction ld = bi_load(T, instr);
 174         ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
 175         ld.src[2] = BIR_INDEX_REGISTER | 62;
 176         ld.src[3] = 0;
 177         ld.src_types[1] = nir_type_uint32;
 178         ld.src_types[2] = nir_type_uint32;
 179         ld.src_types[3] = nir_intrinsic_type(instr);
 180         return ld;
 181 }
 182
 183 static void
 184 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 185 {
 186         bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
 187         address.dest = bi_make_temp(ctx);
 188         address.dest_type = nir_type_uint32;
 189         address.writemask = (1 << 12) - 1;
 190
 191         bi_instruction st = {
 192                 .type = BI_STORE_VAR,
 193                 .src = {
 194                         bir_src_index(&instr->src[0]),
 195                         address.dest, address.dest, address.dest,
 196                 },
 197                 .src_types = {
 198                         nir_type_uint32,
 199                         nir_type_uint32, nir_type_uint32, nir_type_uint32,
 200                 },
 201                 .swizzle = {
 202                         { 0, 1, 2, 3 },
 203                         { 0 }, { 1 }, { 2}
 204                 },
 205                 .store_channels = 4, /* TODO: WRITEMASK */
 206         };
 207
 208         bi_emit(ctx, address);
 209         bi_emit(ctx, st);
 210 }
 211
 212 static void
 213 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
 214 {
 215         bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
 216         ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
 217
 218         /* TODO: Indirect access, since we need to multiply by the element
 219          * size. I believe we can get this lowering automatically via
 220          * nir_lower_io (as mul instructions) with the proper options, but this
 221          * is TODO */
 222         assert(ld.src[0] & BIR_INDEX_CONSTANT);
 223         ld.constant.u64 += ctx->sysvals.sysval_count;
 224         ld.constant.u64 *= 16;
 225
 226         bi_emit(ctx, ld);
 227 }
 228
 229 static void
 230 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
 231                 unsigned nr_components, unsigned offset)
 232 {
 233         nir_dest nir_dest;
 234
 235         /* Figure out which uniform this is */
 236         int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
 237         void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
 238
 239         /* Sysvals are prefix uniforms */
 240         unsigned uniform = ((uintptr_t) val) - 1;
 241
 242         /* Emit the read itself -- this is never indirect */
 243
 244         bi_instruction load = {
 245                 .type = BI_LOAD_UNIFORM,
 246                 .writemask = (1 << (nr_components * 4)) - 1,
 247                 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
 248                 .constant = { (uniform * 16) + offset },
 249                 .dest = bir_dest_index(&nir_dest),
 250                 .dest_type = nir_type_uint32, /* TODO */
 251         };
 252
 253         bi_emit(ctx, load);
 254 }
 255
 256 static void
 257 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
 258 {
 259
 260         switch (instr->intrinsic) {
 261         case nir_intrinsic_load_barycentric_pixel:
 262                 /* stub */
 263                 break;
 264         case nir_intrinsic_load_interpolated_input:
 265         case nir_intrinsic_load_input:
 266                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 267                         bi_emit_ld_vary(ctx, instr);
 268                 else if (ctx->stage == MESA_SHADER_VERTEX)
 269                         bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
 270                 else {
 271                         unreachable("Unsupported shader stage");
 272                 }
 273                 break;
 274
 275         case nir_intrinsic_store_output:
 276                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 277                         bi_emit_frag_out(ctx, instr);
 278                 else if (ctx->stage == MESA_SHADER_VERTEX)
 279                         bi_emit_st_vary(ctx, instr);
 280                 else
 281                         unreachable("Unsupported shader stage");
 282                 break;
 283
 284         case nir_intrinsic_load_uniform:
 285                 bi_emit_ld_uniform(ctx, instr);
 286                 break;
 287
 288         case nir_intrinsic_load_ssbo_address:
 289                 bi_emit_sysval(ctx, &instr->instr, 1, 0);
 290                 break;
 291
 292         case nir_intrinsic_get_buffer_size:
 293                 bi_emit_sysval(ctx, &instr->instr, 1, 8);
 294                 break;
 295
 296         case nir_intrinsic_load_viewport_scale:
 297         case nir_intrinsic_load_viewport_offset:
 298         case nir_intrinsic_load_num_work_groups:
 299         case nir_intrinsic_load_sampler_lod_parameters_pan:
 300                 bi_emit_sysval(ctx, &instr->instr, 3, 0);
 301                 break;
 302
 303         default:
 304                 /* todo */
 305                 break;
 306         }
 307 }
 308
 309 static void
 310 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
 311 {
 312         /* Make sure we've been lowered */
 313         assert(instr->def.num_components == 1);
 314
 315         bi_instruction move = {
 316                 .type = BI_MOV,
 317                 .dest = bir_ssa_index(&instr->def),
 318                 .dest_type = instr->def.bit_size | nir_type_uint,
 319                 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
 320                 .src = {
 321                         BIR_INDEX_CONSTANT
 322                 },
 323                 .src_types = {
 324                         instr->def.bit_size | nir_type_uint,
 325                 },
 326                 .constant = {
 327                         .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
 328                 }
 329         };
 330
 331         bi_emit(ctx, move);
 332 }
 333
 334 #define BI_CASE_CMP(op) \
 335         case op##8: \
 336         case op##16: \
 337         case op##32: \
 338
 339 static enum bi_class
 340 bi_class_for_nir_alu(nir_op op)
 341 {
 342         switch (op) {
 343         case nir_op_iadd:
 344         case nir_op_fadd:
 345         case nir_op_fsub:
 346                 return BI_ADD;
 347         case nir_op_isub:
 348                 return BI_ISUB;
 349
 350         BI_CASE_CMP(nir_op_flt)
 351         BI_CASE_CMP(nir_op_fge)
 352         BI_CASE_CMP(nir_op_feq)
 353         BI_CASE_CMP(nir_op_fne)
 354         BI_CASE_CMP(nir_op_ilt)
 355         BI_CASE_CMP(nir_op_ige)
 356         BI_CASE_CMP(nir_op_ieq)
 357         BI_CASE_CMP(nir_op_ine)
 358                 return BI_CMP;
 359
 360         case nir_op_b8csel:
 361         case nir_op_b16csel:
 362         case nir_op_b32csel:
 363                 return BI_CSEL;
 364
 365         case nir_op_i2i8:
 366         case nir_op_i2i16:
 367         case nir_op_i2i32:
 368         case nir_op_i2i64:
 369         case nir_op_u2u8:
 370         case nir_op_u2u16:
 371         case nir_op_u2u32:
 372         case nir_op_u2u64:
 373         case nir_op_f2i16:
 374         case nir_op_f2i32:
 375         case nir_op_f2i64:
 376         case nir_op_f2u16:
 377         case nir_op_f2u32:
 378         case nir_op_f2u64:
 379         case nir_op_i2f16:
 380         case nir_op_i2f32:
 381         case nir_op_i2f64:
 382         case nir_op_u2f16:
 383         case nir_op_u2f32:
 384         case nir_op_u2f64:
 385         case nir_op_f2f16:
 386         case nir_op_f2f32:
 387         case nir_op_f2f64:
 388         case nir_op_f2fmp:
 389                 return BI_CONVERT;
 390
 391         case nir_op_vec2:
 392         case nir_op_vec3:
 393         case nir_op_vec4:
 394                 return BI_COMBINE;
 395
 396         case nir_op_vec8:
 397         case nir_op_vec16:
 398                 unreachable("should've been lowered");
 399
 400         case nir_op_ffma:
 401         case nir_op_fmul:
 402                 return BI_FMA;
 403
 404         case nir_op_imin:
 405         case nir_op_imax:
 406         case nir_op_umin:
 407         case nir_op_umax:
 408         case nir_op_fmin:
 409         case nir_op_fmax:
 410                 return BI_MINMAX;
 411
 412         case nir_op_fsat:
 413         case nir_op_fneg:
 414         case nir_op_fabs:
 415                 return BI_FMOV;
 416         case nir_op_mov:
 417                 return BI_MOV;
 418
 419         case nir_op_fround_even:
 420         case nir_op_fceil:
 421         case nir_op_ffloor:
 422         case nir_op_ftrunc:
 423                 return BI_ROUND;
 424
 425         case nir_op_frcp:
 426         case nir_op_frsq:
 427                 return BI_SPECIAL;
 428
 429         default:
 430                 unreachable("Unknown ALU op");
 431         }
 432 }
 433
 434 /* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
 435  * return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
 436  * optimizations). Otherwise it will bail (when used for primary code
 437  * generation). */
 438
 439 static enum bi_cond
 440 bi_cond_for_nir(nir_op op, bool soft)
 441 {
 442         switch (op) {
 443         BI_CASE_CMP(nir_op_flt)
 444         BI_CASE_CMP(nir_op_ilt)
 445                 return BI_COND_LT;
 446
 447         BI_CASE_CMP(nir_op_fge)
 448         BI_CASE_CMP(nir_op_ige)
 449                 return BI_COND_GE;
 450
 451         BI_CASE_CMP(nir_op_feq)
 452         BI_CASE_CMP(nir_op_ieq)
 453                 return BI_COND_EQ;
 454
 455         BI_CASE_CMP(nir_op_fne)
 456         BI_CASE_CMP(nir_op_ine)
 457                 return BI_COND_NE;
 458         default:
 459                 if (soft)
 460                         return BI_COND_ALWAYS;
 461                 else
 462                         unreachable("Invalid compare");
 463         }
 464 }
 465
 466 static void
 467 bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
 468                 unsigned *constants_left, unsigned *constant_shift)
 469 {
 470         unsigned bits = nir_src_bit_size(instr->src[i].src);
 471         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 472
 473         alu->src_types[to] = nir_op_infos[instr->op].input_types[i]
 474                 | bits;
 475
 476         /* Try to inline a constant */
 477         if (nir_src_is_const(instr->src[i].src) && *constants_left && (dest_bits == bits)) {
 478                 alu->constant.u64 |=
 479                         (nir_src_as_uint(instr->src[i].src)) << *constant_shift;
 480
 481                 alu->src[to] = BIR_INDEX_CONSTANT | (*constant_shift);
 482                 --(*constants_left);
 483                 (*constant_shift) += dest_bits;
 484                 return;
 485         }
 486
 487         alu->src[to] = bir_src_index(&instr->src[i].src);
 488
 489         /* We assert scalarization above */
 490         alu->swizzle[to][0] = instr->src[i].swizzle[0];
 491 }
 492
 493 static void
 494 bi_fuse_csel_cond(bi_instruction *csel, nir_alu_src cond,
 495                 unsigned *constants_left, unsigned *constant_shift)
 496 {
 497         /* Bail for vector weirdness */
 498         if (cond.swizzle[0] != 0)
 499                 return;
 500
 501         if (!cond.src.is_ssa)
 502                 return;
 503
 504         nir_ssa_def *def = cond.src.ssa;
 505         nir_instr *parent = def->parent_instr;
 506
 507         if (parent->type != nir_instr_type_alu)
 508                 return;
 509
 510         nir_alu_instr *alu = nir_instr_as_alu(parent);
 511
 512         /* Try to match a condition */
 513         enum bi_cond bcond = bi_cond_for_nir(alu->op, true);
 514
 515         if (bcond == BI_COND_ALWAYS)
 516                 return;
 517
 518         /* We found one, let's fuse it in */
 519         csel->csel_cond = bcond;
 520         bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift);
 521         bi_copy_src(csel, alu, 1, 1, constants_left, constant_shift);
 522 }
 523
 524 static void
 525 emit_alu(bi_context *ctx, nir_alu_instr *instr)
 526 {
 527         /* Assume it's something we can handle normally */
 528         bi_instruction alu = {
 529                 .type = bi_class_for_nir_alu(instr->op),
 530                 .dest = bir_dest_index(&instr->dest.dest),
 531                 .dest_type = nir_op_infos[instr->op].output_type
 532                         | nir_dest_bit_size(instr->dest.dest),
 533         };
 534
 535         /* TODO: Implement lowering of special functions for older Bifrost */
 536         assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
 537
 538         if (instr->dest.dest.is_ssa) {
 539                 /* Construct a writemask */
 540                 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
 541                 unsigned comps = instr->dest.dest.ssa.num_components;
 542
 543                 if (alu.type != BI_COMBINE)
 544                         assert(comps == 1);
 545
 546                 unsigned bits = bits_per_comp * comps;
 547                 unsigned bytes = bits / 8;
 548                 alu.writemask = (1 << bytes) - 1;
 549         } else {
 550                 unsigned comp_mask = instr->dest.write_mask;
 551
 552                 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
 553                                 comp_mask);
 554         }
 555
 556         /* We inline constants as we go. This tracks how many constants have
 557          * been inlined, since we're limited to 64-bits of constants per
 558          * instruction */
 559
 560         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 561         unsigned constants_left = (64 / dest_bits);
 562         unsigned constant_shift = 0;
 563
 564         if (alu.type == BI_COMBINE)
 565                 constants_left = 0;
 566
 567         /* Copy sources */
 568
 569         unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
 570         assert(num_inputs <= ARRAY_SIZE(alu.src));
 571
 572         for (unsigned i = 0; i < num_inputs; ++i) {
 573                 unsigned f = 0;
 574
 575                 if (i && alu.type == BI_CSEL)
 576                         f++;
 577
 578                 bi_copy_src(&alu, instr, i, i + f, &constants_left, &constant_shift);
 579         }
 580
 581         /* Op-specific fixup */
 582         switch (instr->op) {
 583         case nir_op_fmul:
 584                 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
 585                 alu.src_types[2] = alu.src_types[1];
 586                 break;
 587         case nir_op_fsat:
 588                 alu.outmod = BIFROST_SAT; /* FMOV */
 589                 break;
 590         case nir_op_fneg:
 591                 alu.src_neg[0] = true; /* FMOV */
 592                 break;
 593         case nir_op_fabs:
 594                 alu.src_abs[0] = true; /* FMOV */
 595                 break;
 596         case nir_op_fsub:
 597                 alu.src_neg[1] = true; /* FADD */
 598                 break;
 599         case nir_op_fmax:
 600         case nir_op_imax:
 601         case nir_op_umax:
 602                 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
 603                 break;
 604         case nir_op_frcp:
 605                 alu.op.special = BI_SPECIAL_FRCP;
 606                 break;
 607         case nir_op_frsq:
 608                 alu.op.special = BI_SPECIAL_FRSQ;
 609                 break;
 610         BI_CASE_CMP(nir_op_flt)
 611         BI_CASE_CMP(nir_op_ilt)
 612         BI_CASE_CMP(nir_op_fge)
 613         BI_CASE_CMP(nir_op_ige)
 614         BI_CASE_CMP(nir_op_feq)
 615         BI_CASE_CMP(nir_op_ieq)
 616         BI_CASE_CMP(nir_op_fne)
 617         BI_CASE_CMP(nir_op_ine)
 618                 alu.op.compare = bi_cond_for_nir(instr->op, false);
 619                 break;
 620         case nir_op_fround_even:
 621                 alu.op.round = BI_ROUND_MODE;
 622                 alu.roundmode = BIFROST_RTE;
 623                 break;
 624         case nir_op_fceil:
 625                 alu.op.round = BI_ROUND_MODE;
 626                 alu.roundmode = BIFROST_RTP;
 627                 break;
 628         case nir_op_ffloor:
 629                 alu.op.round = BI_ROUND_MODE;
 630                 alu.roundmode = BIFROST_RTN;
 631                 break;
 632         case nir_op_ftrunc:
 633                 alu.op.round = BI_ROUND_MODE;
 634                 alu.roundmode = BIFROST_RTZ;
 635                 break;
 636         default:
 637                 break;
 638         }
 639
 640         if (alu.type == BI_CSEL) {
 641                 /* Default to csel3 */
 642                 alu.csel_cond = BI_COND_NE;
 643                 alu.src[1] = BIR_INDEX_ZERO;
 644                 alu.src_types[1] = alu.src_types[0];
 645
 646                 bi_fuse_csel_cond(&alu, instr->src[0],
 647                                 &constants_left, &constant_shift);
 648         }
 649
 650         bi_emit(ctx, alu);
 651 }
 652
 653 static void
 654 emit_instr(bi_context *ctx, struct nir_instr *instr)
 655 {
 656         switch (instr->type) {
 657         case nir_instr_type_load_const:
 658                 emit_load_const(ctx, nir_instr_as_load_const(instr));
 659                 break;
 660
 661         case nir_instr_type_intrinsic:
 662                 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
 663                 break;
 664
 665         case nir_instr_type_alu:
 666                 emit_alu(ctx, nir_instr_as_alu(instr));
 667                 break;
 668
 669 #if 0
 670         case nir_instr_type_tex:
 671                 emit_tex(ctx, nir_instr_as_tex(instr));
 672                 break;
 673 #endif
 674
 675         case nir_instr_type_jump:
 676                 emit_jump(ctx, nir_instr_as_jump(instr));
 677                 break;
 678
 679         case nir_instr_type_ssa_undef:
 680                 /* Spurious */
 681                 break;
 682
 683         default:
 684                 //unreachable("Unhandled instruction type");
 685                 break;
 686         }
 687 }
 688
 689
 690
 691 static bi_block *
 692 create_empty_block(bi_context *ctx)
 693 {
 694         bi_block *blk = rzalloc(ctx, bi_block);
 695
 696         blk->base.predecessors = _mesa_set_create(blk,
 697                         _mesa_hash_pointer,
 698                         _mesa_key_pointer_equal);
 699
 700         blk->base.name = ctx->block_name_count++;
 701
 702         return blk;
 703 }
 704
 705 static void
 706 bi_schedule_barrier(bi_context *ctx)
 707 {
 708         bi_block *temp = ctx->after_block;
 709         ctx->after_block = create_empty_block(ctx);
 710         list_addtail(&ctx->after_block->base.link, &ctx->blocks);
 711         list_inithead(&ctx->after_block->base.instructions);
 712         pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
 713         ctx->current_block = ctx->after_block;
 714         ctx->after_block = temp;
 715 }
 716
 717 static bi_block *
 718 emit_block(bi_context *ctx, nir_block *block)
 719 {
 720         if (ctx->after_block) {
 721                 ctx->current_block = ctx->after_block;
 722                 ctx->after_block = NULL;
 723         } else {
 724                 ctx->current_block = create_empty_block(ctx);
 725         }
 726
 727         list_addtail(&ctx->current_block->base.link, &ctx->blocks);
 728         list_inithead(&ctx->current_block->base.instructions);
 729
 730         nir_foreach_instr(instr, block) {
 731                 emit_instr(ctx, instr);
 732                 ++ctx->instruction_count;
 733         }
 734
 735         return ctx->current_block;
 736 }
 737
 738 /* Emits an unconditional branch to the end of the current block, returning a
 739  * pointer so the user can fill in details */
 740
 741 static bi_instruction *
 742 bi_emit_branch(bi_context *ctx)
 743 {
 744         bi_instruction branch = {
 745                 .type = BI_BRANCH,
 746                 .branch = {
 747                         .cond = BI_COND_ALWAYS
 748                 }
 749         };
 750
 751         return bi_emit(ctx, branch);
 752 }
 753
 754 /* Sets a condition for a branch by examing the NIR condition. If we're
 755  * familiar with the condition, we unwrap it to fold it into the branch
 756  * instruction. Otherwise, we consume the condition directly. We
 757  * generally use 1-bit booleans which allows us to use small types for
 758  * the conditions.
 759  */
 760
 761 static void
 762 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
 763 {
 764         /* TODO: Try to unwrap instead of always bailing */
 765         branch->src[0] = bir_src_index(cond);
 766         branch->src[1] = BIR_INDEX_ZERO;
 767         branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
 768         branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
 769 }
 770
 771 static void
 772 emit_if(bi_context *ctx, nir_if *nif)
 773 {
 774         bi_block *before_block = ctx->current_block;
 775
 776         /* Speculatively emit the branch, but we can't fill it in until later */
 777         bi_instruction *then_branch = bi_emit_branch(ctx);
 778         bi_set_branch_cond(then_branch, &nif->condition, true);
 779
 780         /* Emit the two subblocks. */
 781         bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
 782         bi_block *end_then_block = ctx->current_block;
 783
 784         /* Emit a jump from the end of the then block to the end of the else */
 785         bi_instruction *then_exit = bi_emit_branch(ctx);
 786
 787         /* Emit second block, and check if it's empty */
 788
 789         int count_in = ctx->instruction_count;
 790         bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
 791         bi_block *end_else_block = ctx->current_block;
 792         ctx->after_block = create_empty_block(ctx);
 793
 794         /* Now that we have the subblocks emitted, fix up the branches */
 795
 796         assert(then_block);
 797         assert(else_block);
 798
 799         if (ctx->instruction_count == count_in) {
 800                 /* The else block is empty, so don't emit an exit jump */
 801                 bi_remove_instruction(then_exit);
 802                 then_branch->branch.target = ctx->after_block;
 803         } else {
 804                 then_branch->branch.target = else_block;
 805                 then_exit->branch.target = ctx->after_block;
 806                 pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
 807         }
 808
 809         /* Wire up the successors */
 810
 811         pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
 812
 813         pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
 814         pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
 815 }
 816
 817 static void
 818 emit_loop(bi_context *ctx, nir_loop *nloop)
 819 {
 820         /* Remember where we are */
 821         bi_block *start_block = ctx->current_block;
 822
 823         bi_block *saved_break = ctx->break_block;
 824         bi_block *saved_continue = ctx->continue_block;
 825
 826         ctx->continue_block = create_empty_block(ctx);
 827         ctx->break_block = create_empty_block(ctx);
 828         ctx->after_block = ctx->continue_block;
 829
 830         /* Emit the body itself */
 831         emit_cf_list(ctx, &nloop->body);
 832
 833         /* Branch back to loop back */
 834         bi_instruction *br_back = bi_emit_branch(ctx);
 835         br_back->branch.target = ctx->continue_block;
 836         pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
 837         pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
 838
 839         ctx->after_block = ctx->break_block;
 840
 841         /* Pop off */
 842         ctx->break_block = saved_break;
 843         ctx->continue_block = saved_continue;
 844         ++ctx->loop_count;
 845 }
 846
 847 static bi_block *
 848 emit_cf_list(bi_context *ctx, struct exec_list *list)
 849 {
 850         bi_block *start_block = NULL;
 851
 852         foreach_list_typed(nir_cf_node, node, node, list) {
 853                 switch (node->type) {
 854                 case nir_cf_node_block: {
 855                         bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
 856
 857                         if (!start_block)
 858                                 start_block = block;
 859
 860                         break;
 861                 }
 862
 863                 case nir_cf_node_if:
 864                         emit_if(ctx, nir_cf_node_as_if(node));
 865                         break;
 866
 867                 case nir_cf_node_loop:
 868                         emit_loop(ctx, nir_cf_node_as_loop(node));
 869                         break;
 870
 871                 default:
 872                         unreachable("Unknown control flow");
 873                 }
 874         }
 875
 876         return start_block;
 877 }
 878
 879 static int
 880 glsl_type_size(const struct glsl_type *type, bool bindless)
 881 {
 882         return glsl_count_attribute_slots(type, false);
 883 }
 884
 885 static void
 886 bi_optimize_nir(nir_shader *nir)
 887 {
 888         bool progress;
 889         unsigned lower_flrp = 16 | 32 | 64;
 890
 891         NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
 892         NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
 893
 894         nir_lower_tex_options lower_tex_options = {
 895                 .lower_txs_lod = true,
 896                 .lower_txp = ~0,
 897                 .lower_tex_without_implicit_lod = true,
 898                 .lower_txd = true,
 899         };
 900
 901         NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
 902         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 903         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 904
 905         do {
 906                 progress = false;
 907
 908                 NIR_PASS(progress, nir, nir_lower_var_copies);
 909                 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
 910
 911                 NIR_PASS(progress, nir, nir_copy_prop);
 912                 NIR_PASS(progress, nir, nir_opt_remove_phis);
 913                 NIR_PASS(progress, nir, nir_opt_dce);
 914                 NIR_PASS(progress, nir, nir_opt_dead_cf);
 915                 NIR_PASS(progress, nir, nir_opt_cse);
 916                 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
 917                 NIR_PASS(progress, nir, nir_opt_algebraic);
 918                 NIR_PASS(progress, nir, nir_opt_constant_folding);
 919
 920                 if (lower_flrp != 0) {
 921                         bool lower_flrp_progress = false;
 922                         NIR_PASS(lower_flrp_progress,
 923                                  nir,
 924                                  nir_lower_flrp,
 925                                  lower_flrp,
 926                                  false /* always_precise */,
 927                                  nir->options->lower_ffma);
 928                         if (lower_flrp_progress) {
 929                                 NIR_PASS(progress, nir,
 930                                          nir_opt_constant_folding);
 931                                 progress = true;
 932                         }
 933
 934                         /* Nothing should rematerialize any flrps, so we only
 935                          * need to do this lowering once.
 936                          */
 937                         lower_flrp = 0;
 938                 }
 939
 940                 NIR_PASS(progress, nir, nir_opt_undef);
 941                 NIR_PASS(progress, nir, nir_opt_loop_unroll,
 942                          nir_var_shader_in |
 943                          nir_var_shader_out |
 944                          nir_var_function_temp);
 945         } while (progress);
 946
 947         NIR_PASS(progress, nir, nir_opt_algebraic_late);
 948         NIR_PASS(progress, nir, nir_lower_bool_to_int32);
 949         NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
 950         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 951         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 952
 953         /* Take us out of SSA */
 954         NIR_PASS(progress, nir, nir_lower_locals_to_regs);
 955         NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
 956         NIR_PASS(progress, nir, nir_convert_from_ssa, true);
 957 }
 958
 959 void
 960 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
 961 {
 962         bi_context *ctx = rzalloc(NULL, bi_context);
 963         ctx->nir = nir;
 964         ctx->stage = nir->info.stage;
 965         ctx->quirks = bifrost_get_quirks(product_id);
 966         list_inithead(&ctx->blocks);
 967
 968         /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
 969          * (so we don't accidentally duplicate the epilogue since mesa/st has
 970          * messed with our I/O quite a bit already) */
 971
 972         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 973
 974         if (ctx->stage == MESA_SHADER_VERTEX) {
 975                 NIR_PASS_V(nir, nir_lower_viewport_transform);
 976                 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
 977         }
 978
 979         NIR_PASS_V(nir, nir_split_var_copies);
 980         NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 981         NIR_PASS_V(nir, nir_lower_var_copies);
 982         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 983         NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
 984         NIR_PASS_V(nir, nir_lower_ssbo);
 985
 986         bi_optimize_nir(nir);
 987         nir_print_shader(nir, stdout);
 988
 989         panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
 990         program->sysval_count = ctx->sysvals.sysval_count;
 991         memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
 992
 993         nir_foreach_function(func, nir) {
 994                 if (!func->impl)
 995                         continue;
 996
 997                 ctx->impl = func->impl;
 998                 emit_cf_list(ctx, &func->impl->body);
 999                 break; /* TODO: Multi-function shaders */
1000         }
1001
1002         bi_foreach_block(ctx, _block) {
1003                 bi_block *block = (bi_block *) _block;
1004                 bi_lower_combine(ctx, block);
1005         }
1006
1007         bool progress = false;
1008
1009         do {
1010                 progress = false;
1011
1012                 bi_foreach_block(ctx, _block) {
1013                         bi_block *block = (bi_block *) _block;
1014                         progress |= bi_opt_dead_code_eliminate(ctx, block);
1015                 }
1016         } while(progress);
1017
1018         bi_print_shader(ctx, stdout);
1019         bi_schedule(ctx);
1020         bi_register_allocate(ctx);
1021         bi_print_shader(ctx, stdout);
1022         bi_pack(ctx, &program->compiled);
1023         disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
1024
1025         ralloc_free(ctx);
1026 }