src/panfrost/bifrost/bifrost_compile.c

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #include "main/mtypes.h"
  28 #include "compiler/glsl/glsl_to_nir.h"
  29 #include "compiler/nir_types.h"
  30 #include "main/imports.h"
  31 #include "compiler/nir/nir_builder.h"
  32
  33 #include "disassemble.h"
  34 #include "bifrost_compile.h"
  35 #include "bifrost_nir.h"
  36 #include "compiler.h"
  37 #include "bi_quirks.h"
  38 #include "bi_print.h"
  39
  40 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
  41 static bi_instruction *bi_emit_branch(bi_context *ctx);
  42 static void bi_schedule_barrier(bi_context *ctx);
  43
  44 static void
  45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
  46 {
  47         bi_instruction *branch = bi_emit_branch(ctx);
  48
  49         switch (instr->type) {
  50         case nir_jump_break:
  51                 branch->branch.target = ctx->break_block;
  52                 break;
  53         case nir_jump_continue:
  54                 branch->branch.target = ctx->continue_block;
  55                 break;
  56         default:
  57                 unreachable("Unhandled jump type");
  58         }
  59
  60         pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
  61 }
  62
  63 /* Gets a bytemask for a complete vecN write */
  64 static unsigned
  65 bi_mask_for_channels_32(unsigned i)
  66 {
  67         return (1 << (4 * i)) - 1;
  68 }
  69
  70 static bi_instruction
  71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
  72 {
  73         bi_instruction load = {
  74                 .type = T,
  75                 .writemask = bi_mask_for_channels_32(instr->num_components),
  76                 .src = { BIR_INDEX_CONSTANT },
  77                 .constant = { .u64 = nir_intrinsic_base(instr) },
  78         };
  79
  80         const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
  81
  82         if (info->has_dest)
  83                 load.dest = bir_dest_index(&instr->dest);
  84
  85         if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
  86                 load.dest_type = nir_intrinsic_type(instr);
  87
  88         nir_src *offset = nir_get_io_offset_src(instr);
  89
  90         if (nir_src_is_const(*offset))
  91                 load.constant.u64 += nir_src_as_uint(*offset);
  92         else
  93                 load.src[0] = bir_src_index(offset);
  94
  95         return load;
  96 }
  97
  98 static void
  99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 100 {
 101         bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
 102         ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
 103         ins.load_vary.reuse = false; /* TODO */
 104         ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
 105         ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
 106
 107         if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
 108                 /* Zero it out for direct */
 109                 ins.src[1] = BIR_INDEX_ZERO;
 110         } else {
 111                 /* R61 contains sample mask stuff, TODO RA XXX */
 112                 ins.src[1] = BIR_INDEX_REGISTER | 61;
 113         }
 114
 115         bi_emit(ctx, ins);
 116 }
 117
 118 static void
 119 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
 120 {
 121         if (!ctx->emitted_atest) {
 122                 bi_instruction ins = {
 123                         .type = BI_ATEST,
 124                         .src = {
 125                                 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 126                                 bir_src_index(&instr->src[0])
 127                         },
 128                         .src_types = {
 129                                 nir_type_uint32,
 130                                 nir_type_float32
 131                         },
 132                         .swizzle = {
 133                                 { 0 },
 134                                 { 3, 0 } /* swizzle out the alpha */
 135                         },
 136                         .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 137                         .dest_type = nir_type_uint32,
 138                         .writemask = 0xF
 139                 };
 140
 141                 bi_emit(ctx, ins);
 142                 bi_schedule_barrier(ctx);
 143                 ctx->emitted_atest = true;
 144         }
 145
 146         bi_instruction blend = {
 147                 .type = BI_BLEND,
 148                 .blend_location = nir_intrinsic_base(instr),
 149                 .src = {
 150                         BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
 151                         bir_src_index(&instr->src[0])
 152                 },
 153                 .src_types = {
 154                         nir_type_uint32,
 155                         nir_type_float32,
 156                 },
 157                 .swizzle = {
 158                         { 0 },
 159                         { 0, 1, 2, 3 }
 160                 },
 161                 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
 162                 .dest_type = nir_type_uint32,
 163                 .writemask = 0xF
 164         };
 165
 166         bi_emit(ctx, blend);
 167         bi_schedule_barrier(ctx);
 168 }
 169
 170 static void
 171 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 172 {
 173         bi_instruction address = bi_load(BI_LOAD_VAR_ADDRESS, instr);
 174         address.dest = bi_make_temp(ctx);
 175         address.dest_type = nir_type_uint64;
 176         address.writemask = (1 << 8) - 1;
 177
 178         bi_instruction st = {
 179                 .type = BI_STORE_VAR,
 180                 .src = {
 181                         address.dest,
 182                         bir_src_index(&instr->src[0])
 183                 },
 184                 .src_types = {
 185                         nir_type_uint64,
 186                         nir_type_uint32
 187                 },
 188                 .swizzle = {
 189                         { 0 },
 190                         { 0, 1, 2, 3 }
 191                 }
 192         };
 193
 194         bi_emit(ctx, address);
 195         bi_emit(ctx, st);
 196 }
 197
 198 static void
 199 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
 200 {
 201         bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
 202         ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
 203
 204         /* TODO: Indirect access, since we need to multiply by the element
 205          * size. I believe we can get this lowering automatically via
 206          * nir_lower_io (as mul instructions) with the proper options, but this
 207          * is TODO */
 208         assert(ld.src[0] & BIR_INDEX_CONSTANT);
 209         ld.constant.u64 += ctx->sysvals.sysval_count;
 210         ld.constant.u64 *= 16;
 211
 212         bi_emit(ctx, ld);
 213 }
 214
 215 static void
 216 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
 217                 unsigned nr_components, unsigned offset)
 218 {
 219         nir_dest nir_dest;
 220
 221         /* Figure out which uniform this is */
 222         int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
 223         void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
 224
 225         /* Sysvals are prefix uniforms */
 226         unsigned uniform = ((uintptr_t) val) - 1;
 227
 228         /* Emit the read itself -- this is never indirect */
 229
 230         bi_instruction load = {
 231                 .type = BI_LOAD_UNIFORM,
 232                 .writemask = (1 << (nr_components * 4)) - 1,
 233                 .src = { BIR_INDEX_CONSTANT},
 234                 .constant = { (uniform * 16) + offset },
 235                 .dest = bir_dest_index(&nir_dest),
 236                 .dest_type = nir_type_uint32, /* TODO */
 237         };
 238
 239         bi_emit(ctx, load);
 240 }
 241
 242 static void
 243 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
 244 {
 245
 246         switch (instr->intrinsic) {
 247         case nir_intrinsic_load_barycentric_pixel:
 248                 /* stub */
 249                 break;
 250         case nir_intrinsic_load_interpolated_input:
 251         case nir_intrinsic_load_input:
 252                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 253                         bi_emit_ld_vary(ctx, instr);
 254                 else if (ctx->stage == MESA_SHADER_VERTEX)
 255                         bi_emit(ctx, bi_load(BI_LOAD_ATTR, instr));
 256                 else {
 257                         unreachable("Unsupported shader stage");
 258                 }
 259                 break;
 260
 261         case nir_intrinsic_store_output:
 262                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 263                         bi_emit_frag_out(ctx, instr);
 264                 else if (ctx->stage == MESA_SHADER_VERTEX)
 265                         bi_emit_st_vary(ctx, instr);
 266                 else
 267                         unreachable("Unsupported shader stage");
 268                 break;
 269
 270         case nir_intrinsic_load_uniform:
 271                 bi_emit_ld_uniform(ctx, instr);
 272                 break;
 273
 274         case nir_intrinsic_load_ssbo_address:
 275                 bi_emit_sysval(ctx, &instr->instr, 1, 0);
 276                 break;
 277
 278         case nir_intrinsic_get_buffer_size:
 279                 bi_emit_sysval(ctx, &instr->instr, 1, 8);
 280                 break;
 281
 282         case nir_intrinsic_load_viewport_scale:
 283         case nir_intrinsic_load_viewport_offset:
 284         case nir_intrinsic_load_num_work_groups:
 285         case nir_intrinsic_load_sampler_lod_parameters_pan:
 286                 bi_emit_sysval(ctx, &instr->instr, 3, 0);
 287                 break;
 288
 289         default:
 290                 /* todo */
 291                 break;
 292         }
 293 }
 294
 295 static void
 296 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
 297 {
 298         /* Make sure we've been lowered */
 299         assert(instr->def.num_components == 1);
 300
 301         bi_instruction move = {
 302                 .type = BI_MOV,
 303                 .dest = bir_ssa_index(&instr->def),
 304                 .dest_type = instr->def.bit_size | nir_type_uint,
 305                 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
 306                 .src = {
 307                         BIR_INDEX_CONSTANT
 308                 },
 309                 .constant = {
 310                         .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
 311                 }
 312         };
 313
 314         bi_emit(ctx, move);
 315 }
 316
 317 static enum bi_class
 318 bi_class_for_nir_alu(nir_op op)
 319 {
 320         switch (op) {
 321         case nir_op_iadd:
 322         case nir_op_fadd:
 323         case nir_op_fsub:
 324                 return BI_ADD;
 325         case nir_op_isub:
 326                 return BI_ISUB;
 327
 328         case nir_op_flt:
 329         case nir_op_fge:
 330         case nir_op_feq:
 331         case nir_op_fne:
 332         case nir_op_ilt:
 333         case nir_op_ige:
 334         case nir_op_ieq:
 335         case nir_op_ine:
 336                 return BI_CMP;
 337
 338         case nir_op_bcsel:
 339                 return BI_CSEL;
 340
 341         case nir_op_i2i8:
 342         case nir_op_i2i16:
 343         case nir_op_i2i32:
 344         case nir_op_i2i64:
 345         case nir_op_u2u8:
 346         case nir_op_u2u16:
 347         case nir_op_u2u32:
 348         case nir_op_u2u64:
 349         case nir_op_f2i16:
 350         case nir_op_f2i32:
 351         case nir_op_f2i64:
 352         case nir_op_f2u16:
 353         case nir_op_f2u32:
 354         case nir_op_f2u64:
 355         case nir_op_i2f16:
 356         case nir_op_i2f32:
 357         case nir_op_i2f64:
 358         case nir_op_u2f16:
 359         case nir_op_u2f32:
 360         case nir_op_u2f64:
 361                 return BI_CONVERT;
 362
 363         case nir_op_ffma:
 364         case nir_op_fmul:
 365                 return BI_FMA;
 366
 367         case nir_op_imin:
 368         case nir_op_imax:
 369         case nir_op_umin:
 370         case nir_op_umax:
 371         case nir_op_fmin:
 372         case nir_op_fmax:
 373                 return BI_MINMAX;
 374
 375         case nir_op_fsat:
 376         case nir_op_fneg:
 377         case nir_op_fabs:
 378         case nir_op_mov:
 379                 return BI_MOV;
 380
 381         case nir_op_frcp:
 382         case nir_op_frsq:
 383         case nir_op_fsin:
 384         case nir_op_fcos:
 385                 return BI_SPECIAL;
 386
 387         default:
 388                 unreachable("Unknown ALU op");
 389         }
 390 }
 391
 392 static enum bi_cond
 393 bi_cond_for_nir(nir_op op)
 394 {
 395         switch (op) {
 396         case nir_op_flt:
 397         case nir_op_ilt:
 398                 return BI_COND_LT;
 399         case nir_op_fge:
 400         case nir_op_ige:
 401                 return BI_COND_GE;
 402         case nir_op_feq:
 403         case nir_op_ieq:
 404                 return BI_COND_EQ;
 405         case nir_op_fne:
 406         case nir_op_ine:
 407                 return BI_COND_NE;
 408         default:
 409                 unreachable("Invalid compare");
 410         }
 411 }
 412
 413 static void
 414 emit_alu(bi_context *ctx, nir_alu_instr *instr)
 415 {
 416         /* Assume it's something we can handle normally */
 417         bi_instruction alu = {
 418                 .type = bi_class_for_nir_alu(instr->op),
 419                 .dest = bir_dest_index(&instr->dest.dest),
 420                 .dest_type = nir_op_infos[instr->op].output_type
 421                         | nir_dest_bit_size(instr->dest.dest),
 422         };
 423
 424         /* TODO: Implement lowering of special functions for older Bifrost */
 425         assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
 426
 427         if (instr->dest.dest.is_ssa) {
 428                 /* Construct a writemask */
 429                 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
 430                 unsigned comps = instr->dest.dest.ssa.num_components;
 431                 assert(comps == 1);
 432                 unsigned bits = bits_per_comp * comps;
 433                 unsigned bytes = MAX2(bits / 8, 1);
 434                 alu.writemask = (1 << bytes) - 1;
 435         } else {
 436                 unsigned comp_mask = instr->dest.write_mask;
 437
 438                 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
 439                                 comp_mask);
 440         }
 441
 442         /* We inline constants as we go. This tracks how many constants have
 443          * been inlined, since we're limited to 64-bits of constants per
 444          * instruction */
 445
 446         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 447         unsigned constants_left = (64 / dest_bits);
 448         unsigned constant_shift = 0;
 449
 450         /* Copy sources */
 451
 452         unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
 453         assert(num_inputs <= ARRAY_SIZE(alu.src));
 454
 455         for (unsigned i = 0; i < num_inputs; ++i) {
 456                 unsigned bits = nir_src_bit_size(instr->src[i].src);
 457                 alu.src_types[i] = nir_op_infos[instr->op].input_types[i]
 458                         | bits;
 459
 460                 /* Try to inline a constant */
 461                 if (nir_src_is_const(instr->src[i].src) && constants_left && (dest_bits == bits)) {
 462                         alu.constant.u64 |=
 463                                 (nir_src_as_uint(instr->src[i].src)) << constant_shift;
 464
 465                         alu.src[i] = BIR_INDEX_CONSTANT | constant_shift;
 466                         --constants_left;
 467                         constant_shift += dest_bits;
 468                         continue;
 469                 }
 470
 471                 alu.src[i] = bir_src_index(&instr->src[i].src);
 472
 473                 /* We assert scalarization above */
 474                 alu.swizzle[i][0] = instr->src[i].swizzle[0];
 475         }
 476
 477         /* Op-specific fixup */
 478         switch (instr->op) {
 479         case nir_op_fmul:
 480                 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
 481                 break;
 482         case nir_op_fsat:
 483                 alu.outmod = BIFROST_SAT; /* MOV */
 484                 break;
 485         case nir_op_fneg:
 486                 alu.src_neg[0] = true; /* MOV */
 487                 break;
 488         case nir_op_fabs:
 489                 alu.src_abs[0] = true; /* MOV */
 490                 break;
 491         case nir_op_fsub:
 492                 alu.src_neg[1] = true; /* ADD */
 493                 break;
 494         case nir_op_fmax:
 495         case nir_op_imax:
 496         case nir_op_umax:
 497                 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
 498                 break;
 499         case nir_op_frcp:
 500                 alu.op.special = BI_SPECIAL_FRCP;
 501                 break;
 502         case nir_op_frsq:
 503                 alu.op.special = BI_SPECIAL_FRSQ;
 504                 break;
 505         case nir_op_fsin:
 506                 alu.op.special = BI_SPECIAL_FSIN;
 507                 break;
 508         case nir_op_fcos:
 509                 alu.op.special = BI_SPECIAL_FCOS;
 510                 break;
 511         case nir_op_flt:
 512         case nir_op_ilt:
 513         case nir_op_fge:
 514         case nir_op_ige:
 515         case nir_op_feq:
 516         case nir_op_ieq:
 517         case nir_op_fne:
 518         case nir_op_ine:
 519                 alu.op.compare = bi_cond_for_nir(instr->op);
 520                 break;
 521         default:
 522                 break;
 523         }
 524
 525         bi_emit(ctx, alu);
 526 }
 527
 528 static void
 529 emit_instr(bi_context *ctx, struct nir_instr *instr)
 530 {
 531         switch (instr->type) {
 532         case nir_instr_type_load_const:
 533                 emit_load_const(ctx, nir_instr_as_load_const(instr));
 534                 break;
 535
 536         case nir_instr_type_intrinsic:
 537                 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
 538                 break;
 539
 540         case nir_instr_type_alu:
 541                 emit_alu(ctx, nir_instr_as_alu(instr));
 542                 break;
 543
 544 #if 0
 545         case nir_instr_type_tex:
 546                 emit_tex(ctx, nir_instr_as_tex(instr));
 547                 break;
 548 #endif
 549
 550         case nir_instr_type_jump:
 551                 emit_jump(ctx, nir_instr_as_jump(instr));
 552                 break;
 553
 554         case nir_instr_type_ssa_undef:
 555                 /* Spurious */
 556                 break;
 557
 558         default:
 559                 //unreachable("Unhandled instruction type");
 560                 break;
 561         }
 562 }
 563
 564
 565
 566 static bi_block *
 567 create_empty_block(bi_context *ctx)
 568 {
 569         bi_block *blk = rzalloc(ctx, bi_block);
 570
 571         blk->base.predecessors = _mesa_set_create(blk,
 572                         _mesa_hash_pointer,
 573                         _mesa_key_pointer_equal);
 574
 575         blk->base.name = ctx->block_name_count++;
 576
 577         return blk;
 578 }
 579
 580 static void
 581 bi_schedule_barrier(bi_context *ctx)
 582 {
 583         bi_block *temp = ctx->after_block;
 584         ctx->after_block = create_empty_block(ctx);
 585         list_addtail(&ctx->after_block->base.link, &ctx->blocks);
 586         list_inithead(&ctx->after_block->base.instructions);
 587         pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
 588         ctx->current_block = ctx->after_block;
 589         ctx->after_block = temp;
 590 }
 591
 592 static bi_block *
 593 emit_block(bi_context *ctx, nir_block *block)
 594 {
 595         if (ctx->after_block) {
 596                 ctx->current_block = ctx->after_block;
 597                 ctx->after_block = NULL;
 598         } else {
 599                 ctx->current_block = create_empty_block(ctx);
 600         }
 601
 602         list_addtail(&ctx->current_block->base.link, &ctx->blocks);
 603         list_inithead(&ctx->current_block->base.instructions);
 604
 605         nir_foreach_instr(instr, block) {
 606                 emit_instr(ctx, instr);
 607                 ++ctx->instruction_count;
 608         }
 609
 610         return ctx->current_block;
 611 }
 612
 613 /* Emits an unconditional branch to the end of the current block, returning a
 614  * pointer so the user can fill in details */
 615
 616 static bi_instruction *
 617 bi_emit_branch(bi_context *ctx)
 618 {
 619         bi_instruction branch = {
 620                 .type = BI_BRANCH,
 621                 .branch = {
 622                         .cond = BI_COND_ALWAYS
 623                 }
 624         };
 625
 626         return bi_emit(ctx, branch);
 627 }
 628
 629 /* Sets a condition for a branch by examing the NIR condition. If we're
 630  * familiar with the condition, we unwrap it to fold it into the branch
 631  * instruction. Otherwise, we consume the condition directly. We
 632  * generally use 1-bit booleans which allows us to use small types for
 633  * the conditions.
 634  */
 635
 636 static void
 637 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
 638 {
 639         /* TODO: Try to unwrap instead of always bailing */
 640         branch->src[0] = bir_src_index(cond);
 641         branch->src[1] = BIR_INDEX_ZERO;
 642         branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
 643         branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
 644 }
 645
 646 static void
 647 emit_if(bi_context *ctx, nir_if *nif)
 648 {
 649         bi_block *before_block = ctx->current_block;
 650
 651         /* Speculatively emit the branch, but we can't fill it in until later */
 652         bi_instruction *then_branch = bi_emit_branch(ctx);
 653         bi_set_branch_cond(then_branch, &nif->condition, true);
 654
 655         /* Emit the two subblocks. */
 656         bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
 657         bi_block *end_then_block = ctx->current_block;
 658
 659         /* Emit a jump from the end of the then block to the end of the else */
 660         bi_instruction *then_exit = bi_emit_branch(ctx);
 661
 662         /* Emit second block, and check if it's empty */
 663
 664         int count_in = ctx->instruction_count;
 665         bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
 666         bi_block *end_else_block = ctx->current_block;
 667         ctx->after_block = create_empty_block(ctx);
 668
 669         /* Now that we have the subblocks emitted, fix up the branches */
 670
 671         assert(then_block);
 672         assert(else_block);
 673
 674         if (ctx->instruction_count == count_in) {
 675                 /* The else block is empty, so don't emit an exit jump */
 676                 bi_remove_instruction(then_exit);
 677                 then_branch->branch.target = ctx->after_block;
 678         } else {
 679                 then_branch->branch.target = else_block;
 680                 then_exit->branch.target = ctx->after_block;
 681                 pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
 682         }
 683
 684         /* Wire up the successors */
 685
 686         pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
 687
 688         pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
 689         pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
 690 }
 691
 692 static void
 693 emit_loop(bi_context *ctx, nir_loop *nloop)
 694 {
 695         /* Remember where we are */
 696         bi_block *start_block = ctx->current_block;
 697
 698         bi_block *saved_break = ctx->break_block;
 699         bi_block *saved_continue = ctx->continue_block;
 700
 701         ctx->continue_block = create_empty_block(ctx);
 702         ctx->break_block = create_empty_block(ctx);
 703         ctx->after_block = ctx->continue_block;
 704
 705         /* Emit the body itself */
 706         emit_cf_list(ctx, &nloop->body);
 707
 708         /* Branch back to loop back */
 709         bi_instruction *br_back = bi_emit_branch(ctx);
 710         br_back->branch.target = ctx->continue_block;
 711         pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
 712         pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
 713
 714         ctx->after_block = ctx->break_block;
 715
 716         /* Pop off */
 717         ctx->break_block = saved_break;
 718         ctx->continue_block = saved_continue;
 719         ++ctx->loop_count;
 720 }
 721
 722 static bi_block *
 723 emit_cf_list(bi_context *ctx, struct exec_list *list)
 724 {
 725         bi_block *start_block = NULL;
 726
 727         foreach_list_typed(nir_cf_node, node, node, list) {
 728                 switch (node->type) {
 729                 case nir_cf_node_block: {
 730                         bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
 731
 732                         if (!start_block)
 733                                 start_block = block;
 734
 735                         break;
 736                 }
 737
 738                 case nir_cf_node_if:
 739                         emit_if(ctx, nir_cf_node_as_if(node));
 740                         break;
 741
 742                 case nir_cf_node_loop:
 743                         emit_loop(ctx, nir_cf_node_as_loop(node));
 744                         break;
 745
 746                 default:
 747                         unreachable("Unknown control flow");
 748                 }
 749         }
 750
 751         return start_block;
 752 }
 753
 754 static int
 755 glsl_type_size(const struct glsl_type *type, bool bindless)
 756 {
 757         return glsl_count_attribute_slots(type, false);
 758 }
 759
 760 static void
 761 bi_optimize_nir(nir_shader *nir)
 762 {
 763         bool progress;
 764         unsigned lower_flrp = 16 | 32 | 64;
 765
 766         NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
 767         NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
 768
 769         nir_lower_tex_options lower_tex_options = {
 770                 .lower_txs_lod = true,
 771                 .lower_txp = ~0,
 772                 .lower_tex_without_implicit_lod = true,
 773                 .lower_txd = true,
 774         };
 775
 776         NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
 777         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 778         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 779
 780         do {
 781                 progress = false;
 782
 783                 NIR_PASS(progress, nir, nir_lower_var_copies);
 784                 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
 785
 786                 NIR_PASS(progress, nir, nir_copy_prop);
 787                 NIR_PASS(progress, nir, nir_opt_remove_phis);
 788                 NIR_PASS(progress, nir, nir_opt_dce);
 789                 NIR_PASS(progress, nir, nir_opt_dead_cf);
 790                 NIR_PASS(progress, nir, nir_opt_cse);
 791                 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
 792                 NIR_PASS(progress, nir, nir_opt_algebraic);
 793                 NIR_PASS(progress, nir, nir_opt_constant_folding);
 794
 795                 if (lower_flrp != 0) {
 796                         bool lower_flrp_progress = false;
 797                         NIR_PASS(lower_flrp_progress,
 798                                  nir,
 799                                  nir_lower_flrp,
 800                                  lower_flrp,
 801                                  false /* always_precise */,
 802                                  nir->options->lower_ffma);
 803                         if (lower_flrp_progress) {
 804                                 NIR_PASS(progress, nir,
 805                                          nir_opt_constant_folding);
 806                                 progress = true;
 807                         }
 808
 809                         /* Nothing should rematerialize any flrps, so we only
 810                          * need to do this lowering once.
 811                          */
 812                         lower_flrp = 0;
 813                 }
 814
 815                 NIR_PASS(progress, nir, nir_opt_undef);
 816                 NIR_PASS(progress, nir, nir_opt_loop_unroll,
 817                          nir_var_shader_in |
 818                          nir_var_shader_out |
 819                          nir_var_function_temp);
 820         } while (progress);
 821
 822         NIR_PASS(progress, nir, nir_opt_algebraic_late);
 823         NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
 824         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 825         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 826
 827         /* Take us out of SSA */
 828         NIR_PASS(progress, nir, nir_lower_locals_to_regs);
 829         NIR_PASS(progress, nir, nir_convert_from_ssa, true);
 830
 831         /* We're a primary scalar architecture but there's enough vector that
 832          * we use a vector IR so let's not also deal with scalar hacks on top
 833          * of the vector hacks */
 834
 835         NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
 836         NIR_PASS(progress, nir, nir_lower_vec_to_movs);
 837         NIR_PASS(progress, nir, nir_opt_dce);
 838 }
 839
 840 void
 841 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
 842 {
 843         bi_context *ctx = rzalloc(NULL, bi_context);
 844         ctx->nir = nir;
 845         ctx->stage = nir->info.stage;
 846         ctx->quirks = bifrost_get_quirks(product_id);
 847         list_inithead(&ctx->blocks);
 848
 849         /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
 850          * (so we don't accidentally duplicate the epilogue since mesa/st has
 851          * messed with our I/O quite a bit already) */
 852
 853         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 854
 855         if (ctx->stage == MESA_SHADER_VERTEX) {
 856                 NIR_PASS_V(nir, nir_lower_viewport_transform);
 857                 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
 858         }
 859
 860         NIR_PASS_V(nir, nir_split_var_copies);
 861         NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 862         NIR_PASS_V(nir, nir_lower_var_copies);
 863         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 864         NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
 865         NIR_PASS_V(nir, nir_lower_ssbo);
 866
 867         bi_optimize_nir(nir);
 868         nir_print_shader(nir, stdout);
 869
 870         panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
 871         program->sysval_count = ctx->sysvals.sysval_count;
 872         memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
 873
 874         nir_foreach_function(func, nir) {
 875                 if (!func->impl)
 876                         continue;
 877
 878                 ctx->impl = func->impl;
 879                 emit_cf_list(ctx, &func->impl->body);
 880                 break; /* TODO: Multi-function shaders */
 881         }
 882
 883         bool progress = false;
 884
 885         do {
 886                 progress = false;
 887
 888                 bi_foreach_block(ctx, _block) {
 889                         bi_block *block = (bi_block *) _block;
 890                         progress |= bi_opt_dead_code_eliminate(ctx, block);
 891                 }
 892         } while(progress);
 893
 894         bi_print_shader(ctx, stdout);
 895         bi_schedule(ctx);
 896         bi_register_allocate(ctx);
 897         bi_print_shader(ctx, stdout);
 898         bi_pack(ctx, &program->compiled);
 899         disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
 900
 901         ralloc_free(ctx);
 902 }