src/panfrost/bifrost/bifrost_compile.c

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #include "main/mtypes.h"
  28 #include "compiler/glsl/glsl_to_nir.h"
  29 #include "compiler/nir_types.h"
  30 #include "util/imports.h"
  31 #include "compiler/nir/nir_builder.h"
  32
  33 #include "disassemble.h"
  34 #include "bifrost_compile.h"
  35 #include "bifrost_nir.h"
  36 #include "compiler.h"
  37 #include "bi_quirks.h"
  38 #include "bi_print.h"
  39
  40 static bi_block *emit_cf_list(bi_context *ctx, struct exec_list *list);
  41 static bi_instruction *bi_emit_branch(bi_context *ctx);
  42 static void bi_schedule_barrier(bi_context *ctx);
  43
  44 static void
  45 emit_jump(bi_context *ctx, nir_jump_instr *instr)
  46 {
  47         bi_instruction *branch = bi_emit_branch(ctx);
  48
  49         switch (instr->type) {
  50         case nir_jump_break:
  51                 branch->branch.target = ctx->break_block;
  52                 break;
  53         case nir_jump_continue:
  54                 branch->branch.target = ctx->continue_block;
  55                 break;
  56         default:
  57                 unreachable("Unhandled jump type");
  58         }
  59
  60         pan_block_add_successor(&ctx->current_block->base, &branch->branch.target->base);
  61 }
  62
  63 /* Gets a bytemask for a complete vecN write */
  64 static unsigned
  65 bi_mask_for_channels_32(unsigned i)
  66 {
  67         return (1 << (4 * i)) - 1;
  68 }
  69
  70 static bi_instruction
  71 bi_load(enum bi_class T, nir_intrinsic_instr *instr)
  72 {
  73         bi_instruction load = {
  74                 .type = T,
  75                 .writemask = bi_mask_for_channels_32(instr->num_components),
  76                 .src = { BIR_INDEX_CONSTANT },
  77                 .constant = { .u64 = nir_intrinsic_base(instr) },
  78         };
  79
  80         const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
  81
  82         if (info->has_dest)
  83                 load.dest = bir_dest_index(&instr->dest);
  84
  85         if (info->has_dest && info->index_map[NIR_INTRINSIC_TYPE] > 0)
  86                 load.dest_type = nir_intrinsic_type(instr);
  87
  88         nir_src *offset = nir_get_io_offset_src(instr);
  89
  90         if (nir_src_is_const(*offset))
  91                 load.constant.u64 += nir_src_as_uint(*offset);
  92         else
  93                 load.src[0] = bir_src_index(offset);
  94
  95         return load;
  96 }
  97
  98 static void
  99 bi_emit_ld_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 100 {
 101         bi_instruction ins = bi_load(BI_LOAD_VAR, instr);
 102         ins.load_vary.interp_mode = BIFROST_INTERP_DEFAULT; /* TODO */
 103         ins.load_vary.reuse = false; /* TODO */
 104         ins.load_vary.flat = instr->intrinsic != nir_intrinsic_load_interpolated_input;
 105         ins.dest_type = nir_type_float | nir_dest_bit_size(instr->dest);
 106
 107         if (nir_src_is_const(*nir_get_io_offset_src(instr))) {
 108                 /* Zero it out for direct */
 109                 ins.src[1] = BIR_INDEX_ZERO;
 110         } else {
 111                 /* R61 contains sample mask stuff, TODO RA XXX */
 112                 ins.src[1] = BIR_INDEX_REGISTER | 61;
 113         }
 114
 115         bi_emit(ctx, ins);
 116 }
 117
 118 static void
 119 bi_emit_frag_out(bi_context *ctx, nir_intrinsic_instr *instr)
 120 {
 121         if (!ctx->emitted_atest) {
 122                 bi_instruction ins = {
 123                         .type = BI_ATEST,
 124                         .src = {
 125                                 BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 126                                 bir_src_index(&instr->src[0])
 127                         },
 128                         .src_types = {
 129                                 nir_type_uint32,
 130                                 nir_type_float32
 131                         },
 132                         .swizzle = {
 133                                 { 0 },
 134                                 { 3, 0 } /* swizzle out the alpha */
 135                         },
 136                         .dest = BIR_INDEX_REGISTER | 60 /* TODO: RA */,
 137                         .dest_type = nir_type_uint32,
 138                         .writemask = 0xF
 139                 };
 140
 141                 bi_emit(ctx, ins);
 142                 bi_schedule_barrier(ctx);
 143                 ctx->emitted_atest = true;
 144         }
 145
 146         bi_instruction blend = {
 147                 .type = BI_BLEND,
 148                 .blend_location = nir_intrinsic_base(instr),
 149                 .src = {
 150                         BIR_INDEX_REGISTER | 60 /* Can this be arbitrary? */,
 151                         bir_src_index(&instr->src[0])
 152                 },
 153                 .src_types = {
 154                         nir_type_uint32,
 155                         nir_type_float32,
 156                 },
 157                 .swizzle = {
 158                         { 0 },
 159                         { 0, 1, 2, 3 }
 160                 },
 161                 .dest = BIR_INDEX_REGISTER | 48 /* Looks like magic */,
 162                 .dest_type = nir_type_uint32,
 163                 .writemask = 0xF
 164         };
 165
 166         bi_emit(ctx, blend);
 167         bi_schedule_barrier(ctx);
 168 }
 169
 170 static bi_instruction
 171 bi_load_with_r61(enum bi_class T, nir_intrinsic_instr *instr)
 172 {
 173         bi_instruction ld = bi_load(T, instr);
 174         ld.src[1] = BIR_INDEX_REGISTER | 61; /* TODO: RA */
 175         ld.src[2] = BIR_INDEX_REGISTER | 62;
 176         ld.src[3] = 0;
 177         ld.src_types[1] = nir_type_uint32;
 178         ld.src_types[2] = nir_type_uint32;
 179         ld.src_types[3] = nir_intrinsic_type(instr);
 180         return ld;
 181 }
 182
 183 static void
 184 bi_emit_st_vary(bi_context *ctx, nir_intrinsic_instr *instr)
 185 {
 186         bi_instruction address = bi_load_with_r61(BI_LOAD_VAR_ADDRESS, instr);
 187         address.dest = bi_make_temp(ctx);
 188         address.dest_type = nir_type_uint32;
 189         address.writemask = (1 << 12) - 1;
 190
 191         bi_instruction st = {
 192                 .type = BI_STORE_VAR,
 193                 .src = {
 194                         bir_src_index(&instr->src[0]),
 195                         address.dest, address.dest, address.dest,
 196                 },
 197                 .src_types = {
 198                         nir_type_uint32,
 199                         nir_type_uint32, nir_type_uint32, nir_type_uint32,
 200                 },
 201                 .swizzle = {
 202                         { 0, 1, 2, 3 },
 203                         { 0 }, { 1 }, { 2}
 204                 },
 205                 .store_channels = 4, /* TODO: WRITEMASK */
 206         };
 207
 208         bi_emit(ctx, address);
 209         bi_emit(ctx, st);
 210 }
 211
 212 static void
 213 bi_emit_ld_uniform(bi_context *ctx, nir_intrinsic_instr *instr)
 214 {
 215         bi_instruction ld = bi_load(BI_LOAD_UNIFORM, instr);
 216         ld.src[1] = BIR_INDEX_ZERO; /* TODO: UBO index */
 217
 218         /* TODO: Indirect access, since we need to multiply by the element
 219          * size. I believe we can get this lowering automatically via
 220          * nir_lower_io (as mul instructions) with the proper options, but this
 221          * is TODO */
 222         assert(ld.src[0] & BIR_INDEX_CONSTANT);
 223         ld.constant.u64 += ctx->sysvals.sysval_count;
 224         ld.constant.u64 *= 16;
 225
 226         bi_emit(ctx, ld);
 227 }
 228
 229 static void
 230 bi_emit_sysval(bi_context *ctx, nir_instr *instr,
 231                 unsigned nr_components, unsigned offset)
 232 {
 233         nir_dest nir_dest;
 234
 235         /* Figure out which uniform this is */
 236         int sysval = panfrost_sysval_for_instr(instr, &nir_dest);
 237         void *val = _mesa_hash_table_u64_search(ctx->sysvals.sysval_to_id, sysval);
 238
 239         /* Sysvals are prefix uniforms */
 240         unsigned uniform = ((uintptr_t) val) - 1;
 241
 242         /* Emit the read itself -- this is never indirect */
 243
 244         bi_instruction load = {
 245                 .type = BI_LOAD_UNIFORM,
 246                 .writemask = (1 << (nr_components * 4)) - 1,
 247                 .src = { BIR_INDEX_CONSTANT, BIR_INDEX_ZERO },
 248                 .constant = { (uniform * 16) + offset },
 249                 .dest = bir_dest_index(&nir_dest),
 250                 .dest_type = nir_type_uint32, /* TODO */
 251         };
 252
 253         bi_emit(ctx, load);
 254 }
 255
 256 static void
 257 emit_intrinsic(bi_context *ctx, nir_intrinsic_instr *instr)
 258 {
 259
 260         switch (instr->intrinsic) {
 261         case nir_intrinsic_load_barycentric_pixel:
 262                 /* stub */
 263                 break;
 264         case nir_intrinsic_load_interpolated_input:
 265         case nir_intrinsic_load_input:
 266                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 267                         bi_emit_ld_vary(ctx, instr);
 268                 else if (ctx->stage == MESA_SHADER_VERTEX)
 269                         bi_emit(ctx, bi_load_with_r61(BI_LOAD_ATTR, instr));
 270                 else {
 271                         unreachable("Unsupported shader stage");
 272                 }
 273                 break;
 274
 275         case nir_intrinsic_store_output:
 276                 if (ctx->stage == MESA_SHADER_FRAGMENT)
 277                         bi_emit_frag_out(ctx, instr);
 278                 else if (ctx->stage == MESA_SHADER_VERTEX)
 279                         bi_emit_st_vary(ctx, instr);
 280                 else
 281                         unreachable("Unsupported shader stage");
 282                 break;
 283
 284         case nir_intrinsic_load_uniform:
 285                 bi_emit_ld_uniform(ctx, instr);
 286                 break;
 287
 288         case nir_intrinsic_load_ssbo_address:
 289                 bi_emit_sysval(ctx, &instr->instr, 1, 0);
 290                 break;
 291
 292         case nir_intrinsic_get_buffer_size:
 293                 bi_emit_sysval(ctx, &instr->instr, 1, 8);
 294                 break;
 295
 296         case nir_intrinsic_load_viewport_scale:
 297         case nir_intrinsic_load_viewport_offset:
 298         case nir_intrinsic_load_num_work_groups:
 299         case nir_intrinsic_load_sampler_lod_parameters_pan:
 300                 bi_emit_sysval(ctx, &instr->instr, 3, 0);
 301                 break;
 302
 303         default:
 304                 /* todo */
 305                 break;
 306         }
 307 }
 308
 309 static void
 310 emit_load_const(bi_context *ctx, nir_load_const_instr *instr)
 311 {
 312         /* Make sure we've been lowered */
 313         assert(instr->def.num_components == 1);
 314
 315         bi_instruction move = {
 316                 .type = BI_MOV,
 317                 .dest = bir_ssa_index(&instr->def),
 318                 .dest_type = instr->def.bit_size | nir_type_uint,
 319                 .writemask = (1 << (instr->def.bit_size / 8)) - 1,
 320                 .src = {
 321                         BIR_INDEX_CONSTANT
 322                 },
 323                 .constant = {
 324                         .u64 = nir_const_value_as_uint(instr->value[0], instr->def.bit_size)
 325                 }
 326         };
 327
 328         bi_emit(ctx, move);
 329 }
 330
 331 #define BI_CASE_CMP(op) \
 332         case op##8: \
 333         case op##16: \
 334         case op##32: \
 335
 336 static enum bi_class
 337 bi_class_for_nir_alu(nir_op op)
 338 {
 339         switch (op) {
 340         case nir_op_iadd:
 341         case nir_op_fadd:
 342         case nir_op_fsub:
 343                 return BI_ADD;
 344         case nir_op_isub:
 345                 return BI_ISUB;
 346
 347         BI_CASE_CMP(nir_op_flt)
 348         BI_CASE_CMP(nir_op_fge)
 349         BI_CASE_CMP(nir_op_feq)
 350         BI_CASE_CMP(nir_op_fne)
 351         BI_CASE_CMP(nir_op_ilt)
 352         BI_CASE_CMP(nir_op_ige)
 353         BI_CASE_CMP(nir_op_ieq)
 354         BI_CASE_CMP(nir_op_ine)
 355                 return BI_CMP;
 356
 357         case nir_op_b8csel:
 358         case nir_op_b16csel:
 359         case nir_op_b32csel:
 360                 return BI_CSEL;
 361
 362         case nir_op_i2i8:
 363         case nir_op_i2i16:
 364         case nir_op_i2i32:
 365         case nir_op_i2i64:
 366         case nir_op_u2u8:
 367         case nir_op_u2u16:
 368         case nir_op_u2u32:
 369         case nir_op_u2u64:
 370         case nir_op_f2i16:
 371         case nir_op_f2i32:
 372         case nir_op_f2i64:
 373         case nir_op_f2u16:
 374         case nir_op_f2u32:
 375         case nir_op_f2u64:
 376         case nir_op_i2f16:
 377         case nir_op_i2f32:
 378         case nir_op_i2f64:
 379         case nir_op_u2f16:
 380         case nir_op_u2f32:
 381         case nir_op_u2f64:
 382         case nir_op_f2f16:
 383         case nir_op_f2f32:
 384         case nir_op_f2f64:
 385         case nir_op_f2fmp:
 386                 return BI_CONVERT;
 387
 388         case nir_op_vec2:
 389         case nir_op_vec3:
 390         case nir_op_vec4:
 391                 return BI_COMBINE;
 392
 393         case nir_op_vec8:
 394         case nir_op_vec16:
 395                 unreachable("should've been lowered");
 396
 397         case nir_op_ffma:
 398         case nir_op_fmul:
 399                 return BI_FMA;
 400
 401         case nir_op_imin:
 402         case nir_op_imax:
 403         case nir_op_umin:
 404         case nir_op_umax:
 405         case nir_op_fmin:
 406         case nir_op_fmax:
 407                 return BI_MINMAX;
 408
 409         case nir_op_fsat:
 410         case nir_op_fneg:
 411         case nir_op_fabs:
 412                 return BI_FMOV;
 413         case nir_op_mov:
 414                 return BI_MOV;
 415
 416         case nir_op_fround_even:
 417         case nir_op_fceil:
 418         case nir_op_ffloor:
 419         case nir_op_ftrunc:
 420                 return BI_ROUND;
 421
 422         case nir_op_frcp:
 423         case nir_op_frsq:
 424         case nir_op_fsin:
 425         case nir_op_fcos:
 426                 return BI_SPECIAL;
 427
 428         default:
 429                 unreachable("Unknown ALU op");
 430         }
 431 }
 432
 433 /* Gets a bi_cond for a given NIR comparison opcode. In soft mode, it will
 434  * return BI_COND_ALWAYS as a sentinel if it fails to do so (when used for
 435  * optimizations). Otherwise it will bail (when used for primary code
 436  * generation). */
 437
 438 static enum bi_cond
 439 bi_cond_for_nir(nir_op op, bool soft)
 440 {
 441         switch (op) {
 442         BI_CASE_CMP(nir_op_flt)
 443         BI_CASE_CMP(nir_op_ilt)
 444                 return BI_COND_LT;
 445
 446         BI_CASE_CMP(nir_op_fge)
 447         BI_CASE_CMP(nir_op_ige)
 448                 return BI_COND_GE;
 449
 450         BI_CASE_CMP(nir_op_feq)
 451         BI_CASE_CMP(nir_op_ieq)
 452                 return BI_COND_EQ;
 453
 454         BI_CASE_CMP(nir_op_fne)
 455         BI_CASE_CMP(nir_op_ine)
 456                 return BI_COND_NE;
 457         default:
 458                 if (soft)
 459                         return BI_COND_ALWAYS;
 460                 else
 461                         unreachable("Invalid compare");
 462         }
 463 }
 464
 465 static void
 466 bi_copy_src(bi_instruction *alu, nir_alu_instr *instr, unsigned i, unsigned to,
 467                 unsigned *constants_left, unsigned *constant_shift)
 468 {
 469         unsigned bits = nir_src_bit_size(instr->src[i].src);
 470         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 471
 472         alu->src_types[to] = nir_op_infos[instr->op].input_types[i]
 473                 | bits;
 474
 475         /* Try to inline a constant */
 476         if (nir_src_is_const(instr->src[i].src) && *constants_left && (dest_bits == bits)) {
 477                 alu->constant.u64 |=
 478                         (nir_src_as_uint(instr->src[i].src)) << *constant_shift;
 479
 480                 alu->src[to] = BIR_INDEX_CONSTANT | (*constant_shift);
 481                 --(*constants_left);
 482                 (*constant_shift) += dest_bits;
 483                 return;
 484         }
 485
 486         alu->src[to] = bir_src_index(&instr->src[i].src);
 487
 488         /* We assert scalarization above */
 489         alu->swizzle[to][0] = instr->src[i].swizzle[0];
 490 }
 491
 492 static void
 493 bi_fuse_csel_cond(bi_instruction *csel, nir_alu_src cond,
 494                 unsigned *constants_left, unsigned *constant_shift)
 495 {
 496         /* Bail for vector weirdness */
 497         if (cond.swizzle[0] != 0)
 498                 return;
 499
 500         if (!cond.src.is_ssa)
 501                 return;
 502
 503         nir_ssa_def *def = cond.src.ssa;
 504         nir_instr *parent = def->parent_instr;
 505
 506         if (parent->type != nir_instr_type_alu)
 507                 return;
 508
 509         nir_alu_instr *alu = nir_instr_as_alu(parent);
 510
 511         /* Try to match a condition */
 512         enum bi_cond bcond = bi_cond_for_nir(alu->op, true);
 513
 514         if (bcond == BI_COND_ALWAYS)
 515                 return;
 516
 517         /* We found one, let's fuse it in */
 518         csel->csel_cond = bcond;
 519         bi_copy_src(csel, alu, 0, 0, constants_left, constant_shift);
 520         bi_copy_src(csel, alu, 1, 3, constants_left, constant_shift);
 521 }
 522
 523 static void
 524 emit_alu(bi_context *ctx, nir_alu_instr *instr)
 525 {
 526         /* Assume it's something we can handle normally */
 527         bi_instruction alu = {
 528                 .type = bi_class_for_nir_alu(instr->op),
 529                 .dest = bir_dest_index(&instr->dest.dest),
 530                 .dest_type = nir_op_infos[instr->op].output_type
 531                         | nir_dest_bit_size(instr->dest.dest),
 532         };
 533
 534         /* TODO: Implement lowering of special functions for older Bifrost */
 535         assert((alu.type != BI_SPECIAL) || !(ctx->quirks & BIFROST_NO_FAST_OP));
 536
 537         if (instr->dest.dest.is_ssa) {
 538                 /* Construct a writemask */
 539                 unsigned bits_per_comp = instr->dest.dest.ssa.bit_size;
 540                 unsigned comps = instr->dest.dest.ssa.num_components;
 541
 542                 if (alu.type != BI_COMBINE)
 543                         assert(comps == 1);
 544
 545                 unsigned bits = bits_per_comp * comps;
 546                 unsigned bytes = bits / 8;
 547                 alu.writemask = (1 << bytes) - 1;
 548         } else {
 549                 unsigned comp_mask = instr->dest.write_mask;
 550
 551                 alu.writemask = pan_to_bytemask(nir_dest_bit_size(instr->dest.dest),
 552                                 comp_mask);
 553         }
 554
 555         /* We inline constants as we go. This tracks how many constants have
 556          * been inlined, since we're limited to 64-bits of constants per
 557          * instruction */
 558
 559         unsigned dest_bits = nir_dest_bit_size(instr->dest.dest);
 560         unsigned constants_left = (64 / dest_bits);
 561         unsigned constant_shift = 0;
 562
 563         /* Copy sources */
 564
 565         unsigned num_inputs = nir_op_infos[instr->op].num_inputs;
 566         assert(num_inputs <= ARRAY_SIZE(alu.src));
 567
 568         for (unsigned i = 0; i < num_inputs; ++i)
 569                 bi_copy_src(&alu, instr, i, i, &constants_left, &constant_shift);
 570
 571         /* Op-specific fixup */
 572         switch (instr->op) {
 573         case nir_op_fmul:
 574                 alu.src[2] = BIR_INDEX_ZERO; /* FMA */
 575                 alu.src_types[2] = alu.src_types[1];
 576                 break;
 577         case nir_op_fsat:
 578                 alu.outmod = BIFROST_SAT; /* FMOV */
 579                 break;
 580         case nir_op_fneg:
 581                 alu.src_neg[0] = true; /* FMOV */
 582                 break;
 583         case nir_op_fabs:
 584                 alu.src_abs[0] = true; /* FMOV */
 585                 break;
 586         case nir_op_fsub:
 587                 alu.src_neg[1] = true; /* FADD */
 588                 break;
 589         case nir_op_fmax:
 590         case nir_op_imax:
 591         case nir_op_umax:
 592                 alu.op.minmax = BI_MINMAX_MAX; /* MINMAX */
 593                 break;
 594         case nir_op_frcp:
 595                 alu.op.special = BI_SPECIAL_FRCP;
 596                 break;
 597         case nir_op_frsq:
 598                 alu.op.special = BI_SPECIAL_FRSQ;
 599                 break;
 600         case nir_op_fsin:
 601                 alu.op.special = BI_SPECIAL_FSIN;
 602                 break;
 603         case nir_op_fcos:
 604                 alu.op.special = BI_SPECIAL_FCOS;
 605                 break;
 606         BI_CASE_CMP(nir_op_flt)
 607         BI_CASE_CMP(nir_op_ilt)
 608         BI_CASE_CMP(nir_op_fge)
 609         BI_CASE_CMP(nir_op_ige)
 610         BI_CASE_CMP(nir_op_feq)
 611         BI_CASE_CMP(nir_op_ieq)
 612         BI_CASE_CMP(nir_op_fne)
 613         BI_CASE_CMP(nir_op_ine)
 614                 alu.op.compare = bi_cond_for_nir(instr->op, false);
 615                 break;
 616         case nir_op_fround_even:
 617                 alu.op.round = BI_ROUND_MODE;
 618                 alu.roundmode = BIFROST_RTE;
 619                 break;
 620         case nir_op_fceil:
 621                 alu.op.round = BI_ROUND_MODE;
 622                 alu.roundmode = BIFROST_RTP;
 623                 break;
 624         case nir_op_ffloor:
 625                 alu.op.round = BI_ROUND_MODE;
 626                 alu.roundmode = BIFROST_RTN;
 627                 break;
 628         case nir_op_ftrunc:
 629                 alu.op.round = BI_ROUND_MODE;
 630                 alu.roundmode = BIFROST_RTZ;
 631                 break;
 632         default:
 633                 break;
 634         }
 635
 636         if (alu.type == BI_CSEL) {
 637                 /* Default to csel3 */
 638                 alu.csel_cond = BI_COND_NE;
 639                 alu.src[3] = BIR_INDEX_ZERO;
 640                 alu.src_types[3] = alu.src_types[0];
 641
 642                 bi_fuse_csel_cond(&alu, instr->src[0],
 643                                 &constants_left, &constant_shift);
 644         }
 645
 646         bi_emit(ctx, alu);
 647 }
 648
 649 static void
 650 emit_instr(bi_context *ctx, struct nir_instr *instr)
 651 {
 652         switch (instr->type) {
 653         case nir_instr_type_load_const:
 654                 emit_load_const(ctx, nir_instr_as_load_const(instr));
 655                 break;
 656
 657         case nir_instr_type_intrinsic:
 658                 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
 659                 break;
 660
 661         case nir_instr_type_alu:
 662                 emit_alu(ctx, nir_instr_as_alu(instr));
 663                 break;
 664
 665 #if 0
 666         case nir_instr_type_tex:
 667                 emit_tex(ctx, nir_instr_as_tex(instr));
 668                 break;
 669 #endif
 670
 671         case nir_instr_type_jump:
 672                 emit_jump(ctx, nir_instr_as_jump(instr));
 673                 break;
 674
 675         case nir_instr_type_ssa_undef:
 676                 /* Spurious */
 677                 break;
 678
 679         default:
 680                 //unreachable("Unhandled instruction type");
 681                 break;
 682         }
 683 }
 684
 685
 686
 687 static bi_block *
 688 create_empty_block(bi_context *ctx)
 689 {
 690         bi_block *blk = rzalloc(ctx, bi_block);
 691
 692         blk->base.predecessors = _mesa_set_create(blk,
 693                         _mesa_hash_pointer,
 694                         _mesa_key_pointer_equal);
 695
 696         blk->base.name = ctx->block_name_count++;
 697
 698         return blk;
 699 }
 700
 701 static void
 702 bi_schedule_barrier(bi_context *ctx)
 703 {
 704         bi_block *temp = ctx->after_block;
 705         ctx->after_block = create_empty_block(ctx);
 706         list_addtail(&ctx->after_block->base.link, &ctx->blocks);
 707         list_inithead(&ctx->after_block->base.instructions);
 708         pan_block_add_successor(&ctx->current_block->base, &ctx->after_block->base);
 709         ctx->current_block = ctx->after_block;
 710         ctx->after_block = temp;
 711 }
 712
 713 static bi_block *
 714 emit_block(bi_context *ctx, nir_block *block)
 715 {
 716         if (ctx->after_block) {
 717                 ctx->current_block = ctx->after_block;
 718                 ctx->after_block = NULL;
 719         } else {
 720                 ctx->current_block = create_empty_block(ctx);
 721         }
 722
 723         list_addtail(&ctx->current_block->base.link, &ctx->blocks);
 724         list_inithead(&ctx->current_block->base.instructions);
 725
 726         nir_foreach_instr(instr, block) {
 727                 emit_instr(ctx, instr);
 728                 ++ctx->instruction_count;
 729         }
 730
 731         return ctx->current_block;
 732 }
 733
 734 /* Emits an unconditional branch to the end of the current block, returning a
 735  * pointer so the user can fill in details */
 736
 737 static bi_instruction *
 738 bi_emit_branch(bi_context *ctx)
 739 {
 740         bi_instruction branch = {
 741                 .type = BI_BRANCH,
 742                 .branch = {
 743                         .cond = BI_COND_ALWAYS
 744                 }
 745         };
 746
 747         return bi_emit(ctx, branch);
 748 }
 749
 750 /* Sets a condition for a branch by examing the NIR condition. If we're
 751  * familiar with the condition, we unwrap it to fold it into the branch
 752  * instruction. Otherwise, we consume the condition directly. We
 753  * generally use 1-bit booleans which allows us to use small types for
 754  * the conditions.
 755  */
 756
 757 static void
 758 bi_set_branch_cond(bi_instruction *branch, nir_src *cond, bool invert)
 759 {
 760         /* TODO: Try to unwrap instead of always bailing */
 761         branch->src[0] = bir_src_index(cond);
 762         branch->src[1] = BIR_INDEX_ZERO;
 763         branch->src_types[0] = branch->src_types[1] = nir_type_uint16;
 764         branch->branch.cond = invert ? BI_COND_EQ : BI_COND_NE;
 765 }
 766
 767 static void
 768 emit_if(bi_context *ctx, nir_if *nif)
 769 {
 770         bi_block *before_block = ctx->current_block;
 771
 772         /* Speculatively emit the branch, but we can't fill it in until later */
 773         bi_instruction *then_branch = bi_emit_branch(ctx);
 774         bi_set_branch_cond(then_branch, &nif->condition, true);
 775
 776         /* Emit the two subblocks. */
 777         bi_block *then_block = emit_cf_list(ctx, &nif->then_list);
 778         bi_block *end_then_block = ctx->current_block;
 779
 780         /* Emit a jump from the end of the then block to the end of the else */
 781         bi_instruction *then_exit = bi_emit_branch(ctx);
 782
 783         /* Emit second block, and check if it's empty */
 784
 785         int count_in = ctx->instruction_count;
 786         bi_block *else_block = emit_cf_list(ctx, &nif->else_list);
 787         bi_block *end_else_block = ctx->current_block;
 788         ctx->after_block = create_empty_block(ctx);
 789
 790         /* Now that we have the subblocks emitted, fix up the branches */
 791
 792         assert(then_block);
 793         assert(else_block);
 794
 795         if (ctx->instruction_count == count_in) {
 796                 /* The else block is empty, so don't emit an exit jump */
 797                 bi_remove_instruction(then_exit);
 798                 then_branch->branch.target = ctx->after_block;
 799         } else {
 800                 then_branch->branch.target = else_block;
 801                 then_exit->branch.target = ctx->after_block;
 802                 pan_block_add_successor(&end_then_block->base, &then_exit->branch.target->base);
 803         }
 804
 805         /* Wire up the successors */
 806
 807         pan_block_add_successor(&before_block->base, &then_branch->branch.target->base); /* then_branch */
 808
 809         pan_block_add_successor(&before_block->base, &then_block->base); /* fallthrough */
 810         pan_block_add_successor(&end_else_block->base, &ctx->after_block->base); /* fallthrough */
 811 }
 812
 813 static void
 814 emit_loop(bi_context *ctx, nir_loop *nloop)
 815 {
 816         /* Remember where we are */
 817         bi_block *start_block = ctx->current_block;
 818
 819         bi_block *saved_break = ctx->break_block;
 820         bi_block *saved_continue = ctx->continue_block;
 821
 822         ctx->continue_block = create_empty_block(ctx);
 823         ctx->break_block = create_empty_block(ctx);
 824         ctx->after_block = ctx->continue_block;
 825
 826         /* Emit the body itself */
 827         emit_cf_list(ctx, &nloop->body);
 828
 829         /* Branch back to loop back */
 830         bi_instruction *br_back = bi_emit_branch(ctx);
 831         br_back->branch.target = ctx->continue_block;
 832         pan_block_add_successor(&start_block->base, &ctx->continue_block->base);
 833         pan_block_add_successor(&ctx->current_block->base, &ctx->continue_block->base);
 834
 835         ctx->after_block = ctx->break_block;
 836
 837         /* Pop off */
 838         ctx->break_block = saved_break;
 839         ctx->continue_block = saved_continue;
 840         ++ctx->loop_count;
 841 }
 842
 843 static bi_block *
 844 emit_cf_list(bi_context *ctx, struct exec_list *list)
 845 {
 846         bi_block *start_block = NULL;
 847
 848         foreach_list_typed(nir_cf_node, node, node, list) {
 849                 switch (node->type) {
 850                 case nir_cf_node_block: {
 851                         bi_block *block = emit_block(ctx, nir_cf_node_as_block(node));
 852
 853                         if (!start_block)
 854                                 start_block = block;
 855
 856                         break;
 857                 }
 858
 859                 case nir_cf_node_if:
 860                         emit_if(ctx, nir_cf_node_as_if(node));
 861                         break;
 862
 863                 case nir_cf_node_loop:
 864                         emit_loop(ctx, nir_cf_node_as_loop(node));
 865                         break;
 866
 867                 default:
 868                         unreachable("Unknown control flow");
 869                 }
 870         }
 871
 872         return start_block;
 873 }
 874
 875 static int
 876 glsl_type_size(const struct glsl_type *type, bool bindless)
 877 {
 878         return glsl_count_attribute_slots(type, false);
 879 }
 880
 881 static void
 882 bi_optimize_nir(nir_shader *nir)
 883 {
 884         bool progress;
 885         unsigned lower_flrp = 16 | 32 | 64;
 886
 887         NIR_PASS(progress, nir, nir_lower_regs_to_ssa);
 888         NIR_PASS(progress, nir, nir_lower_idiv, nir_lower_idiv_fast);
 889
 890         nir_lower_tex_options lower_tex_options = {
 891                 .lower_txs_lod = true,
 892                 .lower_txp = ~0,
 893                 .lower_tex_without_implicit_lod = true,
 894                 .lower_txd = true,
 895         };
 896
 897         NIR_PASS(progress, nir, nir_lower_tex, &lower_tex_options);
 898         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 899         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 900
 901         do {
 902                 progress = false;
 903
 904                 NIR_PASS(progress, nir, nir_lower_var_copies);
 905                 NIR_PASS(progress, nir, nir_lower_vars_to_ssa);
 906
 907                 NIR_PASS(progress, nir, nir_copy_prop);
 908                 NIR_PASS(progress, nir, nir_opt_remove_phis);
 909                 NIR_PASS(progress, nir, nir_opt_dce);
 910                 NIR_PASS(progress, nir, nir_opt_dead_cf);
 911                 NIR_PASS(progress, nir, nir_opt_cse);
 912                 NIR_PASS(progress, nir, nir_opt_peephole_select, 64, false, true);
 913                 NIR_PASS(progress, nir, nir_opt_algebraic);
 914                 NIR_PASS(progress, nir, nir_opt_constant_folding);
 915
 916                 if (lower_flrp != 0) {
 917                         bool lower_flrp_progress = false;
 918                         NIR_PASS(lower_flrp_progress,
 919                                  nir,
 920                                  nir_lower_flrp,
 921                                  lower_flrp,
 922                                  false /* always_precise */,
 923                                  nir->options->lower_ffma);
 924                         if (lower_flrp_progress) {
 925                                 NIR_PASS(progress, nir,
 926                                          nir_opt_constant_folding);
 927                                 progress = true;
 928                         }
 929
 930                         /* Nothing should rematerialize any flrps, so we only
 931                          * need to do this lowering once.
 932                          */
 933                         lower_flrp = 0;
 934                 }
 935
 936                 NIR_PASS(progress, nir, nir_opt_undef);
 937                 NIR_PASS(progress, nir, nir_opt_loop_unroll,
 938                          nir_var_shader_in |
 939                          nir_var_shader_out |
 940                          nir_var_function_temp);
 941         } while (progress);
 942
 943         NIR_PASS(progress, nir, nir_opt_algebraic_late);
 944         NIR_PASS(progress, nir, nir_lower_bool_to_int32);
 945         NIR_PASS(progress, nir, bifrost_nir_lower_algebraic_late);
 946         NIR_PASS(progress, nir, nir_lower_alu_to_scalar, NULL, NULL);
 947         NIR_PASS(progress, nir, nir_lower_load_const_to_scalar);
 948
 949         /* Take us out of SSA */
 950         NIR_PASS(progress, nir, nir_lower_locals_to_regs);
 951         NIR_PASS(progress, nir, nir_move_vec_src_uses_to_dest);
 952         NIR_PASS(progress, nir, nir_convert_from_ssa, true);
 953 }
 954
 955 void
 956 bifrost_compile_shader_nir(nir_shader *nir, panfrost_program *program, unsigned product_id)
 957 {
 958         bi_context *ctx = rzalloc(NULL, bi_context);
 959         ctx->nir = nir;
 960         ctx->stage = nir->info.stage;
 961         ctx->quirks = bifrost_get_quirks(product_id);
 962         list_inithead(&ctx->blocks);
 963
 964         /* Lower gl_Position pre-optimisation, but after lowering vars to ssa
 965          * (so we don't accidentally duplicate the epilogue since mesa/st has
 966          * messed with our I/O quite a bit already) */
 967
 968         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 969
 970         if (ctx->stage == MESA_SHADER_VERTEX) {
 971                 NIR_PASS_V(nir, nir_lower_viewport_transform);
 972                 NIR_PASS_V(nir, nir_lower_point_size, 1.0, 1024.0);
 973         }
 974
 975         NIR_PASS_V(nir, nir_split_var_copies);
 976         NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 977         NIR_PASS_V(nir, nir_lower_var_copies);
 978         NIR_PASS_V(nir, nir_lower_vars_to_ssa);
 979         NIR_PASS_V(nir, nir_lower_io, nir_var_all, glsl_type_size, 0);
 980         NIR_PASS_V(nir, nir_lower_ssbo);
 981
 982         bi_optimize_nir(nir);
 983         nir_print_shader(nir, stdout);
 984
 985         panfrost_nir_assign_sysvals(&ctx->sysvals, nir);
 986         program->sysval_count = ctx->sysvals.sysval_count;
 987         memcpy(program->sysvals, ctx->sysvals.sysvals, sizeof(ctx->sysvals.sysvals[0]) * ctx->sysvals.sysval_count);
 988
 989         nir_foreach_function(func, nir) {
 990                 if (!func->impl)
 991                         continue;
 992
 993                 ctx->impl = func->impl;
 994                 emit_cf_list(ctx, &func->impl->body);
 995                 break; /* TODO: Multi-function shaders */
 996         }
 997
 998         bi_foreach_block(ctx, _block) {
 999                 bi_block *block = (bi_block *) _block;
1000                 bi_lower_combine(ctx, block);
1001         }
1002
1003         bool progress = false;
1004
1005         do {
1006                 progress = false;
1007
1008                 bi_foreach_block(ctx, _block) {
1009                         bi_block *block = (bi_block *) _block;
1010                         progress |= bi_opt_dead_code_eliminate(ctx, block);
1011                 }
1012         } while(progress);
1013
1014         bi_print_shader(ctx, stdout);
1015         bi_schedule(ctx);
1016         bi_register_allocate(ctx);
1017         bi_print_shader(ctx, stdout);
1018         bi_pack(ctx, &program->compiled);
1019         disassemble_bifrost(stdout, program->compiled.data, program->compiled.size, true);
1020
1021         ralloc_free(ctx);
1022 }