2 * Copyright (C) 2020 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
27 #ifndef __BIFROST_COMPILER_H
28 #define __BIFROST_COMPILER_H
31 #include "compiler/nir/nir.h"
32 #include "panfrost/util/pan_ir.h"
34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
35 * ADD with two completely different opcodes, and opcodes can be varying
36 * length in some cases. Then we have different opcodes for int vs float
37 * and then sometimes even for different typesizes. Further, virtually
38 * every op has a number of flags which depend on the op. In constrast
39 * to Midgard where you have a strict ALU/LDST/TEX division and within
40 * ALU you have strict int/float and that's it... here it's a *lot* more
41 * involved. As such, we use something much higher level for our IR,
42 * encoding "classes" of operations, letting the opcode details get
43 * sorted out at emit time.
45 * Please keep this list alphabetized. Please use a dictionary if you
46 * don't know how to do that.
75 BI_SPECIAL
, /* _FAST on supported GPUs */
83 /* Properties of a class... */
84 extern unsigned bi_class_props
[BI_NUM_CLASSES
];
86 /* abs/neg/outmod valid for a float op */
87 #define BI_MODS (1 << 0)
89 /* Generic enough that little class-specific information is required. In other
90 * words, it acts as a "normal" ALU op, even if the encoding ends up being
91 * irregular enough to warrant a separate class */
92 #define BI_GENERIC (1 << 1)
94 /* Accepts a bifrost_roundmode */
95 #define BI_ROUNDMODE (1 << 2)
97 /* Can be scheduled to FMA */
98 #define BI_SCHED_FMA (1 << 3)
100 /* Can be scheduled to ADD */
101 #define BI_SCHED_ADD (1 << 4)
103 /* Most ALU ops can do either, actually */
104 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
106 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
107 * nopped out. Used for _FAST operations. */
108 #define BI_SCHED_SLOW (1 << 5)
110 /* Swizzling allowed for the 8/16-bit source */
111 #define BI_SWIZZLABLE (1 << 6)
113 /* For scheduling purposes this is a high latency instruction and must be at
114 * the end of a clause. Implies ADD */
115 #define BI_SCHED_HI_LATENCY (1 << 7)
117 /* Intrinsic is vectorized and should read 4 components in the first source
118 * regardless of writemask */
119 #define BI_VECTOR (1 << 8)
121 /* Use a data register for src0/dest respectively, bypassing the usual
122 * register accessor. Mutually exclusive. */
123 #define BI_DATA_REG_SRC (1 << 9)
124 #define BI_DATA_REG_DEST (1 << 10)
126 /* Quirk: cannot encode multiple abs on FMA in fp16 mode */
127 #define BI_NO_ABS_ABS_FP16_FMA (1 << 11)
129 /* It can't get any worse than csel4... can it? */
130 #define BIR_SRC_COUNT 4
133 struct bi_load_vary
{
134 enum bifrost_interp_mode interp_mode
;
139 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
140 * the target. We forward declare bi_block since this is mildly circular (not
141 * strictly, but this order of the file makes more sense I think)
143 * We define our own enum of conditions since the conditions in the hardware
144 * packed in crazy ways that would make manipulation unweildly (meaning changes
145 * based on port swapping, etc), so we defer dealing with that until emit time.
146 * Likewise, we expose NIR types instead of the crazy branch types, although
147 * the restrictions do eventually apply of course. */
162 /* Types are specified in src_types and must be compatible (either both
163 * int, or both float, 16/32, and same size or 32/16 if float. Types
164 * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
167 struct bi_block
*target
;
170 /* Opcodes within a class */
183 BI_ROUND_MODE
, /* use round mode */
184 BI_ROUND_ROUND
/* i.e.: fround() */
188 /* fp32 log2() with low precision, suitable for GL or half_log2() in
189 * CL. In the first argument, takes x. Letting u be such that x =
190 * 2^{-m} u with m integer and 0.75 <= u < 1.5, returns
191 * log2(u) / (u - 1). */
193 BI_TABLE_LOG2_U_OVER_U_1_LOW
,
197 /* Takes two fp32 arguments and returns x + frexp(y). Used in
198 * low-precision log2 argument reduction on newer models. */
200 BI_REDUCE_ADD_FREXPM
,
211 /* fp32 exp2() with low precision, suitable for half_exp2() in CL or
212 * exp2() in GL. In the first argument, it takes f2i_rte(x * 2^24). In
213 * the second, it takes x itself. */
224 struct list_head link
; /* Must be first */
227 /* Indices, see bir_ssa_index etc. Note zero is special cased
228 * to "no argument" */
230 unsigned src
[BIR_SRC_COUNT
];
232 /* If one of the sources has BIR_INDEX_CONSTANT */
240 /* Floating-point modifiers, type/class permitting. If not
241 * allowed for the type/class, these are ignored. */
242 enum bifrost_outmod outmod
;
243 bool src_abs
[BIR_SRC_COUNT
];
244 bool src_neg
[BIR_SRC_COUNT
];
246 /* Round mode (requires BI_ROUNDMODE) */
247 enum bifrost_roundmode roundmode
;
249 /* Writemask (bit for each affected byte). This is quite restricted --
250 * ALU ops can only write to a single channel (exception: <32 in which
251 * you can write to 32/N contiguous aligned channels). Load/store can
252 * only write to all channels at once, in a sense. But it's still
253 * better to use this generic form than have synthetic ops flying
254 * about, since we're not essentially vector for RA purposes. */
257 /* Destination type. Usually the type of the instruction
258 * itself, but if sources and destination have different
259 * types, the type of the destination wins (so f2i would be
260 * int). Zero if there is no destination. Bitsize included */
261 nir_alu_type dest_type
;
263 /* Source types if required by the class */
264 nir_alu_type src_types
[BIR_SRC_COUNT
];
266 /* If the source type is 8-bit or 16-bit such that SIMD is possible,
267 * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
268 * sense. On non-SIMD instructions, it can be used for component
269 * selection, so we don't have to special case extraction. */
270 uint8_t swizzle
[BIR_SRC_COUNT
][NIR_MAX_VEC_COMPONENTS
];
272 /* A class-specific op from which the actual opcode can be derived
273 * (along with the above information) */
276 enum bi_minmax_op minmax
;
277 enum bi_bitwise_op bitwise
;
278 enum bi_round_op round
;
279 enum bi_special_op special
;
280 enum bi_reduce_op reduce
;
281 enum bi_table_op table
;
282 enum bi_frexp_op frexp
;
283 enum bi_cond compare
;
284 enum bi_tex_op texture
;
286 /* For FMA/ADD, should we add a biased exponent? */
290 /* Union for class-specific information */
292 enum bifrost_minmax_mode minmax
;
293 struct bi_load_vary load_vary
;
294 struct bi_branch branch
;
296 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
297 * sense here but you can always just use a move for that */
298 enum bi_cond csel_cond
;
300 /* For BLEND -- the location 0-7 */
301 unsigned blend_location
;
303 /* For STORE, STORE_VAR -- channel count */
304 unsigned store_channels
;
308 /* Scheduling takes place in two steps. Step 1 groups instructions within a
309 * block into distinct clauses (bi_clause). Step 2 schedules instructions
310 * within a clause into FMA/ADD pairs (bi_bundle).
312 * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
313 * leave it NULL; the emitter will fill in a nop.
322 struct list_head link
;
324 /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
325 * can be 8 bundles. But each bundle can have both an FMA and an ADD,
326 * so a clause can have up to 16 bi_instructions. Whether bundles or
327 * instructions are used depends on where in scheduling we are. */
329 unsigned instruction_count
;
330 unsigned bundle_count
;
333 bi_instruction
*instructions
[16];
334 bi_bundle bundles
[8];
337 /* For scoreboarding -- the clause ID (this is not globally unique!)
338 * and its dependencies in terms of other clauses, computed during
339 * scheduling and used when emitting code. Dependencies expressed as a
340 * bitfield matching the hardware, except shifted by a clause (the
341 * shift back to the ISA's off-by-one encoding is worked out when
342 * emitting clauses) */
343 unsigned scoreboard_id
;
344 uint8_t dependencies
;
346 /* Back-to-back corresponds directly to the back-to-back bit. Branch
347 * conditional corresponds to the branch conditional bit except that in
348 * the emitted code it's always set if back-to-bit is, whereas we use
349 * the actual value (without back-to-back so to speak) internally */
351 bool branch_conditional
;
353 /* Assigned data register */
354 unsigned data_register
;
356 /* Corresponds to the usual bit but shifted by a clause */
357 bool data_register_write_barrier
;
359 /* Constants read by this clause. ISA limit. */
360 uint64_t constants
[8];
361 unsigned constant_count
;
363 /* What type of high latency instruction is here, basically */
364 unsigned clause_type
;
367 typedef struct bi_block
{
368 pan_block base
; /* must be first */
370 /* If true, uses clauses; if false, uses instructions */
372 struct list_head clauses
; /* list of bi_clause */
377 gl_shader_stage stage
;
378 struct list_head blocks
; /* list of bi_block */
379 struct panfrost_sysvals sysvals
;
382 /* During NIR->BIR */
383 nir_function_impl
*impl
;
384 bi_block
*current_block
;
385 unsigned block_name_count
;
386 bi_block
*after_block
;
387 bi_block
*break_block
;
388 bi_block
*continue_block
;
391 /* For creating temporaries */
394 /* Analysis results */
397 /* Stats for shader-db */
398 unsigned instruction_count
;
402 static inline bi_instruction
*
403 bi_emit(bi_context
*ctx
, bi_instruction ins
)
405 bi_instruction
*u
= rzalloc(ctx
, bi_instruction
);
406 memcpy(u
, &ins
, sizeof(ins
));
407 list_addtail(&u
->link
, &ctx
->current_block
->base
.instructions
);
411 static inline bi_instruction
*
412 bi_emit_before(bi_context
*ctx
, bi_instruction
*tag
, bi_instruction ins
)
414 bi_instruction
*u
= rzalloc(ctx
, bi_instruction
);
415 memcpy(u
, &ins
, sizeof(ins
));
416 list_addtail(&u
->link
, &tag
->link
);
421 bi_remove_instruction(bi_instruction
*ins
)
423 list_del(&ins
->link
);
426 /* So we can distinguish between SSA/reg/sentinel quickly */
427 #define BIR_NO_ARG (0)
428 #define BIR_IS_REG (1)
430 /* If high bits are set, instead of SSA/registers, we have specials indexed by
431 * the low bits if necessary.
433 * Fixed register: do not allocate register, do not collect $200.
434 * Uniform: access a uniform register given by low bits.
435 * Constant: access the specified constant (specifies a bit offset / shift)
436 * Zero: special cased to avoid wasting a constant
437 * Passthrough: a bifrost_packed_src to passthrough T/T0/T1
440 #define BIR_INDEX_REGISTER (1 << 31)
441 #define BIR_INDEX_UNIFORM (1 << 30)
442 #define BIR_INDEX_CONSTANT (1 << 29)
443 #define BIR_INDEX_ZERO (1 << 28)
444 #define BIR_INDEX_PASS (1 << 27)
446 /* Keep me synced please so we can check src & BIR_SPECIAL */
448 #define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
449 (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
451 static inline unsigned
452 bi_max_temp(bi_context
*ctx
)
454 unsigned alloc
= MAX2(ctx
->impl
->reg_alloc
, ctx
->impl
->ssa_alloc
);
455 return ((alloc
+ 2 + ctx
->temp_alloc
) << 1);
458 static inline unsigned
459 bi_make_temp(bi_context
*ctx
)
461 return (ctx
->impl
->ssa_alloc
+ 1 + ctx
->temp_alloc
++) << 1;
464 static inline unsigned
465 bi_make_temp_reg(bi_context
*ctx
)
467 return ((ctx
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | BIR_IS_REG
;
470 static inline unsigned
471 bir_ssa_index(nir_ssa_def
*ssa
)
473 /* Off-by-one ensures BIR_NO_ARG is skipped */
474 return ((ssa
->index
+ 1) << 1) | 0;
477 static inline unsigned
478 bir_src_index(nir_src
*src
)
481 return bir_ssa_index(src
->ssa
);
483 assert(!src
->reg
.indirect
);
484 return (src
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
488 static inline unsigned
489 bir_dest_index(nir_dest
*dst
)
492 return bir_ssa_index(&dst
->ssa
);
494 assert(!dst
->reg
.indirect
);
495 return (dst
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
499 /* Iterators for Bifrost IR */
501 #define bi_foreach_block(ctx, v) \
502 list_for_each_entry(pan_block, v, &ctx->blocks, link)
504 #define bi_foreach_block_from(ctx, from, v) \
505 list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
507 #define bi_foreach_instr_in_block(block, v) \
508 list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
510 #define bi_foreach_instr_in_block_rev(block, v) \
511 list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
513 #define bi_foreach_instr_in_block_safe(block, v) \
514 list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
516 #define bi_foreach_instr_in_block_safe_rev(block, v) \
517 list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
519 #define bi_foreach_instr_in_block_from(block, v, from) \
520 list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
522 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
523 list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
525 #define bi_foreach_clause_in_block(block, v) \
526 list_for_each_entry(bi_clause, v, &(block)->clauses, link)
528 #define bi_foreach_instr_global(ctx, v) \
529 bi_foreach_block(ctx, v_block) \
530 bi_foreach_instr_in_block((bi_block *) v_block, v)
532 #define bi_foreach_instr_global_safe(ctx, v) \
533 bi_foreach_block(ctx, v_block) \
534 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
536 /* Based on set_foreach, expanded with automatic type casts */
538 #define bi_foreach_predecessor(blk, v) \
539 struct set_entry *_entry_##v; \
541 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
542 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \
543 _entry_##v != NULL; \
544 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
545 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
547 #define bi_foreach_src(ins, v) \
548 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
550 static inline bi_instruction
*
551 bi_prev_op(bi_instruction
*ins
)
553 return list_last_entry(&(ins
->link
), bi_instruction
, link
);
556 static inline bi_instruction
*
557 bi_next_op(bi_instruction
*ins
)
559 return list_first_entry(&(ins
->link
), bi_instruction
, link
);
562 static inline pan_block
*
563 pan_next_block(pan_block
*block
)
565 return list_first_entry(&(block
->link
), pan_block
, link
);
568 /* Special functions */
570 void bi_emit_fexp2(bi_context
*ctx
, nir_alu_instr
*instr
);
571 void bi_emit_flog2(bi_context
*ctx
, nir_alu_instr
*instr
);
573 /* BIR manipulation */
575 bool bi_has_outmod(bi_instruction
*ins
);
576 bool bi_has_source_mods(bi_instruction
*ins
);
577 bool bi_is_src_swizzled(bi_instruction
*ins
, unsigned s
);
578 bool bi_has_arg(bi_instruction
*ins
, unsigned arg
);
579 uint16_t bi_from_bytemask(uint16_t bytemask
, unsigned bytes
);
580 unsigned bi_get_component_count(bi_instruction
*ins
, unsigned s
);
581 unsigned bi_load32_components(bi_instruction
*ins
);
582 uint16_t bi_bytemask_of_read_components(bi_instruction
*ins
, unsigned node
);
583 uint64_t bi_get_immediate(bi_instruction
*ins
, unsigned index
);
584 bool bi_writes_component(bi_instruction
*ins
, unsigned comp
);
588 void bi_lower_combine(bi_context
*ctx
, bi_block
*block
);
589 bool bi_opt_dead_code_eliminate(bi_context
*ctx
, bi_block
*block
);
590 void bi_schedule(bi_context
*ctx
);
591 void bi_register_allocate(bi_context
*ctx
);
595 void bi_compute_liveness(bi_context
*ctx
);
596 void bi_liveness_ins_update(uint16_t *live
, bi_instruction
*ins
, unsigned max
);
597 void bi_invalidate_liveness(bi_context
*ctx
);
598 bool bi_is_live_after(bi_context
*ctx
, bi_block
*block
, bi_instruction
*start
, int src
);
602 void bi_pack(bi_context
*ctx
, struct util_dynarray
*emission
);