src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 #include "bifrost.h"
  31 #include "compiler/nir/nir.h"
  32
  33 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  34  * ADD with two completely different opcodes, and opcodes can be varying
  35  * length in some cases. Then we have different opcodes for int vs float
  36  * and then sometimes even for different typesizes. Further, virtually
  37  * every op has a number of flags which depend on the op. In constrast
  38  * to Midgard where you have a strict ALU/LDST/TEX division and within
  39  * ALU you have strict int/float and that's it... here it's a *lot* more
  40  * involved. As such, we use something much higher level for our IR,
  41  * encoding "classes" of operations, letting the opcode details get
  42  * sorted out at emit time.
  43  *
  44  * Please keep this list alphabetized. Please use a dictionary if you
  45  * don't know how to do that.
  46  */
  47
  48 enum bi_class {
  49         BI_ADD,
  50         BI_ATEST,
  51         BI_BRANCH,
  52         BI_CMP,
  53         BI_BLEND,
  54         BI_BITWISE,
  55         BI_CONVERT,
  56         BI_CSEL,
  57         BI_DISCARD,
  58         BI_FMA,
  59         BI_FREXP,
  60         BI_LOAD,
  61         BI_LOAD_ATTR,
  62         BI_LOAD_VAR,
  63         BI_LOAD_VAR_ADDRESS,
  64         BI_MINMAX,
  65         BI_MOV,
  66         BI_SHIFT,
  67         BI_STORE,
  68         BI_STORE_VAR,
  69         BI_SPECIAL, /* _FAST, _TABLE on supported GPUs */
  70         BI_SWIZZLE,
  71         BI_TEX,
  72         BI_ROUND,
  73         BI_NUM_CLASSES
  74 };
  75
  76 /* Properties of a class... */
  77 extern unsigned bi_class_props[BI_NUM_CLASSES];
  78
  79 /* abs/neg/outmod valid for a float op */
  80 #define BI_MODS (1 << 0)
  81
  82 /* Generic enough that little class-specific information is required. In other
  83  * words, it acts as a "normal" ALU op, even if the encoding ends up being
  84  * irregular enough to warrant a separate class */
  85 #define BI_GENERIC (1 << 1)
  86
  87 /* Accepts a bifrost_roundmode */
  88 #define BI_ROUNDMODE (1 << 2)
  89
  90 /* Can be scheduled to FMA */
  91 #define BI_SCHED_FMA (1 << 3)
  92
  93 /* Can be scheduled to ADD */
  94 #define BI_SCHED_ADD (1 << 4)
  95
  96 /* Most ALU ops can do either, actually */
  97 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
  98
  99 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
 100  * nopped out. Used for _FAST operations. */
 101 #define BI_SCHED_SLOW (1 << 5)
 102
 103 /* Swizzling allowed for the 8/16-bit source */
 104 #define BI_SWIZZLABLE (1 << 6)
 105
 106 /* It can't get any worse than csel4... can it? */
 107 #define BIR_SRC_COUNT 4
 108
 109 /* Class-specific data for BI_LD_ATTR, BI_LD_VAR_ADDR */
 110 struct bi_load {
 111         /* Note: no indirects here */
 112         unsigned location;
 113
 114         /* Only for BI_LD_ATTR. But number of vector channels */
 115         unsigned channels;
 116 };
 117
 118 /* BI_LD_VARY */
 119 struct bi_load_vary {
 120         /* All parameters used here. Indirect location specified in
 121          * src1 and ignoring location, if present. */
 122         struct bi_load load;
 123
 124         enum bifrost_interp_mode interp_mode;
 125         bool reuse;
 126         bool flat;
 127 };
 128
 129 /* Opcodes within a class */
 130 enum bi_minmax_op {
 131         BI_MINMAX_MIN,
 132         BI_MINMAX_MAX
 133 };
 134
 135 enum bi_bitwise_op {
 136         BI_BITWISE_AND,
 137         BI_BITWISE_OR,
 138         BI_BITWISE_XOR
 139 };
 140
 141 enum bi_round_op {
 142         BI_ROUND_MODE, /* use round mode */
 143         BI_ROUND_ROUND /* i.e.: fround() */
 144 };
 145
 146 typedef struct {
 147         struct list_head link; /* Must be first */
 148         enum bi_class type;
 149
 150         /* Indices, see bir_ssa_index etc. Note zero is special cased
 151          * to "no argument" */
 152         unsigned dest;
 153         unsigned src[BIR_SRC_COUNT];
 154
 155         /* If one of the sources has BIR_INDEX_CONSTANT... */
 156         union {
 157                 uint64_t u64;
 158                 uint32_t u32;
 159                 uint16_t u16[2];
 160                 uint8_t u8[4];
 161         } constant;
 162
 163         /* Floating-point modifiers, type/class permitting. If not
 164          * allowed for the type/class, these are ignored. */
 165         enum bifrost_outmod outmod;
 166         bool src_abs[BIR_SRC_COUNT];
 167         bool src_neg[BIR_SRC_COUNT];
 168
 169         /* Round mode (requires BI_ROUNDMODE) */
 170         enum bifrost_roundmode roundmode;
 171
 172         /* Destination type. Usually the type of the instruction
 173          * itself, but if sources and destination have different
 174          * types, the type of the destination wins (so f2i would be
 175          * int). Zero if there is no destination. Bitsize included */
 176         nir_alu_type dest_type;
 177
 178         /* If the source type is 8-bit or 16-bit such that SIMD is possible, and
 179          * the class has BI_SWIZZLABLE, this is a swizzle for the input. Swizzles
 180          * in practice only occur with one-source arguments (conversions,
 181          * dedicated swizzle ops) and as component selection on two-sources
 182          * where it is unambiguous which is which. Bounds are 32/type_size. */
 183         unsigned swizzle[4];
 184
 185         /* A class-specific op from which the actual opcode can be derived
 186          * (along with the above information) */
 187
 188         union {
 189                 enum bi_minmax_op minmax;
 190                 enum bi_bitwise_op bitwise;
 191                 enum bi_round_op round;
 192         } op;
 193
 194         /* Union for class-specific information */
 195         union {
 196                 enum bifrost_minmax_mode minmax;
 197                 struct bi_load load;
 198                 struct bi_load_vary load_vary;
 199         };
 200 } bi_instruction;
 201
 202 /* Scheduling takes place in two steps. Step 1 groups instructions within a
 203  * block into distinct clauses (bi_clause). Step 2 schedules instructions
 204  * within a clause into FMA/ADD pairs (bi_bundle).
 205  *
 206  * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
 207  * leave it NULL; the emitter will fill in a nop.
 208  */
 209
 210 typedef struct {
 211         bi_instruction *fma;
 212         bi_instruction *add;
 213 } bi_bundle;
 214
 215 typedef struct {
 216         struct list_head link;
 217
 218         /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
 219          * can be 8 bundles. But each bundle can have both an FMA and an ADD,
 220          * so a clause can have up to 16 bi_instructions. Whether bundles or
 221          * instructions are used depends on where in scheduling we are. */
 222
 223         unsigned instruction_count;
 224         unsigned bundle_count;
 225
 226         union {
 227                 bi_instruction *instructions[16];
 228                 bi_bundle bundles[8];
 229         };
 230
 231         /* For scoreboarding -- the clause ID (this is not globally unique!)
 232          * and its dependencies in terms of other clauses, computed during
 233          * scheduling and used when emitting code. Dependencies expressed as a
 234          * bitfield matching the hardware, except shifted by a clause (the
 235          * shift back to the ISA's off-by-one encoding is worked out when
 236          * emitting clauses) */
 237         unsigned scoreboard_id;
 238         uint8_t dependencies;
 239
 240         /* Back-to-back corresponds directly to the back-to-back bit. Branch
 241          * conditional corresponds to the branch conditional bit except that in
 242          * the emitted code it's always set if back-to-bit is, whereas we use
 243          * the actual value (without back-to-back so to speak) internally */
 244         bool back_to_back;
 245         bool branch_conditional;
 246
 247         /* Corresponds to the usual bit but shifted by a clause */
 248         bool data_register_write_barrier;
 249 } bi_clause;
 250
 251 typedef struct bi_block {
 252         struct list_head link; /* must be first */
 253         unsigned name; /* Just for pretty-printing */
 254
 255         /* If true, uses clauses; if false, uses instructions */
 256         bool scheduled;
 257
 258         union {
 259                 struct list_head instructions; /* pre-schedule, list of bi_instructions */
 260                 struct list_head clauses; /* list of bi_clause */
 261         };
 262 } bi_block;
 263
 264 typedef struct {
 265        nir_shader *nir;
 266        struct list_head blocks; /* list of bi_block */
 267 } bi_context;
 268
 269 /* So we can distinguish between SSA/reg/sentinel quickly */
 270 #define BIR_NO_ARG (0)
 271 #define BIR_IS_REG (1)
 272
 273 /* If high bits are set, instead of SSA/registers, we have specials indexed by
 274  * the low bits if necessary.
 275  *
 276  *  Fixed register: do not allocate register, do not collect $200.
 277  *  Uniform: access a uniform register given by low bits.
 278  *  Constant: access the specified constant
 279  *  Zero: special cased to avoid wasting a constant
 280  */
 281
 282 #define BIR_INDEX_REGISTER (1 << 31)
 283 #define BIR_INDEX_UNIFORM  (1 << 30)
 284 #define BIR_INDEX_CONSTANT (1 << 29)
 285 #define BIR_INDEX_ZERO     (1 << 28)
 286
 287 /* Keep me synced please so we can check src & BIR_SPECIAL */
 288
 289 #define BIR_SPECIAL        ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
 290         (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO)
 291
 292 static inline unsigned
 293 bir_ssa_index(nir_ssa_def *ssa)
 294 {
 295         /* Off-by-one ensures BIR_NO_ARG is skipped */
 296         return ((ssa->index + 1) << 1) | 0;
 297 }
 298
 299 static inline unsigned
 300 bir_src_index(nir_src *src)
 301 {
 302         if (src->is_ssa)
 303                 return bir_ssa_index(src->ssa);
 304         else {
 305                 assert(!src->reg.indirect);
 306                 return (src->reg.reg->index << 1) | BIR_IS_REG;
 307         }
 308 }
 309
 310 static inline unsigned
 311 bir_dest_index(nir_dest *dst)
 312 {
 313         if (dst->is_ssa)
 314                 return bir_ssa_index(&dst->ssa);
 315         else {
 316                 assert(!dst->reg.indirect);
 317                 return (dst->reg.reg->index << 1) | BIR_IS_REG;
 318         }
 319 }
 320
 321 #endif