2 * Copyright (C) 2020 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
27 #ifndef __BIFROST_COMPILER_H
28 #define __BIFROST_COMPILER_H
31 #include "compiler/nir/nir.h"
32 #include "panfrost/util/pan_ir.h"
34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
35 * ADD with two completely different opcodes, and opcodes can be varying
36 * length in some cases. Then we have different opcodes for int vs float
37 * and then sometimes even for different typesizes. Further, virtually
38 * every op has a number of flags which depend on the op. In constrast
39 * to Midgard where you have a strict ALU/LDST/TEX division and within
40 * ALU you have strict int/float and that's it... here it's a *lot* more
41 * involved. As such, we use something much higher level for our IR,
42 * encoding "classes" of operations, letting the opcode details get
43 * sorted out at emit time.
45 * Please keep this list alphabetized. Please use a dictionary if you
46 * don't know how to do that.
74 BI_SPECIAL
, /* _FAST, _TABLE on supported GPUs */
81 /* Properties of a class... */
82 extern unsigned bi_class_props
[BI_NUM_CLASSES
];
84 /* abs/neg/outmod valid for a float op */
85 #define BI_MODS (1 << 0)
87 /* Generic enough that little class-specific information is required. In other
88 * words, it acts as a "normal" ALU op, even if the encoding ends up being
89 * irregular enough to warrant a separate class */
90 #define BI_GENERIC (1 << 1)
92 /* Accepts a bifrost_roundmode */
93 #define BI_ROUNDMODE (1 << 2)
95 /* Can be scheduled to FMA */
96 #define BI_SCHED_FMA (1 << 3)
98 /* Can be scheduled to ADD */
99 #define BI_SCHED_ADD (1 << 4)
101 /* Most ALU ops can do either, actually */
102 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
104 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
105 * nopped out. Used for _FAST operations. */
106 #define BI_SCHED_SLOW (1 << 5)
108 /* Swizzling allowed for the 8/16-bit source */
109 #define BI_SWIZZLABLE (1 << 6)
111 /* For scheduling purposes this is a high latency instruction and must be at
112 * the end of a clause. Implies ADD */
113 #define BI_SCHED_HI_LATENCY (1 << 7)
115 /* Intrinsic is vectorized and should read 4 components in the first source
116 * regardless of writemask */
117 #define BI_VECTOR (1 << 8)
119 /* Use a data register for src0/dest respectively, bypassing the usual
120 * register accessor. Mutually exclusive. */
121 #define BI_DATA_REG_SRC (1 << 9)
122 #define BI_DATA_REG_DEST (1 << 10)
124 /* It can't get any worse than csel4... can it? */
125 #define BIR_SRC_COUNT 4
128 struct bi_load_vary
{
129 enum bifrost_interp_mode interp_mode
;
134 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
135 * the target. We forward declare bi_block since this is mildly circular (not
136 * strictly, but this order of the file makes more sense I think)
138 * We define our own enum of conditions since the conditions in the hardware
139 * packed in crazy ways that would make manipulation unweildly (meaning changes
140 * based on port swapping, etc), so we defer dealing with that until emit time.
141 * Likewise, we expose NIR types instead of the crazy branch types, although
142 * the restrictions do eventually apply of course. */
157 /* Types are specified in src_types and must be compatible (either both
158 * int, or both float, 16/32, and same size or 32/16 if float. Types
159 * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
162 struct bi_block
*target
;
165 /* Opcodes within a class */
178 BI_ROUND_MODE
, /* use round mode */
179 BI_ROUND_ROUND
/* i.e.: fround() */
194 struct list_head link
; /* Must be first */
197 /* Indices, see bir_ssa_index etc. Note zero is special cased
198 * to "no argument" */
200 unsigned src
[BIR_SRC_COUNT
];
202 /* If one of the sources has BIR_INDEX_CONSTANT */
210 /* Floating-point modifiers, type/class permitting. If not
211 * allowed for the type/class, these are ignored. */
212 enum bifrost_outmod outmod
;
213 bool src_abs
[BIR_SRC_COUNT
];
214 bool src_neg
[BIR_SRC_COUNT
];
216 /* Round mode (requires BI_ROUNDMODE) */
217 enum bifrost_roundmode roundmode
;
219 /* Writemask (bit for each affected byte). This is quite restricted --
220 * ALU ops can only write to a single channel (exception: <32 in which
221 * you can write to 32/N contiguous aligned channels). Load/store can
222 * only write to all channels at once, in a sense. But it's still
223 * better to use this generic form than have synthetic ops flying
224 * about, since we're not essentially vector for RA purposes. */
227 /* Destination type. Usually the type of the instruction
228 * itself, but if sources and destination have different
229 * types, the type of the destination wins (so f2i would be
230 * int). Zero if there is no destination. Bitsize included */
231 nir_alu_type dest_type
;
233 /* Source types if required by the class */
234 nir_alu_type src_types
[BIR_SRC_COUNT
];
236 /* If the source type is 8-bit or 16-bit such that SIMD is possible,
237 * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
238 * sense. On non-SIMD instructions, it can be used for component
239 * selection, so we don't have to special case extraction. */
240 uint8_t swizzle
[BIR_SRC_COUNT
][NIR_MAX_VEC_COMPONENTS
];
242 /* A class-specific op from which the actual opcode can be derived
243 * (along with the above information) */
246 enum bi_minmax_op minmax
;
247 enum bi_bitwise_op bitwise
;
248 enum bi_round_op round
;
249 enum bi_special_op special
;
250 enum bi_cond compare
;
253 /* Union for class-specific information */
255 enum bifrost_minmax_mode minmax
;
256 struct bi_load_vary load_vary
;
257 struct bi_branch branch
;
259 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
260 * sense here but you can always just use a move for that */
261 enum bi_cond csel_cond
;
263 /* For BLEND -- the location 0-7 */
264 unsigned blend_location
;
266 /* For STORE, STORE_VAR -- channel count */
267 unsigned store_channels
;
271 /* Scheduling takes place in two steps. Step 1 groups instructions within a
272 * block into distinct clauses (bi_clause). Step 2 schedules instructions
273 * within a clause into FMA/ADD pairs (bi_bundle).
275 * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
276 * leave it NULL; the emitter will fill in a nop.
285 struct list_head link
;
287 /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
288 * can be 8 bundles. But each bundle can have both an FMA and an ADD,
289 * so a clause can have up to 16 bi_instructions. Whether bundles or
290 * instructions are used depends on where in scheduling we are. */
292 unsigned instruction_count
;
293 unsigned bundle_count
;
296 bi_instruction
*instructions
[16];
297 bi_bundle bundles
[8];
300 /* For scoreboarding -- the clause ID (this is not globally unique!)
301 * and its dependencies in terms of other clauses, computed during
302 * scheduling and used when emitting code. Dependencies expressed as a
303 * bitfield matching the hardware, except shifted by a clause (the
304 * shift back to the ISA's off-by-one encoding is worked out when
305 * emitting clauses) */
306 unsigned scoreboard_id
;
307 uint8_t dependencies
;
309 /* Back-to-back corresponds directly to the back-to-back bit. Branch
310 * conditional corresponds to the branch conditional bit except that in
311 * the emitted code it's always set if back-to-bit is, whereas we use
312 * the actual value (without back-to-back so to speak) internally */
314 bool branch_conditional
;
316 /* Assigned data register */
317 unsigned data_register
;
319 /* Corresponds to the usual bit but shifted by a clause */
320 bool data_register_write_barrier
;
322 /* Constants read by this clause. ISA limit. */
323 uint64_t constants
[8];
324 unsigned constant_count
;
326 /* What type of high latency instruction is here, basically */
327 unsigned clause_type
;
330 typedef struct bi_block
{
331 pan_block base
; /* must be first */
333 /* If true, uses clauses; if false, uses instructions */
335 struct list_head clauses
; /* list of bi_clause */
340 gl_shader_stage stage
;
341 struct list_head blocks
; /* list of bi_block */
342 struct panfrost_sysvals sysvals
;
345 /* During NIR->BIR */
346 nir_function_impl
*impl
;
347 bi_block
*current_block
;
348 unsigned block_name_count
;
349 bi_block
*after_block
;
350 bi_block
*break_block
;
351 bi_block
*continue_block
;
354 /* For creating temporaries */
357 /* Analysis results */
360 /* Stats for shader-db */
361 unsigned instruction_count
;
365 static inline bi_instruction
*
366 bi_emit(bi_context
*ctx
, bi_instruction ins
)
368 bi_instruction
*u
= rzalloc(ctx
, bi_instruction
);
369 memcpy(u
, &ins
, sizeof(ins
));
370 list_addtail(&u
->link
, &ctx
->current_block
->base
.instructions
);
374 static inline bi_instruction
*
375 bi_emit_before(bi_context
*ctx
, bi_instruction
*tag
, bi_instruction ins
)
377 bi_instruction
*u
= rzalloc(ctx
, bi_instruction
);
378 memcpy(u
, &ins
, sizeof(ins
));
379 list_addtail(&u
->link
, &tag
->link
);
384 bi_remove_instruction(bi_instruction
*ins
)
386 list_del(&ins
->link
);
389 /* So we can distinguish between SSA/reg/sentinel quickly */
390 #define BIR_NO_ARG (0)
391 #define BIR_IS_REG (1)
393 /* If high bits are set, instead of SSA/registers, we have specials indexed by
394 * the low bits if necessary.
396 * Fixed register: do not allocate register, do not collect $200.
397 * Uniform: access a uniform register given by low bits.
398 * Constant: access the specified constant (specifies a bit offset / shift)
399 * Zero: special cased to avoid wasting a constant
400 * Passthrough: a bifrost_packed_src to passthrough T/T0/T1
403 #define BIR_INDEX_REGISTER (1 << 31)
404 #define BIR_INDEX_UNIFORM (1 << 30)
405 #define BIR_INDEX_CONSTANT (1 << 29)
406 #define BIR_INDEX_ZERO (1 << 28)
407 #define BIR_INDEX_PASS (1 << 27)
409 /* Keep me synced please so we can check src & BIR_SPECIAL */
411 #define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
412 (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
414 static inline unsigned
415 bi_max_temp(bi_context
*ctx
)
417 unsigned alloc
= MAX2(ctx
->impl
->reg_alloc
, ctx
->impl
->ssa_alloc
);
418 return ((alloc
+ 2 + ctx
->temp_alloc
) << 1);
421 static inline unsigned
422 bi_make_temp(bi_context
*ctx
)
424 return (ctx
->impl
->ssa_alloc
+ 1 + ctx
->temp_alloc
++) << 1;
427 static inline unsigned
428 bi_make_temp_reg(bi_context
*ctx
)
430 return ((ctx
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | BIR_IS_REG
;
433 static inline unsigned
434 bir_ssa_index(nir_ssa_def
*ssa
)
436 /* Off-by-one ensures BIR_NO_ARG is skipped */
437 return ((ssa
->index
+ 1) << 1) | 0;
440 static inline unsigned
441 bir_src_index(nir_src
*src
)
444 return bir_ssa_index(src
->ssa
);
446 assert(!src
->reg
.indirect
);
447 return (src
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
451 static inline unsigned
452 bir_dest_index(nir_dest
*dst
)
455 return bir_ssa_index(&dst
->ssa
);
457 assert(!dst
->reg
.indirect
);
458 return (dst
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
462 /* Iterators for Bifrost IR */
464 #define bi_foreach_block(ctx, v) \
465 list_for_each_entry(pan_block, v, &ctx->blocks, link)
467 #define bi_foreach_block_from(ctx, from, v) \
468 list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
470 #define bi_foreach_instr_in_block(block, v) \
471 list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
473 #define bi_foreach_instr_in_block_rev(block, v) \
474 list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
476 #define bi_foreach_instr_in_block_safe(block, v) \
477 list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
479 #define bi_foreach_instr_in_block_safe_rev(block, v) \
480 list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
482 #define bi_foreach_instr_in_block_from(block, v, from) \
483 list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
485 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
486 list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
488 #define bi_foreach_clause_in_block(block, v) \
489 list_for_each_entry(bi_clause, v, &(block)->clauses, link)
491 #define bi_foreach_instr_global(ctx, v) \
492 bi_foreach_block(ctx, v_block) \
493 bi_foreach_instr_in_block((bi_block *) v_block, v)
495 #define bi_foreach_instr_global_safe(ctx, v) \
496 bi_foreach_block(ctx, v_block) \
497 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
499 /* Based on set_foreach, expanded with automatic type casts */
501 #define bi_foreach_predecessor(blk, v) \
502 struct set_entry *_entry_##v; \
504 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
505 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \
506 _entry_##v != NULL; \
507 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
508 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
510 #define bi_foreach_src(ins, v) \
511 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
513 static inline bi_instruction
*
514 bi_prev_op(bi_instruction
*ins
)
516 return list_last_entry(&(ins
->link
), bi_instruction
, link
);
519 static inline bi_instruction
*
520 bi_next_op(bi_instruction
*ins
)
522 return list_first_entry(&(ins
->link
), bi_instruction
, link
);
525 static inline pan_block
*
526 pan_next_block(pan_block
*block
)
528 return list_first_entry(&(block
->link
), pan_block
, link
);
531 /* BIR manipulation */
533 bool bi_has_outmod(bi_instruction
*ins
);
534 bool bi_has_source_mods(bi_instruction
*ins
);
535 bool bi_is_src_swizzled(bi_instruction
*ins
, unsigned s
);
536 bool bi_has_arg(bi_instruction
*ins
, unsigned arg
);
537 uint16_t bi_from_bytemask(uint16_t bytemask
, unsigned bytes
);
538 unsigned bi_get_component_count(bi_instruction
*ins
, unsigned s
);
539 unsigned bi_load32_components(bi_instruction
*ins
);
540 uint16_t bi_bytemask_of_read_components(bi_instruction
*ins
, unsigned node
);
541 uint64_t bi_get_immediate(bi_instruction
*ins
, unsigned index
);
542 bool bi_writes_component(bi_instruction
*ins
, unsigned comp
);
546 void bi_lower_combine(bi_context
*ctx
, bi_block
*block
);
547 bool bi_opt_dead_code_eliminate(bi_context
*ctx
, bi_block
*block
);
548 void bi_schedule(bi_context
*ctx
);
549 void bi_register_allocate(bi_context
*ctx
);
553 void bi_compute_liveness(bi_context
*ctx
);
554 void bi_liveness_ins_update(uint16_t *live
, bi_instruction
*ins
, unsigned max
);
555 void bi_invalidate_liveness(bi_context
*ctx
);
556 bool bi_is_live_after(bi_context
*ctx
, bi_block
*block
, bi_instruction
*start
, int src
);
560 void bi_pack(bi_context
*ctx
, struct util_dynarray
*emission
);