src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 #include "bifrost.h"
  31 #include "compiler/nir/nir.h"
  32 #include "panfrost/util/pan_ir.h"
  33
  34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  35  * ADD with two completely different opcodes, and opcodes can be varying
  36  * length in some cases. Then we have different opcodes for int vs float
  37  * and then sometimes even for different typesizes. Further, virtually
  38  * every op has a number of flags which depend on the op. In constrast
  39  * to Midgard where you have a strict ALU/LDST/TEX division and within
  40  * ALU you have strict int/float and that's it... here it's a *lot* more
  41  * involved. As such, we use something much higher level for our IR,
  42  * encoding "classes" of operations, letting the opcode details get
  43  * sorted out at emit time.
  44  *
  45  * Please keep this list alphabetized. Please use a dictionary if you
  46  * don't know how to do that.
  47  */
  48
  49 enum bi_class {
  50         BI_ADD,
  51         BI_ATEST,
  52         BI_BRANCH,
  53         BI_CMP,
  54         BI_BLEND,
  55         BI_BITWISE,
  56         BI_COMBINE,
  57         BI_CONVERT,
  58         BI_CSEL,
  59         BI_DISCARD,
  60         BI_FMA,
  61         BI_FMOV,
  62         BI_FREXP,
  63         BI_ISUB,
  64         BI_LOAD,
  65         BI_LOAD_UNIFORM,
  66         BI_LOAD_ATTR,
  67         BI_LOAD_VAR,
  68         BI_LOAD_VAR_ADDRESS,
  69         BI_MINMAX,
  70         BI_MOV,
  71         BI_REDUCE_FMA,
  72         BI_SELECT,
  73         BI_SHIFT,
  74         BI_STORE,
  75         BI_STORE_VAR,
  76         BI_SPECIAL, /* _FAST on supported GPUs */
  77         BI_TABLE,
  78         BI_TEX,
  79         BI_ROUND,
  80         BI_NUM_CLASSES
  81 };
  82
  83 /* Properties of a class... */
  84 extern unsigned bi_class_props[BI_NUM_CLASSES];
  85
  86 /* abs/neg/outmod valid for a float op */
  87 #define BI_MODS (1 << 0)
  88
  89 /* Generic enough that little class-specific information is required. In other
  90  * words, it acts as a "normal" ALU op, even if the encoding ends up being
  91  * irregular enough to warrant a separate class */
  92 #define BI_GENERIC (1 << 1)
  93
  94 /* Accepts a bifrost_roundmode */
  95 #define BI_ROUNDMODE (1 << 2)
  96
  97 /* Can be scheduled to FMA */
  98 #define BI_SCHED_FMA (1 << 3)
  99
 100 /* Can be scheduled to ADD */
 101 #define BI_SCHED_ADD (1 << 4)
 102
 103 /* Most ALU ops can do either, actually */
 104 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
 105
 106 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
 107  * nopped out. Used for _FAST operations. */
 108 #define BI_SCHED_SLOW (1 << 5)
 109
 110 /* Swizzling allowed for the 8/16-bit source */
 111 #define BI_SWIZZLABLE (1 << 6)
 112
 113 /* For scheduling purposes this is a high latency instruction and must be at
 114  * the end of a clause. Implies ADD */
 115 #define BI_SCHED_HI_LATENCY (1 << 7)
 116
 117 /* Intrinsic is vectorized and acts with `vector_channels` components */
 118 #define BI_VECTOR (1 << 8)
 119
 120 /* Use a data register for src0/dest respectively, bypassing the usual
 121  * register accessor. Mutually exclusive. */
 122 #define BI_DATA_REG_SRC (1 << 9)
 123 #define BI_DATA_REG_DEST (1 << 10)
 124
 125 /* Quirk: cannot encode multiple abs on FMA in fp16 mode */
 126 #define BI_NO_ABS_ABS_FP16_FMA (1 << 11)
 127
 128 /* It can't get any worse than csel4... can it? */
 129 #define BIR_SRC_COUNT 4
 130
 131 /* BI_LD_VARY */
 132 struct bi_load_vary {
 133         enum bifrost_interp_mode interp_mode;
 134         bool reuse;
 135         bool flat;
 136 };
 137
 138 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
 139  * the target. We forward declare bi_block since this is mildly circular (not
 140  * strictly, but this order of the file makes more sense I think)
 141  *
 142  * We define our own enum of conditions since the conditions in the hardware
 143  * packed in crazy ways that would make manipulation unweildly (meaning changes
 144  * based on port swapping, etc), so we defer dealing with that until emit time.
 145  * Likewise, we expose NIR types instead of the crazy branch types, although
 146  * the restrictions do eventually apply of course. */
 147
 148 struct bi_block;
 149
 150 enum bi_cond {
 151         BI_COND_ALWAYS,
 152         BI_COND_LT,
 153         BI_COND_LE,
 154         BI_COND_GE,
 155         BI_COND_GT,
 156         BI_COND_EQ,
 157         BI_COND_NE,
 158 };
 159
 160 struct bi_branch {
 161         /* Types are specified in src_types and must be compatible (either both
 162          * int, or both float, 16/32, and same size or 32/16 if float. Types
 163          * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
 164
 165         enum bi_cond cond;
 166         struct bi_block *target;
 167 };
 168
 169 /* Opcodes within a class */
 170 enum bi_minmax_op {
 171         BI_MINMAX_MIN,
 172         BI_MINMAX_MAX
 173 };
 174
 175 enum bi_bitwise_op {
 176         BI_BITWISE_AND,
 177         BI_BITWISE_OR,
 178         BI_BITWISE_XOR
 179 };
 180
 181 enum bi_table_op {
 182         /* fp32 log2() with low precision, suitable for GL or half_log2() in
 183          * CL. In the first argument, takes x. Letting u be such that x =
 184          * 2^{-m} u with m integer and 0.75 <= u < 1.5, returns
 185          * log2(u) / (u - 1). */
 186
 187         BI_TABLE_LOG2_U_OVER_U_1_LOW,
 188 };
 189
 190 enum bi_reduce_op {
 191         /* Takes two fp32 arguments and returns x + frexp(y). Used in
 192          * low-precision log2 argument reduction on newer models. */
 193
 194         BI_REDUCE_ADD_FREXPM,
 195 };
 196
 197 enum bi_frexp_op {
 198         BI_FREXPE_LOG,
 199 };
 200
 201 enum bi_special_op {
 202         BI_SPECIAL_FRCP,
 203         BI_SPECIAL_FRSQ,
 204
 205         /* fp32 exp2() with low precision, suitable for half_exp2() in CL or
 206          * exp2() in GL. In the first argument, it takes f2i_rte(x * 2^24). In
 207          * the second, it takes x itself. */
 208         BI_SPECIAL_EXP2_LOW,
 209 };
 210
 211 enum bi_tex_op {
 212         BI_TEX_NORMAL,
 213         BI_TEX_COMPACT,
 214         BI_TEX_DUAL
 215 };
 216
 217 struct bi_bitwise {
 218         bool src_invert[2];
 219         bool rshift; /* false for lshift */
 220 };
 221
 222 struct bi_texture {
 223         /* Constant indices. Indirect would need to be in src[..] like normal,
 224          * we can reserve some sentinels there for that for future. */
 225         unsigned texture_index, sampler_index;
 226 };
 227
 228 typedef struct {
 229         struct list_head link; /* Must be first */
 230         enum bi_class type;
 231
 232         /* Indices, see pan_ssa_index etc. Note zero is special cased
 233          * to "no argument" */
 234         unsigned dest;
 235         unsigned src[BIR_SRC_COUNT];
 236
 237         /* 32-bit word offset for destination, added to the register number in
 238          * RA when lowering combines */
 239         unsigned dest_offset;
 240
 241         /* If one of the sources has BIR_INDEX_CONSTANT */
 242         union {
 243                 uint64_t u64;
 244                 uint32_t u32;
 245                 uint16_t u16[2];
 246                 uint8_t u8[4];
 247         } constant;
 248
 249         /* Floating-point modifiers, type/class permitting. If not
 250          * allowed for the type/class, these are ignored. */
 251         enum bifrost_outmod outmod;
 252         bool src_abs[BIR_SRC_COUNT];
 253         bool src_neg[BIR_SRC_COUNT];
 254
 255         /* Round mode (requires BI_ROUNDMODE) */
 256         enum bifrost_roundmode roundmode;
 257
 258         /* Destination type. Usually the type of the instruction
 259          * itself, but if sources and destination have different
 260          * types, the type of the destination wins (so f2i would be
 261          * int). Zero if there is no destination. Bitsize included */
 262         nir_alu_type dest_type;
 263
 264         /* Source types if required by the class */
 265         nir_alu_type src_types[BIR_SRC_COUNT];
 266
 267         /* If the source type is 8-bit or 16-bit such that SIMD is possible,
 268          * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
 269          * sense. On non-SIMD instructions, it can be used for component
 270          * selection, so we don't have to special case extraction. */
 271         uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS];
 272
 273         /* For VECTOR ops, how many channels are written? */
 274         unsigned vector_channels;
 275
 276         /* A class-specific op from which the actual opcode can be derived
 277          * (along with the above information) */
 278
 279         union {
 280                 enum bi_minmax_op minmax;
 281                 enum bi_bitwise_op bitwise;
 282                 enum bi_special_op special;
 283                 enum bi_reduce_op reduce;
 284                 enum bi_table_op table;
 285                 enum bi_frexp_op frexp;
 286                 enum bi_tex_op texture;
 287
 288                 /* For FMA/ADD, should we add a biased exponent? */
 289                 bool mscale;
 290         } op;
 291
 292         /* Union for class-specific information */
 293         union {
 294                 enum bifrost_minmax_mode minmax;
 295                 struct bi_load_vary load_vary;
 296                 struct bi_branch branch;
 297
 298                 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
 299                  * sense here but you can always just use a move for that */
 300                 enum bi_cond cond;
 301
 302                 /* For BLEND -- the location 0-7 */
 303                 unsigned blend_location;
 304
 305                 struct bi_bitwise bitwise;
 306                 struct bi_texture texture;
 307         };
 308 } bi_instruction;
 309
 310 /* Scheduling takes place in two steps. Step 1 groups instructions within a
 311  * block into distinct clauses (bi_clause). Step 2 schedules instructions
 312  * within a clause into FMA/ADD pairs (bi_bundle).
 313  *
 314  * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
 315  * leave it NULL; the emitter will fill in a nop.
 316  */
 317
 318 typedef struct {
 319         bi_instruction *fma;
 320         bi_instruction *add;
 321 } bi_bundle;
 322
 323 typedef struct {
 324         struct list_head link;
 325
 326         /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
 327          * can be 8 bundles. But each bundle can have both an FMA and an ADD,
 328          * so a clause can have up to 16 bi_instructions. Whether bundles or
 329          * instructions are used depends on where in scheduling we are. */
 330
 331         unsigned instruction_count;
 332         unsigned bundle_count;
 333
 334         union {
 335                 bi_instruction *instructions[16];
 336                 bi_bundle bundles[8];
 337         };
 338
 339         /* For scoreboarding -- the clause ID (this is not globally unique!)
 340          * and its dependencies in terms of other clauses, computed during
 341          * scheduling and used when emitting code. Dependencies expressed as a
 342          * bitfield matching the hardware, except shifted by a clause (the
 343          * shift back to the ISA's off-by-one encoding is worked out when
 344          * emitting clauses) */
 345         unsigned scoreboard_id;
 346         uint8_t dependencies;
 347
 348         /* Back-to-back corresponds directly to the back-to-back bit. Branch
 349          * conditional corresponds to the branch conditional bit except that in
 350          * the emitted code it's always set if back-to-bit is, whereas we use
 351          * the actual value (without back-to-back so to speak) internally */
 352         bool back_to_back;
 353         bool branch_conditional;
 354
 355         /* Assigned data register */
 356         unsigned data_register;
 357
 358         /* Corresponds to the usual bit but shifted by a clause */
 359         bool data_register_write_barrier;
 360
 361         /* Constants read by this clause. ISA limit. */
 362         uint64_t constants[8];
 363         unsigned constant_count;
 364
 365         /* What type of high latency instruction is here, basically */
 366         unsigned clause_type;
 367 } bi_clause;
 368
 369 typedef struct bi_block {
 370         pan_block base; /* must be first */
 371
 372         /* If true, uses clauses; if false, uses instructions */
 373         bool scheduled;
 374         struct list_head clauses; /* list of bi_clause */
 375 } bi_block;
 376
 377 typedef struct {
 378        nir_shader *nir;
 379        gl_shader_stage stage;
 380        struct list_head blocks; /* list of bi_block */
 381        struct panfrost_sysvals sysvals;
 382        uint32_t quirks;
 383
 384        /* During NIR->BIR */
 385        nir_function_impl *impl;
 386        bi_block *current_block;
 387        unsigned block_name_count;
 388        bi_block *after_block;
 389        bi_block *break_block;
 390        bi_block *continue_block;
 391        bool emitted_atest;
 392        nir_alu_type *blend_types;
 393
 394        /* For creating temporaries */
 395        unsigned temp_alloc;
 396
 397        /* Analysis results */
 398        bool has_liveness;
 399
 400        /* Stats for shader-db */
 401        unsigned instruction_count;
 402        unsigned loop_count;
 403 } bi_context;
 404
 405 static inline bi_instruction *
 406 bi_emit(bi_context *ctx, bi_instruction ins)
 407 {
 408         bi_instruction *u = rzalloc(ctx, bi_instruction);
 409         memcpy(u, &ins, sizeof(ins));
 410         list_addtail(&u->link, &ctx->current_block->base.instructions);
 411         return u;
 412 }
 413
 414 static inline bi_instruction *
 415 bi_emit_before(bi_context *ctx, bi_instruction *tag, bi_instruction ins)
 416 {
 417         bi_instruction *u = rzalloc(ctx, bi_instruction);
 418         memcpy(u, &ins, sizeof(ins));
 419         list_addtail(&u->link, &tag->link);
 420         return u;
 421 }
 422
 423 static inline void
 424 bi_remove_instruction(bi_instruction *ins)
 425 {
 426         list_del(&ins->link);
 427 }
 428
 429 /* If high bits are set, instead of SSA/registers, we have specials indexed by
 430  * the low bits if necessary.
 431  *
 432  *  Fixed register: do not allocate register, do not collect $200.
 433  *  Uniform: access a uniform register given by low bits.
 434  *  Constant: access the specified constant (specifies a bit offset / shift)
 435  *  Zero: special cased to avoid wasting a constant
 436  *  Passthrough: a bifrost_packed_src to passthrough T/T0/T1
 437  */
 438
 439 #define BIR_INDEX_REGISTER (1 << 31)
 440 #define BIR_INDEX_UNIFORM  (1 << 30)
 441 #define BIR_INDEX_CONSTANT (1 << 29)
 442 #define BIR_INDEX_ZERO     (1 << 28)
 443 #define BIR_INDEX_PASS     (1 << 27)
 444
 445 /* Keep me synced please so we can check src & BIR_SPECIAL */
 446
 447 #define BIR_SPECIAL        ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
 448         (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
 449
 450 static inline unsigned
 451 bi_max_temp(bi_context *ctx)
 452 {
 453         unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc);
 454         return ((alloc + 2 + ctx->temp_alloc) << 1);
 455 }
 456
 457 static inline unsigned
 458 bi_make_temp(bi_context *ctx)
 459 {
 460         return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1;
 461 }
 462
 463 static inline unsigned
 464 bi_make_temp_reg(bi_context *ctx)
 465 {
 466         return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | PAN_IS_REG;
 467 }
 468
 469 /* Iterators for Bifrost IR */
 470
 471 #define bi_foreach_block(ctx, v) \
 472         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 473
 474 #define bi_foreach_block_from(ctx, from, v) \
 475         list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
 476
 477 #define bi_foreach_instr_in_block(block, v) \
 478         list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
 479
 480 #define bi_foreach_instr_in_block_rev(block, v) \
 481         list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
 482
 483 #define bi_foreach_instr_in_block_safe(block, v) \
 484         list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
 485
 486 #define bi_foreach_instr_in_block_safe_rev(block, v) \
 487         list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
 488
 489 #define bi_foreach_instr_in_block_from(block, v, from) \
 490         list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
 491
 492 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
 493         list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
 494
 495 #define bi_foreach_clause_in_block(block, v) \
 496         list_for_each_entry(bi_clause, v, &(block)->clauses, link)
 497
 498 #define bi_foreach_instr_global(ctx, v) \
 499         bi_foreach_block(ctx, v_block) \
 500                 bi_foreach_instr_in_block((bi_block *) v_block, v)
 501
 502 #define bi_foreach_instr_global_safe(ctx, v) \
 503         bi_foreach_block(ctx, v_block) \
 504                 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
 505
 506 /* Based on set_foreach, expanded with automatic type casts */
 507
 508 #define bi_foreach_predecessor(blk, v) \
 509         struct set_entry *_entry_##v; \
 510         bi_block *v; \
 511         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 512                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 513                 _entry_##v != NULL; \
 514                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 515                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
 516
 517 #define bi_foreach_src(ins, v) \
 518         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 519
 520 static inline bi_instruction *
 521 bi_prev_op(bi_instruction *ins)
 522 {
 523         return list_last_entry(&(ins->link), bi_instruction, link);
 524 }
 525
 526 static inline bi_instruction *
 527 bi_next_op(bi_instruction *ins)
 528 {
 529         return list_first_entry(&(ins->link), bi_instruction, link);
 530 }
 531
 532 static inline pan_block *
 533 pan_next_block(pan_block *block)
 534 {
 535         return list_first_entry(&(block->link), pan_block, link);
 536 }
 537
 538 /* Special functions */
 539
 540 void bi_emit_fexp2(bi_context *ctx, nir_alu_instr *instr);
 541 void bi_emit_flog2(bi_context *ctx, nir_alu_instr *instr);
 542
 543 /* BIR manipulation */
 544
 545 bool bi_has_outmod(bi_instruction *ins);
 546 bool bi_has_source_mods(bi_instruction *ins);
 547 bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
 548 bool bi_has_arg(bi_instruction *ins, unsigned arg);
 549 uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes);
 550 unsigned bi_get_component_count(bi_instruction *ins, signed s);
 551 uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node);
 552 uint64_t bi_get_immediate(bi_instruction *ins, unsigned index);
 553 bool bi_writes_component(bi_instruction *ins, unsigned comp);
 554 unsigned bi_writemask(bi_instruction *ins);
 555
 556 /* BIR passes */
 557
 558 void bi_lower_combine(bi_context *ctx, bi_block *block);
 559 bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
 560 void bi_schedule(bi_context *ctx);
 561 void bi_register_allocate(bi_context *ctx);
 562
 563 /* Liveness */
 564
 565 void bi_compute_liveness(bi_context *ctx);
 566 void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max);
 567 void bi_invalidate_liveness(bi_context *ctx);
 568 bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src);
 569
 570 /* Code emit */
 571
 572 void bi_pack(bi_context *ctx, struct util_dynarray *emission);
 573
 574 #endif