src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 #include "bifrost.h"
  31 #include "compiler/nir/nir.h"
  32 #include "panfrost/util/pan_ir.h"
  33
  34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  35  * ADD with two completely different opcodes, and opcodes can be varying
  36  * length in some cases. Then we have different opcodes for int vs float
  37  * and then sometimes even for different typesizes. Further, virtually
  38  * every op has a number of flags which depend on the op. In constrast
  39  * to Midgard where you have a strict ALU/LDST/TEX division and within
  40  * ALU you have strict int/float and that's it... here it's a *lot* more
  41  * involved. As such, we use something much higher level for our IR,
  42  * encoding "classes" of operations, letting the opcode details get
  43  * sorted out at emit time.
  44  *
  45  * Please keep this list alphabetized. Please use a dictionary if you
  46  * don't know how to do that.
  47  */
  48
  49 enum bi_class {
  50         BI_ADD,
  51         BI_ATEST,
  52         BI_BRANCH,
  53         BI_CMP,
  54         BI_BLEND,
  55         BI_BITWISE,
  56         BI_CONVERT,
  57         BI_CSEL,
  58         BI_DISCARD,
  59         BI_FMA,
  60         BI_FMOV,
  61         BI_FREXP,
  62         BI_ISUB,
  63         BI_LOAD,
  64         BI_LOAD_UNIFORM,
  65         BI_LOAD_ATTR,
  66         BI_LOAD_VAR,
  67         BI_LOAD_VAR_ADDRESS,
  68         BI_MINMAX,
  69         BI_MOV,
  70         BI_SHIFT,
  71         BI_STORE,
  72         BI_STORE_VAR,
  73         BI_SPECIAL, /* _FAST, _TABLE on supported GPUs */
  74         BI_SWIZZLE,
  75         BI_TEX,
  76         BI_ROUND,
  77         BI_NUM_CLASSES
  78 };
  79
  80 /* Properties of a class... */
  81 extern unsigned bi_class_props[BI_NUM_CLASSES];
  82
  83 /* abs/neg/outmod valid for a float op */
  84 #define BI_MODS (1 << 0)
  85
  86 /* Generic enough that little class-specific information is required. In other
  87  * words, it acts as a "normal" ALU op, even if the encoding ends up being
  88  * irregular enough to warrant a separate class */
  89 #define BI_GENERIC (1 << 1)
  90
  91 /* Accepts a bifrost_roundmode */
  92 #define BI_ROUNDMODE (1 << 2)
  93
  94 /* Can be scheduled to FMA */
  95 #define BI_SCHED_FMA (1 << 3)
  96
  97 /* Can be scheduled to ADD */
  98 #define BI_SCHED_ADD (1 << 4)
  99
 100 /* Most ALU ops can do either, actually */
 101 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
 102
 103 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
 104  * nopped out. Used for _FAST operations. */
 105 #define BI_SCHED_SLOW (1 << 5)
 106
 107 /* Swizzling allowed for the 8/16-bit source */
 108 #define BI_SWIZZLABLE (1 << 6)
 109
 110 /* For scheduling purposes this is a high latency instruction and must be at
 111  * the end of a clause. Implies ADD */
 112 #define BI_SCHED_HI_LATENCY (1 << 7)
 113
 114 /* Intrinsic is vectorized and should read 4 components in the first source
 115  * regardless of writemask */
 116 #define BI_VECTOR (1 << 8)
 117
 118 /* Use a data register for src0/dest respectively, bypassing the usual
 119  * register accessor. Mutually exclusive. */
 120 #define BI_DATA_REG_SRC (1 << 9)
 121 #define BI_DATA_REG_DEST (1 << 10)
 122
 123 /* It can't get any worse than csel4... can it? */
 124 #define BIR_SRC_COUNT 4
 125
 126 /* BI_LD_VARY */
 127 struct bi_load_vary {
 128         enum bifrost_interp_mode interp_mode;
 129         bool reuse;
 130         bool flat;
 131 };
 132
 133 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
 134  * the target. We forward declare bi_block since this is mildly circular (not
 135  * strictly, but this order of the file makes more sense I think)
 136  *
 137  * We define our own enum of conditions since the conditions in the hardware
 138  * packed in crazy ways that would make manipulation unweildly (meaning changes
 139  * based on port swapping, etc), so we defer dealing with that until emit time.
 140  * Likewise, we expose NIR types instead of the crazy branch types, although
 141  * the restrictions do eventually apply of course. */
 142
 143 struct bi_block;
 144
 145 enum bi_cond {
 146         BI_COND_ALWAYS,
 147         BI_COND_LT,
 148         BI_COND_LE,
 149         BI_COND_GE,
 150         BI_COND_GT,
 151         BI_COND_EQ,
 152         BI_COND_NE,
 153 };
 154
 155 struct bi_branch {
 156         /* Types are specified in src_types and must be compatible (either both
 157          * int, or both float, 16/32, and same size or 32/16 if float. Types
 158          * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
 159
 160         enum bi_cond cond;
 161         struct bi_block *target;
 162 };
 163
 164 /* Opcodes within a class */
 165 enum bi_minmax_op {
 166         BI_MINMAX_MIN,
 167         BI_MINMAX_MAX
 168 };
 169
 170 enum bi_bitwise_op {
 171         BI_BITWISE_AND,
 172         BI_BITWISE_OR,
 173         BI_BITWISE_XOR
 174 };
 175
 176 enum bi_round_op {
 177         BI_ROUND_MODE, /* use round mode */
 178         BI_ROUND_ROUND /* i.e.: fround() */
 179 };
 180
 181 enum bi_special_op {
 182         BI_SPECIAL_FRCP,
 183         BI_SPECIAL_FRSQ,
 184         BI_SPECIAL_FATAN,
 185         BI_SPECIAL_FSIN,
 186         BI_SPECIAL_FCOS,
 187         BI_SPECIAL_FEXP,
 188         BI_SPECIAL_FLOG2,
 189         BI_SPECIAL_FLOGE
 190 };
 191
 192 typedef struct {
 193         struct list_head link; /* Must be first */
 194         enum bi_class type;
 195
 196         /* Indices, see bir_ssa_index etc. Note zero is special cased
 197          * to "no argument" */
 198         unsigned dest;
 199         unsigned src[BIR_SRC_COUNT];
 200
 201         /* If one of the sources has BIR_INDEX_CONSTANT */
 202         union {
 203                 uint64_t u64;
 204                 uint32_t u32;
 205                 uint16_t u16[2];
 206                 uint8_t u8[4];
 207         } constant;
 208
 209         /* Floating-point modifiers, type/class permitting. If not
 210          * allowed for the type/class, these are ignored. */
 211         enum bifrost_outmod outmod;
 212         bool src_abs[BIR_SRC_COUNT];
 213         bool src_neg[BIR_SRC_COUNT];
 214
 215         /* Round mode (requires BI_ROUNDMODE) */
 216         enum bifrost_roundmode roundmode;
 217
 218         /* Writemask (bit for each affected byte). This is quite restricted --
 219          * ALU ops can only write to a single channel (exception: <32 in which
 220          * you can write to 32/N contiguous aligned channels). Load/store can
 221          * only write to all channels at once, in a sense. But it's still
 222          * better to use this generic form than have synthetic ops flying
 223          * about, since we're not essentially vector for RA purposes. */
 224         uint16_t writemask;
 225
 226         /* Destination type. Usually the type of the instruction
 227          * itself, but if sources and destination have different
 228          * types, the type of the destination wins (so f2i would be
 229          * int). Zero if there is no destination. Bitsize included */
 230         nir_alu_type dest_type;
 231
 232         /* Source types if required by the class */
 233         nir_alu_type src_types[BIR_SRC_COUNT];
 234
 235         /* If the source type is 8-bit or 16-bit such that SIMD is possible,
 236          * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
 237          * sense. On non-SIMD instructions, it can be used for component
 238          * selection, so we don't have to special case extraction. */
 239         uint8_t swizzle[BIR_SRC_COUNT][NIR_MAX_VEC_COMPONENTS];
 240
 241         /* A class-specific op from which the actual opcode can be derived
 242          * (along with the above information) */
 243
 244         union {
 245                 enum bi_minmax_op minmax;
 246                 enum bi_bitwise_op bitwise;
 247                 enum bi_round_op round;
 248                 enum bi_special_op special;
 249                 enum bi_cond compare;
 250         } op;
 251
 252         /* Union for class-specific information */
 253         union {
 254                 enum bifrost_minmax_mode minmax;
 255                 struct bi_load_vary load_vary;
 256                 struct bi_branch branch;
 257
 258                 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
 259                  * sense here but you can always just use a move for that */
 260                 enum bi_cond csel_cond;
 261
 262                 /* For BLEND -- the location 0-7 */
 263                 unsigned blend_location;
 264
 265                 /* For STORE, STORE_VAR -- channel count */
 266                 unsigned store_channels;
 267         };
 268 } bi_instruction;
 269
 270 /* Scheduling takes place in two steps. Step 1 groups instructions within a
 271  * block into distinct clauses (bi_clause). Step 2 schedules instructions
 272  * within a clause into FMA/ADD pairs (bi_bundle).
 273  *
 274  * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
 275  * leave it NULL; the emitter will fill in a nop.
 276  */
 277
 278 typedef struct {
 279         bi_instruction *fma;
 280         bi_instruction *add;
 281 } bi_bundle;
 282
 283 typedef struct {
 284         struct list_head link;
 285
 286         /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
 287          * can be 8 bundles. But each bundle can have both an FMA and an ADD,
 288          * so a clause can have up to 16 bi_instructions. Whether bundles or
 289          * instructions are used depends on where in scheduling we are. */
 290
 291         unsigned instruction_count;
 292         unsigned bundle_count;
 293
 294         union {
 295                 bi_instruction *instructions[16];
 296                 bi_bundle bundles[8];
 297         };
 298
 299         /* For scoreboarding -- the clause ID (this is not globally unique!)
 300          * and its dependencies in terms of other clauses, computed during
 301          * scheduling and used when emitting code. Dependencies expressed as a
 302          * bitfield matching the hardware, except shifted by a clause (the
 303          * shift back to the ISA's off-by-one encoding is worked out when
 304          * emitting clauses) */
 305         unsigned scoreboard_id;
 306         uint8_t dependencies;
 307
 308         /* Back-to-back corresponds directly to the back-to-back bit. Branch
 309          * conditional corresponds to the branch conditional bit except that in
 310          * the emitted code it's always set if back-to-bit is, whereas we use
 311          * the actual value (without back-to-back so to speak) internally */
 312         bool back_to_back;
 313         bool branch_conditional;
 314
 315         /* Assigned data register */
 316         unsigned data_register;
 317
 318         /* Corresponds to the usual bit but shifted by a clause */
 319         bool data_register_write_barrier;
 320
 321         /* Constants read by this clause. ISA limit. */
 322         uint64_t constants[8];
 323         unsigned constant_count;
 324
 325         /* What type of high latency instruction is here, basically */
 326         unsigned clause_type;
 327 } bi_clause;
 328
 329 typedef struct bi_block {
 330         pan_block base; /* must be first */
 331
 332         /* If true, uses clauses; if false, uses instructions */
 333         bool scheduled;
 334         struct list_head clauses; /* list of bi_clause */
 335 } bi_block;
 336
 337 typedef struct {
 338        nir_shader *nir;
 339        gl_shader_stage stage;
 340        struct list_head blocks; /* list of bi_block */
 341        struct panfrost_sysvals sysvals;
 342        uint32_t quirks;
 343
 344        /* During NIR->BIR */
 345        nir_function_impl *impl;
 346        bi_block *current_block;
 347        unsigned block_name_count;
 348        bi_block *after_block;
 349        bi_block *break_block;
 350        bi_block *continue_block;
 351        bool emitted_atest;
 352
 353        /* For creating temporaries */
 354        unsigned temp_alloc;
 355
 356        /* Analysis results */
 357        bool has_liveness;
 358
 359        /* Stats for shader-db */
 360        unsigned instruction_count;
 361        unsigned loop_count;
 362 } bi_context;
 363
 364 static inline bi_instruction *
 365 bi_emit(bi_context *ctx, bi_instruction ins)
 366 {
 367         bi_instruction *u = rzalloc(ctx, bi_instruction);
 368         memcpy(u, &ins, sizeof(ins));
 369         list_addtail(&u->link, &ctx->current_block->base.instructions);
 370         return u;
 371 }
 372
 373 static inline bi_instruction *
 374 bi_emit_before(bi_context *ctx, bi_instruction *tag, bi_instruction ins)
 375 {
 376         bi_instruction *u = rzalloc(ctx, bi_instruction);
 377         memcpy(u, &ins, sizeof(ins));
 378         list_addtail(&u->link, &tag->link);
 379         return u;
 380 }
 381
 382 static inline void
 383 bi_remove_instruction(bi_instruction *ins)
 384 {
 385         list_del(&ins->link);
 386 }
 387
 388 /* So we can distinguish between SSA/reg/sentinel quickly */
 389 #define BIR_NO_ARG (0)
 390 #define BIR_IS_REG (1)
 391
 392 /* If high bits are set, instead of SSA/registers, we have specials indexed by
 393  * the low bits if necessary.
 394  *
 395  *  Fixed register: do not allocate register, do not collect $200.
 396  *  Uniform: access a uniform register given by low bits.
 397  *  Constant: access the specified constant (specifies a bit offset / shift)
 398  *  Zero: special cased to avoid wasting a constant
 399  *  Passthrough: a bifrost_packed_src to passthrough T/T0/T1
 400  */
 401
 402 #define BIR_INDEX_REGISTER (1 << 31)
 403 #define BIR_INDEX_UNIFORM  (1 << 30)
 404 #define BIR_INDEX_CONSTANT (1 << 29)
 405 #define BIR_INDEX_ZERO     (1 << 28)
 406 #define BIR_INDEX_PASS     (1 << 27)
 407
 408 /* Keep me synced please so we can check src & BIR_SPECIAL */
 409
 410 #define BIR_SPECIAL        ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
 411         (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO | BIR_INDEX_PASS))
 412
 413 static inline unsigned
 414 bi_max_temp(bi_context *ctx)
 415 {
 416         unsigned alloc = MAX2(ctx->impl->reg_alloc, ctx->impl->ssa_alloc);
 417         return ((alloc + 2 + ctx->temp_alloc) << 1);
 418 }
 419
 420 static inline unsigned
 421 bi_make_temp(bi_context *ctx)
 422 {
 423         return (ctx->impl->ssa_alloc + 1 + ctx->temp_alloc++) << 1;
 424 }
 425
 426 static inline unsigned
 427 bi_make_temp_reg(bi_context *ctx)
 428 {
 429         return ((ctx->impl->reg_alloc + ctx->temp_alloc++) << 1) | BIR_IS_REG;
 430 }
 431
 432 static inline unsigned
 433 bir_ssa_index(nir_ssa_def *ssa)
 434 {
 435         /* Off-by-one ensures BIR_NO_ARG is skipped */
 436         return ((ssa->index + 1) << 1) | 0;
 437 }
 438
 439 static inline unsigned
 440 bir_src_index(nir_src *src)
 441 {
 442         if (src->is_ssa)
 443                 return bir_ssa_index(src->ssa);
 444         else {
 445                 assert(!src->reg.indirect);
 446                 return (src->reg.reg->index << 1) | BIR_IS_REG;
 447         }
 448 }
 449
 450 static inline unsigned
 451 bir_dest_index(nir_dest *dst)
 452 {
 453         if (dst->is_ssa)
 454                 return bir_ssa_index(&dst->ssa);
 455         else {
 456                 assert(!dst->reg.indirect);
 457                 return (dst->reg.reg->index << 1) | BIR_IS_REG;
 458         }
 459 }
 460
 461 /* Iterators for Bifrost IR */
 462
 463 #define bi_foreach_block(ctx, v) \
 464         list_for_each_entry(pan_block, v, &ctx->blocks, link)
 465
 466 #define bi_foreach_block_from(ctx, from, v) \
 467         list_for_each_entry_from(pan_block, v, from, &ctx->blocks, link)
 468
 469 #define bi_foreach_instr_in_block(block, v) \
 470         list_for_each_entry(bi_instruction, v, &(block)->base.instructions, link)
 471
 472 #define bi_foreach_instr_in_block_rev(block, v) \
 473         list_for_each_entry_rev(bi_instruction, v, &(block)->base.instructions, link)
 474
 475 #define bi_foreach_instr_in_block_safe(block, v) \
 476         list_for_each_entry_safe(bi_instruction, v, &(block)->base.instructions, link)
 477
 478 #define bi_foreach_instr_in_block_safe_rev(block, v) \
 479         list_for_each_entry_safe_rev(bi_instruction, v, &(block)->base.instructions, link)
 480
 481 #define bi_foreach_instr_in_block_from(block, v, from) \
 482         list_for_each_entry_from(bi_instruction, v, from, &(block)->base.instructions, link)
 483
 484 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
 485         list_for_each_entry_from_rev(bi_instruction, v, from, &(block)->base.instructions, link)
 486
 487 #define bi_foreach_clause_in_block(block, v) \
 488         list_for_each_entry(bi_clause, v, &(block)->clauses, link)
 489
 490 #define bi_foreach_instr_global(ctx, v) \
 491         bi_foreach_block(ctx, v_block) \
 492                 bi_foreach_instr_in_block((bi_block *) v_block, v)
 493
 494 #define bi_foreach_instr_global_safe(ctx, v) \
 495         bi_foreach_block(ctx, v_block) \
 496                 bi_foreach_instr_in_block_safe((bi_block *) v_block, v)
 497
 498 /* Based on set_foreach, expanded with automatic type casts */
 499
 500 #define bi_foreach_predecessor(blk, v) \
 501         struct set_entry *_entry_##v; \
 502         bi_block *v; \
 503         for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
 504                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL);  \
 505                 _entry_##v != NULL; \
 506                 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
 507                 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
 508
 509 #define bi_foreach_src(ins, v) \
 510         for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
 511
 512 static inline bi_instruction *
 513 bi_prev_op(bi_instruction *ins)
 514 {
 515         return list_last_entry(&(ins->link), bi_instruction, link);
 516 }
 517
 518 static inline bi_instruction *
 519 bi_next_op(bi_instruction *ins)
 520 {
 521         return list_first_entry(&(ins->link), bi_instruction, link);
 522 }
 523
 524 static inline pan_block *
 525 pan_next_block(pan_block *block)
 526 {
 527         return list_first_entry(&(block->link), pan_block, link);
 528 }
 529
 530 /* BIR manipulation */
 531
 532 bool bi_has_outmod(bi_instruction *ins);
 533 bool bi_has_source_mods(bi_instruction *ins);
 534 bool bi_is_src_swizzled(bi_instruction *ins, unsigned s);
 535 bool bi_has_arg(bi_instruction *ins, unsigned arg);
 536 uint16_t bi_from_bytemask(uint16_t bytemask, unsigned bytes);
 537 unsigned bi_get_component_count(bi_instruction *ins, unsigned s);
 538 unsigned bi_load32_components(bi_instruction *ins);
 539 uint16_t bi_bytemask_of_read_components(bi_instruction *ins, unsigned node);
 540 uint64_t bi_get_immediate(bi_instruction *ins, unsigned index);
 541
 542 /* BIR passes */
 543
 544 bool bi_opt_dead_code_eliminate(bi_context *ctx, bi_block *block);
 545 void bi_schedule(bi_context *ctx);
 546 void bi_register_allocate(bi_context *ctx);
 547
 548 /* Liveness */
 549
 550 void bi_compute_liveness(bi_context *ctx);
 551 void bi_liveness_ins_update(uint16_t *live, bi_instruction *ins, unsigned max);
 552 void bi_invalidate_liveness(bi_context *ctx);
 553 bool bi_is_live_after(bi_context *ctx, bi_block *block, bi_instruction *start, int src);
 554
 555 /* Code emit */
 556
 557 void bi_pack(bi_context *ctx, struct util_dynarray *emission);
 558
 559 #endif