src/panfrost/bifrost/compiler.h

   1 /*
   2  * Copyright (C) 2020 Collabora Ltd.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors (Collabora):
  24  *      Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
  25  */
  26
  27 #ifndef __BIFROST_COMPILER_H
  28 #define __BIFROST_COMPILER_H
  29
  30 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
  31  * ADD with two completely different opcodes, and opcodes can be varying
  32  * length in some cases. Then we have different opcodes for int vs float
  33  * and then sometimes even for different typesizes. Further, virtually
  34  * every op has a number of flags which depend on the op. In constrast
  35  * to Midgard where you have a strict ALU/LDST/TEX division and within
  36  * ALU you have strict int/float and that's it... here it's a *lot* more
  37  * involved. As such, we use something much higher level for our IR,
  38  * encoding "classes" of operations, letting the opcode details get
  39  * sorted out at emit time.
  40  *
  41  * Please keep this list alphabetized. Please use a dictionary if you
  42  * don't know how to do that.
  43  */
  44
  45 enum bi_class {
  46         BI_ADD,
  47         BI_ATEST,
  48         BI_BRANCH,
  49         BI_CMP,
  50         BI_BLEND,
  51         BI_BITWISE,
  52         BI_CONVERT,
  53         BI_CSEL,
  54         BI_DISCARD,
  55         BI_FMA,
  56         BI_FREXP,
  57         BI_LOAD,
  58         BI_LOAD_ATTR,
  59         BI_LOAD_VAR,
  60         BI_LOAD_VAR_ADDRESS,
  61         BI_MINMAX,
  62         BI_MOV,
  63         BI_SHIFT,
  64         BI_STORE,
  65         BI_STORE_VAR,
  66         BI_SPECIAL, /* _FAST, _TABLE on supported GPUs */
  67         BI_TEX,
  68         BI_ROUND,
  69 };
  70
  71 /* It can't get any worse than csel4... can it? */
  72 #define BIR_SRC_COUNT 4
  73
  74 typedef struct {
  75         struct list_head link; /* Must be first */
  76         enum bi_class type;
  77
  78         /* Indices, see bir_ssa_index etc. Note zero is special cased
  79          * to "no argument" */
  80         unsigned dest;
  81         unsigned src[BIR_SRC_COUNT];
  82 } bi_instruction;
  83
  84 typedef struct {
  85         struct list_head link; /* must be first */
  86         struct list_head instructions; /* list of bi_instructions */
  87 } bi_block;
  88
  89 typedef struct {
  90        nir_shader *nir;
  91        struct list_head blocks; /* list of bi_block */
  92 } bi_context;
  93
  94 /* So we can distinguish between SSA/reg/sentinel quickly */
  95 #define BIR_NO_ARG (0)
  96 #define BIR_IS_REG (1)
  97
  98 static inline unsigned
  99 bir_ssa_index(nir_ssa_def *ssa)
 100 {
 101         /* Off-by-one ensures BIR_NO_ARG is skipped */
 102         return ((ssa->index + 1) << 1) | 0;
 103 }
 104
 105 static inline unsigned
 106 bir_src_index(nir_src *src)
 107 {
 108         if (src->is_ssa)
 109                 return bir_ssa_index(src->ssa);
 110         else {
 111                 assert(!src->reg.indirect);
 112                 return (src->reg.reg->index << 1) | BIR_IS_REG;
 113         }
 114 }
 115
 116 static inline unsigned
 117 bir_dest_index(nir_dest *dst)
 118 {
 119         if (dst->is_ssa)
 120                 return bir_ssa_index(&dst->ssa);
 121         else {
 122                 assert(!dst->reg.indirect);
 123                 return (dst->reg.reg->index << 1) | BIR_IS_REG;
 124         }
 125 }
 126
 127 #endif