pan/bi: Add PAN_SCHED_* flags
[mesa.git] / src / panfrost / bifrost / compiler.h
1 /*
2 * Copyright (C) 2020 Collabora Ltd.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
25 */
26
27 #ifndef __BIFROST_COMPILER_H
28 #define __BIFROST_COMPILER_H
29
30 #include "bifrost.h"
31 #include "compiler/nir/nir.h"
32
33 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
34 * ADD with two completely different opcodes, and opcodes can be varying
35 * length in some cases. Then we have different opcodes for int vs float
36 * and then sometimes even for different typesizes. Further, virtually
37 * every op has a number of flags which depend on the op. In constrast
38 * to Midgard where you have a strict ALU/LDST/TEX division and within
39 * ALU you have strict int/float and that's it... here it's a *lot* more
40 * involved. As such, we use something much higher level for our IR,
41 * encoding "classes" of operations, letting the opcode details get
42 * sorted out at emit time.
43 *
44 * Please keep this list alphabetized. Please use a dictionary if you
45 * don't know how to do that.
46 */
47
48 enum bi_class {
49 BI_ADD,
50 BI_ATEST,
51 BI_BRANCH,
52 BI_CMP,
53 BI_BLEND,
54 BI_BITWISE,
55 BI_CONVERT,
56 BI_CSEL,
57 BI_DISCARD,
58 BI_FMA,
59 BI_FREXP,
60 BI_LOAD,
61 BI_LOAD_ATTR,
62 BI_LOAD_VAR,
63 BI_LOAD_VAR_ADDRESS,
64 BI_MINMAX,
65 BI_MOV,
66 BI_SHIFT,
67 BI_STORE,
68 BI_STORE_VAR,
69 BI_SPECIAL, /* _FAST, _TABLE on supported GPUs */
70 BI_TEX,
71 BI_ROUND,
72 BI_NUM_CLASSES
73 };
74
75 /* Properties of a class... */
76 extern unsigned bi_class_props[BI_NUM_CLASSES];
77
78 /* abs/neg/outmod valid for a float op */
79 #define BI_MODS (1 << 0)
80
81 /* Generic enough that little class-specific information is required. In other
82 * words, it acts as a "normal" ALU op, even if the encoding ends up being
83 * irregular enough to warrant a separate class */
84 #define BI_GENERIC (1 << 1)
85
86 /* Accepts a bifrost_roundmode */
87 #define BI_ROUNDMODE (1 << 2)
88
89 /* Can be scheduled to FMA */
90 #define BI_SCHED_FMA (1 << 3)
91
92 /* Can be scheduled to ADD */
93 #define BI_SCHED_ADD (1 << 4)
94
95 /* Most ALU ops can do either, actually */
96 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
97
98 /* It can't get any worse than csel4... can it? */
99 #define BIR_SRC_COUNT 4
100
101 /* Class-specific data for BI_LD_ATTR, BI_LD_VAR_ADDR */
102 struct bi_load {
103 /* Note: no indirects here */
104 unsigned location;
105
106 /* Only for BI_LD_ATTR. But number of vector channels */
107 unsigned channels;
108 };
109
110 /* BI_LD_VARY */
111 struct bi_load_vary {
112 /* All parameters used here. Indirect location specified in
113 * src1 and ignoring location, if present. */
114 struct bi_load load;
115
116 enum bifrost_interp_mode interp_mode;
117 bool reuse;
118 bool flat;
119 };
120
121 typedef struct {
122 struct list_head link; /* Must be first */
123 enum bi_class type;
124
125 /* Indices, see bir_ssa_index etc. Note zero is special cased
126 * to "no argument" */
127 unsigned dest;
128 unsigned src[BIR_SRC_COUNT];
129
130 /* Floating-point modifiers, type/class permitting. If not
131 * allowed for the type/class, these are ignored. */
132 enum bifrost_outmod outmod;
133 bool src_abs[BIR_SRC_COUNT];
134 bool src_neg[BIR_SRC_COUNT];
135
136 /* Round mode (requires BI_ROUNDMODE) */
137 enum bifrost_roundmode roundmode;
138
139 /* Union for class-specific information */
140 union {
141 enum bifrost_minmax_mode minmax;
142 struct bi_load load;
143 struct bi_load_vary load_vary;
144 };
145 } bi_instruction;
146
147 typedef struct {
148 struct list_head link; /* must be first */
149 struct list_head instructions; /* list of bi_instructions */
150 } bi_block;
151
152 typedef struct {
153 nir_shader *nir;
154 struct list_head blocks; /* list of bi_block */
155 } bi_context;
156
157 /* So we can distinguish between SSA/reg/sentinel quickly */
158 #define BIR_NO_ARG (0)
159 #define BIR_IS_REG (1)
160
161 static inline unsigned
162 bir_ssa_index(nir_ssa_def *ssa)
163 {
164 /* Off-by-one ensures BIR_NO_ARG is skipped */
165 return ((ssa->index + 1) << 1) | 0;
166 }
167
168 static inline unsigned
169 bir_src_index(nir_src *src)
170 {
171 if (src->is_ssa)
172 return bir_ssa_index(src->ssa);
173 else {
174 assert(!src->reg.indirect);
175 return (src->reg.reg->index << 1) | BIR_IS_REG;
176 }
177 }
178
179 static inline unsigned
180 bir_dest_index(nir_dest *dst)
181 {
182 if (dst->is_ssa)
183 return bir_ssa_index(&dst->ssa);
184 else {
185 assert(!dst->reg.indirect);
186 return (dst->reg.reg->index << 1) | BIR_IS_REG;
187 }
188 }
189
190 #endif