2 * Copyright (C) 2020 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
27 #ifndef __BIFROST_COMPILER_H
28 #define __BIFROST_COMPILER_H
31 #include "compiler/nir/nir.h"
32 #include "panfrost/util/pan_ir.h"
34 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
35 * ADD with two completely different opcodes, and opcodes can be varying
36 * length in some cases. Then we have different opcodes for int vs float
37 * and then sometimes even for different typesizes. Further, virtually
38 * every op has a number of flags which depend on the op. In constrast
39 * to Midgard where you have a strict ALU/LDST/TEX division and within
40 * ALU you have strict int/float and that's it... here it's a *lot* more
41 * involved. As such, we use something much higher level for our IR,
42 * encoding "classes" of operations, letting the opcode details get
43 * sorted out at emit time.
45 * Please keep this list alphabetized. Please use a dictionary if you
46 * don't know how to do that.
71 BI_SPECIAL
, /* _FAST, _TABLE on supported GPUs */
78 /* Properties of a class... */
79 extern unsigned bi_class_props
[BI_NUM_CLASSES
];
81 /* abs/neg/outmod valid for a float op */
82 #define BI_MODS (1 << 0)
84 /* Generic enough that little class-specific information is required. In other
85 * words, it acts as a "normal" ALU op, even if the encoding ends up being
86 * irregular enough to warrant a separate class */
87 #define BI_GENERIC (1 << 1)
89 /* Accepts a bifrost_roundmode */
90 #define BI_ROUNDMODE (1 << 2)
92 /* Can be scheduled to FMA */
93 #define BI_SCHED_FMA (1 << 3)
95 /* Can be scheduled to ADD */
96 #define BI_SCHED_ADD (1 << 4)
98 /* Most ALU ops can do either, actually */
99 #define BI_SCHED_ALL (BI_SCHED_FMA | BI_SCHED_ADD)
101 /* Along with setting BI_SCHED_ADD, eats up the entire cycle, so FMA must be
102 * nopped out. Used for _FAST operations. */
103 #define BI_SCHED_SLOW (1 << 5)
105 /* Swizzling allowed for the 8/16-bit source */
106 #define BI_SWIZZLABLE (1 << 6)
108 /* For scheduling purposes this is a high latency instruction and must be at
109 * the end of a clause. Implies ADD */
110 #define BI_SCHED_HI_LATENCY ((1 << 7) | BI_SCHED_ADD)
112 /* It can't get any worse than csel4... can it? */
113 #define BIR_SRC_COUNT 4
116 struct bi_load_vary
{
117 enum bifrost_interp_mode interp_mode
;
122 /* BI_BRANCH encoding the details of the branch itself as well as a pointer to
123 * the target. We forward declare bi_block since this is mildly circular (not
124 * strictly, but this order of the file makes more sense I think)
126 * We define our own enum of conditions since the conditions in the hardware
127 * packed in crazy ways that would make manipulation unweildly (meaning changes
128 * based on port swapping, etc), so we defer dealing with that until emit time.
129 * Likewise, we expose NIR types instead of the crazy branch types, although
130 * the restrictions do eventually apply of course. */
145 /* Types are specified in src_types and must be compatible (either both
146 * int, or both float, 16/32, and same size or 32/16 if float. Types
147 * ignored if BI_COND_ALWAYS is set for an unconditional branch. */
150 struct bi_block
*target
;
153 /* Opcodes within a class */
166 BI_ROUND_MODE
, /* use round mode */
167 BI_ROUND_ROUND
/* i.e.: fround() */
182 struct list_head link
; /* Must be first */
185 /* Indices, see bir_ssa_index etc. Note zero is special cased
186 * to "no argument" */
188 unsigned src
[BIR_SRC_COUNT
];
190 /* If one of the sources has BIR_INDEX_CONSTANT */
198 /* Floating-point modifiers, type/class permitting. If not
199 * allowed for the type/class, these are ignored. */
200 enum bifrost_outmod outmod
;
201 bool src_abs
[BIR_SRC_COUNT
];
202 bool src_neg
[BIR_SRC_COUNT
];
204 /* Round mode (requires BI_ROUNDMODE) */
205 enum bifrost_roundmode roundmode
;
207 /* Writemask (bit for each affected byte). This is quite restricted --
208 * ALU ops can only write to a single channel (exception: <32 in which
209 * you can write to 32/N contiguous aligned channels). Load/store can
210 * only write to all channels at once, in a sense. But it's still
211 * better to use this generic form than have synthetic ops flying
212 * about, since we're not essentially vector for RA purposes. */
215 /* Destination type. Usually the type of the instruction
216 * itself, but if sources and destination have different
217 * types, the type of the destination wins (so f2i would be
218 * int). Zero if there is no destination. Bitsize included */
219 nir_alu_type dest_type
;
221 /* Source types if required by the class */
222 nir_alu_type src_types
[BIR_SRC_COUNT
];
224 /* If the source type is 8-bit or 16-bit such that SIMD is possible,
225 * and the class has BI_SWIZZLABLE, this is a swizzle in the usual
226 * sense. On non-SIMD instructions, it can be used for component
227 * selection, so we don't have to special case extraction. */
228 uint8_t swizzle
[BIR_SRC_COUNT
][NIR_MAX_VEC_COMPONENTS
];
230 /* A class-specific op from which the actual opcode can be derived
231 * (along with the above information) */
234 enum bi_minmax_op minmax
;
235 enum bi_bitwise_op bitwise
;
236 enum bi_round_op round
;
237 enum bi_special_op special
;
240 /* Union for class-specific information */
242 enum bifrost_minmax_mode minmax
;
243 struct bi_load_vary load_vary
;
244 struct bi_branch branch
;
246 /* For CSEL, the comparison op. BI_COND_ALWAYS doesn't make
247 * sense here but you can always just use a move for that */
248 enum bi_cond csel_cond
;
250 /* For BLEND -- the location 0-7 */
251 unsigned blend_location
;
255 /* Scheduling takes place in two steps. Step 1 groups instructions within a
256 * block into distinct clauses (bi_clause). Step 2 schedules instructions
257 * within a clause into FMA/ADD pairs (bi_bundle).
259 * A bi_bundle contains two paired instruction pointers. If a slot is unfilled,
260 * leave it NULL; the emitter will fill in a nop.
269 struct list_head link
;
271 /* A clause can have 8 instructions in bundled FMA/ADD sense, so there
272 * can be 8 bundles. But each bundle can have both an FMA and an ADD,
273 * so a clause can have up to 16 bi_instructions. Whether bundles or
274 * instructions are used depends on where in scheduling we are. */
276 unsigned instruction_count
;
277 unsigned bundle_count
;
280 bi_instruction
*instructions
[16];
281 bi_bundle bundles
[8];
284 /* For scoreboarding -- the clause ID (this is not globally unique!)
285 * and its dependencies in terms of other clauses, computed during
286 * scheduling and used when emitting code. Dependencies expressed as a
287 * bitfield matching the hardware, except shifted by a clause (the
288 * shift back to the ISA's off-by-one encoding is worked out when
289 * emitting clauses) */
290 unsigned scoreboard_id
;
291 uint8_t dependencies
;
293 /* Back-to-back corresponds directly to the back-to-back bit. Branch
294 * conditional corresponds to the branch conditional bit except that in
295 * the emitted code it's always set if back-to-bit is, whereas we use
296 * the actual value (without back-to-back so to speak) internally */
298 bool branch_conditional
;
300 /* Corresponds to the usual bit but shifted by a clause */
301 bool data_register_write_barrier
;
303 /* Constants read by this clause. ISA limit. */
304 uint64_t constants
[8];
305 unsigned constant_count
;
308 typedef struct bi_block
{
309 struct list_head link
; /* must be first */
310 unsigned name
; /* Just for pretty-printing */
312 /* If true, uses clauses; if false, uses instructions */
314 struct list_head instructions
; /* pre-schedule, list of bi_instructions */
315 struct list_head clauses
; /* list of bi_clause */
317 /* Control flow graph */
318 struct set
*predecessors
;
319 struct bi_block
*successors
[2];
324 gl_shader_stage stage
;
325 struct list_head blocks
; /* list of bi_block */
328 /* During NIR->BIR */
329 nir_function_impl
*impl
;
330 bi_block
*current_block
;
331 unsigned block_name_count
;
332 bi_block
*after_block
;
333 bi_block
*break_block
;
334 bi_block
*continue_block
;
337 /* For creating temporaries */
340 /* Stats for shader-db */
341 unsigned instruction_count
;
345 static inline bi_instruction
*
346 bi_emit(bi_context
*ctx
, bi_instruction ins
)
348 bi_instruction
*u
= rzalloc(ctx
, bi_instruction
);
349 memcpy(u
, &ins
, sizeof(ins
));
350 list_addtail(&u
->link
, &ctx
->current_block
->instructions
);
355 bi_remove_instruction(bi_instruction
*ins
)
357 list_del(&ins
->link
);
360 /* So we can distinguish between SSA/reg/sentinel quickly */
361 #define BIR_NO_ARG (0)
362 #define BIR_IS_REG (1)
364 /* If high bits are set, instead of SSA/registers, we have specials indexed by
365 * the low bits if necessary.
367 * Fixed register: do not allocate register, do not collect $200.
368 * Uniform: access a uniform register given by low bits.
369 * Constant: access the specified constant
370 * Zero: special cased to avoid wasting a constant
373 #define BIR_INDEX_REGISTER (1 << 31)
374 #define BIR_INDEX_UNIFORM (1 << 30)
375 #define BIR_INDEX_CONSTANT (1 << 29)
376 #define BIR_INDEX_ZERO (1 << 28)
378 /* Keep me synced please so we can check src & BIR_SPECIAL */
380 #define BIR_SPECIAL ((BIR_INDEX_REGISTER | BIR_INDEX_UNIFORM) | \
381 (BIR_INDEX_CONSTANT | BIR_INDEX_ZERO)
383 static inline unsigned
384 bi_make_temp(bi_context
*ctx
)
386 return (ctx
->impl
->ssa_alloc
+ 1 + ctx
->temp_alloc
++) << 1;
389 static inline unsigned
390 bi_make_temp_reg(bi_context
*ctx
)
392 return ((ctx
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | BIR_IS_REG
;
395 static inline unsigned
396 bir_ssa_index(nir_ssa_def
*ssa
)
398 /* Off-by-one ensures BIR_NO_ARG is skipped */
399 return ((ssa
->index
+ 1) << 1) | 0;
402 static inline unsigned
403 bir_src_index(nir_src
*src
)
406 return bir_ssa_index(src
->ssa
);
408 assert(!src
->reg
.indirect
);
409 return (src
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
413 static inline unsigned
414 bir_dest_index(nir_dest
*dst
)
417 return bir_ssa_index(&dst
->ssa
);
419 assert(!dst
->reg
.indirect
);
420 return (dst
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
424 /* Iterators for Bifrost IR */
426 #define bi_foreach_block(ctx, v) \
427 list_for_each_entry(bi_block, v, &ctx->blocks, link)
429 #define bi_foreach_block_from(ctx, from, v) \
430 list_for_each_entry_from(bi_block, v, from, &ctx->blocks, link)
432 #define bi_foreach_instr_in_block(block, v) \
433 list_for_each_entry(bi_instruction, v, &block->instructions, link)
435 #define bi_foreach_instr_in_block_rev(block, v) \
436 list_for_each_entry_rev(bi_instruction, v, &block->instructions, link)
438 #define bi_foreach_instr_in_block_safe(block, v) \
439 list_for_each_entry_safe(bi_instruction, v, &block->instructions, link)
441 #define bi_foreach_instr_in_block_safe_rev(block, v) \
442 list_for_each_entry_safe_rev(bi_instruction, v, &block->instructions, link)
444 #define bi_foreach_instr_in_block_from(block, v, from) \
445 list_for_each_entry_from(bi_instruction, v, from, &block->instructions, link)
447 #define bi_foreach_instr_in_block_from_rev(block, v, from) \
448 list_for_each_entry_from_rev(bi_instruction, v, from, &block->instructions, link)
450 #define bi_foreach_clause_in_block(block, v) \
451 list_for_each_entry(bi_clause, v, &block->clauses, link)
453 #define bi_foreach_instr_global(ctx, v) \
454 bi_foreach_block(ctx, v_block) \
455 bi_foreach_instr_in_block(v_block, v)
457 #define bi_foreach_instr_global_safe(ctx, v) \
458 bi_foreach_block(ctx, v_block) \
459 bi_foreach_instr_in_block_safe(v_block, v)
461 #define bi_foreach_successor(blk, v) \
464 for (_v = &blk->successors[0], \
466 v != NULL && _v < &blk->successors[2]; \
469 /* Based on set_foreach, expanded with automatic type casts */
471 #define bi_foreach_predecessor(blk, v) \
472 struct set_entry *_entry_##v; \
474 for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
475 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL); \
476 _entry_##v != NULL; \
477 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
478 v = (bi_block *) (_entry_##v ? _entry_##v->key : NULL))
480 #define bi_foreach_src(ins, v) \
481 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
483 /* BIR manipulation */
485 bool bi_has_outmod(bi_instruction
*ins
);
486 bool bi_has_source_mods(bi_instruction
*ins
);
487 bool bi_is_src_swizzled(bi_instruction
*ins
, unsigned s
);
491 void bi_schedule(bi_context
*ctx
);