2 * Copyright (C) 2020 Collabora Ltd.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * Authors (Collabora):
24 * Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
27 #ifndef __BIFROST_COMPILER_H
28 #define __BIFROST_COMPILER_H
31 #include "compiler/nir/nir.h"
33 /* Bifrost opcodes are tricky -- the same op may exist on both FMA and
34 * ADD with two completely different opcodes, and opcodes can be varying
35 * length in some cases. Then we have different opcodes for int vs float
36 * and then sometimes even for different typesizes. Further, virtually
37 * every op has a number of flags which depend on the op. In constrast
38 * to Midgard where you have a strict ALU/LDST/TEX division and within
39 * ALU you have strict int/float and that's it... here it's a *lot* more
40 * involved. As such, we use something much higher level for our IR,
41 * encoding "classes" of operations, letting the opcode details get
42 * sorted out at emit time.
44 * Please keep this list alphabetized. Please use a dictionary if you
45 * don't know how to do that.
69 BI_SPECIAL
, /* _FAST, _TABLE on supported GPUs */
75 /* Properties of a class... */
76 extern unsigned bi_class_props
[BI_NUM_CLASSES
];
78 /* abs/neg/outmod valid for a float op */
79 #define BI_MODS (1 << 0)
81 /* Generic enough that little class-specific information is required. In other
82 * words, it acts as a "normal" ALU op, even if the encoding ends up being
83 * irregular enough to warrant a separate class */
84 #define BI_GENERIC (1 << 1)
86 /* Accepts a bifrost_roundmode */
87 #define BI_ROUNDMODE (1 << 2)
89 /* It can't get any worse than csel4... can it? */
90 #define BIR_SRC_COUNT 4
93 struct list_head link
; /* Must be first */
96 /* Indices, see bir_ssa_index etc. Note zero is special cased
99 unsigned src
[BIR_SRC_COUNT
];
101 /* Floating-point modifiers, type/class permitting. If not
102 * allowed for the type/class, these are ignored. */
103 enum bifrost_outmod outmod
;
104 bool src_abs
[BIR_SRC_COUNT
];
105 bool src_neg
[BIR_SRC_COUNT
];
107 /* Round mode (requires BI_ROUNDMODE) */
108 enum bifrost_roundmode roundmode
;
112 struct list_head link
; /* must be first */
113 struct list_head instructions
; /* list of bi_instructions */
118 struct list_head blocks
; /* list of bi_block */
121 /* So we can distinguish between SSA/reg/sentinel quickly */
122 #define BIR_NO_ARG (0)
123 #define BIR_IS_REG (1)
125 static inline unsigned
126 bir_ssa_index(nir_ssa_def
*ssa
)
128 /* Off-by-one ensures BIR_NO_ARG is skipped */
129 return ((ssa
->index
+ 1) << 1) | 0;
132 static inline unsigned
133 bir_src_index(nir_src
*src
)
136 return bir_ssa_index(src
->ssa
);
138 assert(!src
->reg
.indirect
);
139 return (src
->reg
.reg
->index
<< 1) | BIR_IS_REG
;
143 static inline unsigned
144 bir_dest_index(nir_dest
*dst
)
147 return bir_ssa_index(&dst
->ssa
);
149 assert(!dst
->reg
.indirect
);
150 return (dst
->reg
.reg
->index
<< 1) | BIR_IS_REG
;