2 * Copyright (C) 2019 Connor Abbott <cwabbott0@gmail.com>
3 * Copyright (C) 2019 Lyude Paul <thatslyude@gmail.com>
4 * Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include "bifrost_ops.h"
35 #include "disassemble.h"
36 #include "util/macros.h"
38 // return bits (high, lo]
39 static uint64_t bits(uint32_t word
, unsigned lo
, unsigned high
)
43 return (word
& ((1 << high
) - 1)) >> lo
;
46 // each of these structs represents an instruction that's dispatched in one
47 // cycle. Note that these instructions are packed in funny ways within the
48 // clause, hence the need for a separate struct.
49 struct bifrost_alu_inst
{
56 unsigned uniform_const
: 8;
64 static unsigned get_reg0(struct bifrost_regs regs
)
67 return regs
.reg0
| ((regs
.reg1
& 0x1) << 5);
69 return regs
.reg0
<= regs
.reg1
? regs
.reg0
: 63 - regs
.reg0
;
72 static unsigned get_reg1(struct bifrost_regs regs
)
74 return regs
.reg0
<= regs
.reg1
? regs
.reg1
: 63 - regs
.reg1
;
77 enum bifrost_reg_write_unit
{
78 REG_WRITE_NONE
= 0, // don't write
79 REG_WRITE_TWO
, // write using reg2
80 REG_WRITE_THREE
, // write using reg3
83 // this represents the decoded version of the ctrl register field.
84 struct bifrost_reg_ctrl
{
88 enum bifrost_reg_write_unit fma_write_unit
;
89 enum bifrost_reg_write_unit add_write_unit
;
115 enum fma_src_type src_type
;
130 ADD_TEX_COMPACT
, // texture instruction with embedded sampler
131 ADD_TEX
, // texture instruction with sampler/etc. in uniform port
142 enum add_src_type src_type
;
146 struct bifrost_tex_ctrl
{
147 unsigned sampler_index
: 4; // also used to signal indirects
148 unsigned tex_index
: 7;
149 bool no_merge_index
: 1; // whether to merge (direct) sampler & texture indices
150 bool filter
: 1; // use the usual filtering pipeline (0 for texelFetch & textureGather)
152 bool texel_offset
: 1; // *Offset()
155 unsigned tex_type
: 2; // 2D, 3D, Cube, Buffer
156 bool compute_lod
: 1; // 0 for *Lod()
157 bool not_supply_lod
: 1; // 0 for *Lod() or when a bias is applied
158 bool calc_gradients
: 1; // 0 for *Grad()
160 unsigned result_type
: 4; // integer, unsigned, float TODO: why is this 4 bits?
164 struct bifrost_dual_tex_ctrl
{
165 unsigned sampler_index0
: 2;
167 unsigned tex_index0
: 2;
168 unsigned sampler_index1
: 2;
169 unsigned tex_index1
: 2;
173 enum branch_bit_size
{
177 // For the above combinations of bitsize and location, an extra bit is
178 // encoded via comparing the sources. The only possible source of ambiguity
179 // would be if the sources were the same, but then the branch condition
180 // would be always true or always false anyways, so we can ignore it. But
181 // this no longer works when comparing the y component to the x component,
182 // since it's valid to compare the y component of a source against its own
183 // x component. Instead, the extra bit is encoded via an extra bitsize.
186 BR_SIZE_32_AND_16X
= 5,
187 BR_SIZE_32_AND_16Y
= 6,
188 // Used for comparisons with zero and always-true, see below. I think this
189 // only works for integer comparisons.
193 void dump_header(FILE *fp
, struct bifrost_header header
, bool verbose
);
194 void dump_instr(FILE *fp
, const struct bifrost_alu_inst
*instr
,
195 struct bifrost_regs next_regs
, uint64_t *consts
,
196 unsigned data_reg
, unsigned offset
, bool verbose
);
197 bool dump_clause(FILE *fp
, uint32_t *words
, unsigned *size
, unsigned offset
, bool verbose
);
199 void dump_header(FILE *fp
, struct bifrost_header header
, bool verbose
)
201 if (header
.clause_type
!= 0) {
202 fprintf(fp
, "id(%du) ", header
.scoreboard_index
);
205 if (header
.scoreboard_deps
!= 0) {
206 fprintf(fp
, "next-wait(");
208 for (unsigned i
= 0; i
< 8; i
++) {
209 if (header
.scoreboard_deps
& (1 << i
)) {
213 fprintf(fp
, "%d", i
);
220 if (header
.datareg_writebarrier
)
221 fprintf(fp
, "data-reg-barrier ");
223 if (!header
.no_end_of_shader
)
226 if (!header
.back_to_back
) {
228 if (header
.branch_cond
)
229 fprintf(fp
, "branch-cond ");
231 fprintf(fp
, "branch-uncond ");
234 if (header
.elide_writes
)
237 if (header
.suppress_inf
)
238 fprintf(fp
, "suppress-inf ");
239 if (header
.suppress_nan
)
240 fprintf(fp
, "suppress-nan ");
243 fprintf(fp
, "unk0 ");
245 fprintf(fp
, "unk1 ");
247 fprintf(fp
, "unk2 ");
249 fprintf(fp
, "unk3 ");
251 fprintf(fp
, "unk4 ");
256 fprintf(fp
, "# clause type %d, next clause type %d\n",
257 header
.clause_type
, header
.next_clause_type
);
261 static struct bifrost_reg_ctrl
DecodeRegCtrl(FILE *fp
, struct bifrost_regs regs
)
263 struct bifrost_reg_ctrl decoded
= {};
265 if (regs
.ctrl
== 0) {
266 ctrl
= regs
.reg1
>> 2;
267 decoded
.read_reg0
= !(regs
.reg1
& 0x2);
268 decoded
.read_reg1
= false;
271 decoded
.read_reg0
= decoded
.read_reg1
= true;
275 decoded
.fma_write_unit
= REG_WRITE_TWO
;
279 decoded
.fma_write_unit
= REG_WRITE_TWO
;
280 decoded
.read_reg3
= true;
283 decoded
.read_reg3
= true;
286 decoded
.add_write_unit
= REG_WRITE_TWO
;
289 decoded
.add_write_unit
= REG_WRITE_TWO
;
290 decoded
.read_reg3
= true;
293 decoded
.clause_start
= true;
296 decoded
.fma_write_unit
= REG_WRITE_TWO
;
297 decoded
.clause_start
= true;
302 decoded
.read_reg3
= true;
303 decoded
.clause_start
= true;
306 decoded
.add_write_unit
= REG_WRITE_TWO
;
307 decoded
.clause_start
= true;
312 decoded
.fma_write_unit
= REG_WRITE_THREE
;
313 decoded
.add_write_unit
= REG_WRITE_TWO
;
316 fprintf(fp
, "# unknown reg ctrl %d\n", ctrl
);
322 // Pass in the add_write_unit or fma_write_unit, and this returns which register
323 // the ADD/FMA units are writing to
324 static unsigned GetRegToWrite(enum bifrost_reg_write_unit unit
, struct bifrost_regs regs
)
329 case REG_WRITE_THREE
:
331 default: /* REG_WRITE_NONE */
337 static void dump_regs(FILE *fp
, struct bifrost_regs srcs
)
339 struct bifrost_reg_ctrl ctrl
= DecodeRegCtrl(fp
, srcs
);
342 fprintf(fp
, "port 0: R%d ", get_reg0(srcs
));
344 fprintf(fp
, "port 1: R%d ", get_reg1(srcs
));
346 if (ctrl
.fma_write_unit
== REG_WRITE_TWO
)
347 fprintf(fp
, "port 2: R%d (write FMA) ", srcs
.reg2
);
348 else if (ctrl
.add_write_unit
== REG_WRITE_TWO
)
349 fprintf(fp
, "port 2: R%d (write ADD) ", srcs
.reg2
);
351 if (ctrl
.fma_write_unit
== REG_WRITE_THREE
)
352 fprintf(fp
, "port 3: R%d (write FMA) ", srcs
.reg3
);
353 else if (ctrl
.add_write_unit
== REG_WRITE_THREE
)
354 fprintf(fp
, "port 3: R%d (write ADD) ", srcs
.reg3
);
355 else if (ctrl
.read_reg3
)
356 fprintf(fp
, "port 3: R%d (read) ", srcs
.reg3
);
358 if (srcs
.uniform_const
) {
359 if (srcs
.uniform_const
& 0x80) {
360 fprintf(fp
, "uniform: U%d", (srcs
.uniform_const
& 0x7f) * 2);
366 static void dump_const_imm(FILE *fp
, uint32_t imm
)
373 fprintf(fp
, "0x%08x /* %f */", imm
, fi
.f
);
376 static uint64_t get_const(uint64_t *consts
, struct bifrost_regs srcs
)
378 unsigned low_bits
= srcs
.uniform_const
& 0xf;
380 switch (srcs
.uniform_const
>> 4) {
403 return imm
| low_bits
;
406 static void dump_uniform_const_src(FILE *fp
, struct bifrost_regs srcs
, uint64_t *consts
, bool high32
)
408 if (srcs
.uniform_const
& 0x80) {
409 unsigned uniform
= (srcs
.uniform_const
& 0x7f) * 2;
410 fprintf(fp
, "U%d", uniform
+ (high32
? 1 : 0));
411 } else if (srcs
.uniform_const
>= 0x20) {
412 uint64_t imm
= get_const(consts
, srcs
);
414 dump_const_imm(fp
, imm
>> 32);
416 dump_const_imm(fp
, imm
);
418 switch (srcs
.uniform_const
) {
423 fprintf(fp
, "atest-data");
426 fprintf(fp
, "sample-ptr");
436 fprintf(fp
, "blend-descriptor%u", (unsigned) srcs
.uniform_const
- 8);
439 fprintf(fp
, "unkConst%u", (unsigned) srcs
.uniform_const
);
450 static void dump_src(FILE *fp
, unsigned src
, struct bifrost_regs srcs
, uint64_t *consts
, bool isFMA
)
454 fprintf(fp
, "R%d", get_reg0(srcs
));
457 fprintf(fp
, "R%d", get_reg1(srcs
));
460 fprintf(fp
, "R%d", srcs
.reg3
);
466 fprintf(fp
, "T"); // i.e. the output of FMA this cycle
469 dump_uniform_const_src(fp
, srcs
, consts
, false);
472 dump_uniform_const_src(fp
, srcs
, consts
, true);
483 static void dump_output_mod(FILE *fp
, unsigned mod
)
489 fprintf(fp
, ".clamp_0_inf");
490 break; // max(out, 0)
491 case BIFROST_SAT_SIGNED
:
492 fprintf(fp
, ".clamp_m1_1");
493 break; // clamp(out, -1, 1)
495 fprintf(fp
, ".clamp_0_1");
496 break; // clamp(out, 0, 1)
502 static void dump_minmax_mode(FILE *fp
, unsigned mod
)
506 /* Same as fmax() and fmin() -- return the other number if any
507 * number is NaN. Also always return +0 if one argument is +0 and
512 /* Instead of never returning a NaN, always return one. The
513 * "greater"/"lesser" NaN is always returned, first by checking the
514 * sign and then the mantissa bits.
516 fprintf(fp
, ".nan_wins");
519 /* For max, implement src0 > src1 ? src0 : src1
520 * For min, implement src0 < src1 ? src0 : src1
522 * This includes handling NaN's and signedness of 0 differently
523 * from above, since +0 and -0 compare equal and comparisons always
524 * return false for NaN's. As a result, this mode is *not*
527 fprintf(fp
, ".src1_wins");
530 /* For max, implement src0 < src1 ? src1 : src0
531 * For min, implement src0 > src1 ? src1 : src0
533 fprintf(fp
, ".src0_wins");
540 static void dump_round_mode(FILE *fp
, unsigned mod
)
544 /* roundTiesToEven, the IEEE default. */
547 /* roundTowardPositive in the IEEE spec. */
548 fprintf(fp
, ".round_pos");
551 /* roundTowardNegative in the IEEE spec. */
552 fprintf(fp
, ".round_neg");
555 /* roundTowardZero in the IEEE spec. */
556 fprintf(fp
, ".round_zero");
564 csel_cond_name(enum bifrost_csel_cond cond
)
567 case BIFROST_FEQ_F
: return "feq.f";
568 case BIFROST_FGT_F
: return "fgt.f";
569 case BIFROST_FGE_F
: return "fge.f";
570 case BIFROST_IEQ_F
: return "ieq.f";
571 case BIFROST_IGT_I
: return "igt.i";
572 case BIFROST_IGE_I
: return "uge.i";
573 case BIFROST_UGT_I
: return "ugt.i";
574 case BIFROST_UGE_I
: return "uge.i";
575 default: return "invalid";
579 static const struct fma_op_info FMAOpInfos
[] = {
580 { false, 0x00000, "FMA.f32", FMA_FMA
},
581 { false, 0x40000, "MAX.f32", FMA_FMINMAX
},
582 { false, 0x44000, "MIN.f32", FMA_FMINMAX
},
583 { false, 0x48000, "FCMP.GL", FMA_FCMP
},
584 { false, 0x4c000, "FCMP.D3D", FMA_FCMP
},
585 { false, 0x4ff98, "ADD.i32", FMA_TWO_SRC
},
586 { false, 0x4ffd8, "SUB.i32", FMA_TWO_SRC
},
587 { false, 0x4fff0, "SUBB.i32", FMA_TWO_SRC
},
588 { false, 0x50000, "FMA_MSCALE", FMA_FMA_MSCALE
},
589 { false, 0x58000, "ADD.f32", FMA_FADD
},
590 { false, 0x5c000, "CSEL4", FMA_CSEL4
},
591 { false, 0x5d8d0, "ICMP.D3D.GT.v2i16", FMA_TWO_SRC
},
592 { false, 0x5d9d0, "UCMP.D3D.GT.v2i16", FMA_TWO_SRC
},
593 { false, 0x5dad0, "ICMP.D3D.GE.v2i16", FMA_TWO_SRC
},
594 { false, 0x5dbd0, "UCMP.D3D.GE.v2i16", FMA_TWO_SRC
},
595 { false, 0x5dcd0, "ICMP.D3D.EQ.v2i16", FMA_TWO_SRC
},
596 { false, 0x5de40, "ICMP.GL.GT.i32", FMA_TWO_SRC
}, // src0 > src1 ? 1 : 0
597 { false, 0x5de48, "ICMP.GL.GE.i32", FMA_TWO_SRC
},
598 { false, 0x5de50, "UCMP.GL.GT.i32", FMA_TWO_SRC
},
599 { false, 0x5de58, "UCMP.GL.GE.i32", FMA_TWO_SRC
},
600 { false, 0x5de60, "ICMP.GL.EQ.i32", FMA_TWO_SRC
},
601 { false, 0x5dec0, "ICMP.D3D.GT.i32", FMA_TWO_SRC
}, // src0 > src1 ? ~0 : 0
602 { false, 0x5dec8, "ICMP.D3D.GE.i32", FMA_TWO_SRC
},
603 { false, 0x5ded0, "UCMP.D3D.GT.i32", FMA_TWO_SRC
},
604 { false, 0x5ded8, "UCMP.D3D.GE.i32", FMA_TWO_SRC
},
605 { false, 0x5dee0, "ICMP.D3D.EQ.i32", FMA_TWO_SRC
},
606 { false, 0x60000, "RSHIFT_NAND", FMA_SHIFT
},
607 { false, 0x61000, "RSHIFT_AND", FMA_SHIFT
},
608 { false, 0x62000, "LSHIFT_NAND", FMA_SHIFT
},
609 { false, 0x63000, "LSHIFT_AND", FMA_SHIFT
}, // (src0 << src2) & src1
610 { false, 0x64000, "RSHIFT_XOR", FMA_SHIFT
},
611 { false, 0x65200, "LSHIFT_ADD.i32", FMA_THREE_SRC
},
612 { false, 0x65600, "LSHIFT_SUB.i32", FMA_THREE_SRC
}, // (src0 << src2) - src1
613 { false, 0x65a00, "LSHIFT_RSUB.i32", FMA_THREE_SRC
}, // src1 - (src0 << src2)
614 { false, 0x65e00, "RSHIFT_ADD.i32", FMA_THREE_SRC
},
615 { false, 0x66200, "RSHIFT_SUB.i32", FMA_THREE_SRC
},
616 { false, 0x66600, "RSHIFT_RSUB.i32", FMA_THREE_SRC
},
617 { false, 0x66a00, "ARSHIFT_ADD.i32", FMA_THREE_SRC
},
618 { false, 0x66e00, "ARSHIFT_SUB.i32", FMA_THREE_SRC
},
619 { false, 0x67200, "ARSHIFT_RSUB.i32", FMA_THREE_SRC
},
620 { false, 0x80000, "FMA.v2f16", FMA_FMA16
},
621 { false, 0xc0000, "MAX.v2f16", FMA_FMINMAX16
},
622 { false, 0xc4000, "MIN.v2f16", FMA_FMINMAX16
},
623 { false, 0xc8000, "FCMP.GL", FMA_FCMP16
},
624 { false, 0xcc000, "FCMP.D3D", FMA_FCMP16
},
625 { false, 0xcf900, "ADD.v2i16", FMA_TWO_SRC
},
626 { false, 0xcfc10, "ADDC.i32", FMA_TWO_SRC
},
627 { false, 0xcfd80, "ADD.i32.i16.X", FMA_TWO_SRC
},
628 { false, 0xcfd90, "ADD.i32.u16.X", FMA_TWO_SRC
},
629 { false, 0xcfdc0, "ADD.i32.i16.Y", FMA_TWO_SRC
},
630 { false, 0xcfdd0, "ADD.i32.u16.Y", FMA_TWO_SRC
},
631 { false, 0xd8000, "ADD.v2f16", FMA_FADD16
},
632 { false, 0xdc000, "CSEL4.v16", FMA_CSEL4
},
633 { false, 0xdd000, "F32_TO_F16", FMA_TWO_SRC
},
634 { true, 0x00046, "F16_TO_I16.XX", FMA_ONE_SRC
},
635 { true, 0x00047, "F16_TO_U16.XX", FMA_ONE_SRC
},
636 { true, 0x0004e, "F16_TO_I16.YX", FMA_ONE_SRC
},
637 { true, 0x0004f, "F16_TO_U16.YX", FMA_ONE_SRC
},
638 { true, 0x00056, "F16_TO_I16.XY", FMA_ONE_SRC
},
639 { true, 0x00057, "F16_TO_U16.XY", FMA_ONE_SRC
},
640 { true, 0x0005e, "F16_TO_I16.YY", FMA_ONE_SRC
},
641 { true, 0x0005f, "F16_TO_U16.YY", FMA_ONE_SRC
},
642 { true, 0x000c0, "I16_TO_F16.XX", FMA_ONE_SRC
},
643 { true, 0x000c1, "U16_TO_F16.XX", FMA_ONE_SRC
},
644 { true, 0x000c8, "I16_TO_F16.YX", FMA_ONE_SRC
},
645 { true, 0x000c9, "U16_TO_F16.YX", FMA_ONE_SRC
},
646 { true, 0x000d0, "I16_TO_F16.XY", FMA_ONE_SRC
},
647 { true, 0x000d1, "U16_TO_F16.XY", FMA_ONE_SRC
},
648 { true, 0x000d8, "I16_TO_F16.YY", FMA_ONE_SRC
},
649 { true, 0x000d9, "U16_TO_F16.YY", FMA_ONE_SRC
},
650 { true, 0x00136, "F32_TO_I32", FMA_ONE_SRC
},
651 { true, 0x00137, "F32_TO_U32", FMA_ONE_SRC
},
652 { true, 0x00178, "I32_TO_F32", FMA_ONE_SRC
},
653 { true, 0x00179, "U32_TO_F32", FMA_ONE_SRC
},
654 { true, 0x00198, "I16_TO_I32.X", FMA_ONE_SRC
},
655 { true, 0x00199, "U16_TO_U32.X", FMA_ONE_SRC
},
656 { true, 0x0019a, "I16_TO_I32.Y", FMA_ONE_SRC
},
657 { true, 0x0019b, "U16_TO_U32.Y", FMA_ONE_SRC
},
658 { true, 0x0019c, "I16_TO_F32.X", FMA_ONE_SRC
},
659 { true, 0x0019d, "U16_TO_F32.X", FMA_ONE_SRC
},
660 { true, 0x0019e, "I16_TO_F32.Y", FMA_ONE_SRC
},
661 { true, 0x0019f, "U16_TO_F32.Y", FMA_ONE_SRC
},
662 { true, 0x001a2, "F16_TO_F32.X", FMA_ONE_SRC
},
663 { true, 0x001a3, "F16_TO_F32.Y", FMA_ONE_SRC
},
664 { true, 0x0032c, "NOP", FMA_ONE_SRC
},
665 { true, 0x0032d, "MOV", FMA_ONE_SRC
},
666 { true, 0x0032f, "SWZ.YY.v2i16", FMA_ONE_SRC
},
667 { true, 0x00345, "LOG_FREXPM", FMA_ONE_SRC
},
668 { true, 0x00365, "FRCP_FREXPM", FMA_ONE_SRC
},
669 { true, 0x00375, "FSQRT_FREXPM", FMA_ONE_SRC
},
670 { true, 0x0038d, "FRCP_FREXPE", FMA_ONE_SRC
},
671 { true, 0x003a5, "FSQRT_FREXPE", FMA_ONE_SRC
},
672 { true, 0x003ad, "FRSQ_FREXPE", FMA_ONE_SRC
},
673 { true, 0x003c5, "LOG_FREXPE", FMA_ONE_SRC
},
674 { true, 0x003fa, "CLZ", FMA_ONE_SRC
},
675 { true, 0x00b80, "IMAX3", FMA_THREE_SRC
},
676 { true, 0x00bc0, "UMAX3", FMA_THREE_SRC
},
677 { true, 0x00c00, "IMIN3", FMA_THREE_SRC
},
678 { true, 0x00c40, "UMIN3", FMA_THREE_SRC
},
679 { true, 0x00ec5, "ROUND", FMA_ONE_SRC
},
680 { true, 0x00f40, "CSEL", FMA_THREE_SRC
}, // src2 != 0 ? src1 : src0
681 { true, 0x00fc0, "MUX.i32", FMA_THREE_SRC
}, // see ADD comment
682 { true, 0x01805, "ROUNDEVEN", FMA_ONE_SRC
},
683 { true, 0x01845, "CEIL", FMA_ONE_SRC
},
684 { true, 0x01885, "FLOOR", FMA_ONE_SRC
},
685 { true, 0x018c5, "TRUNC", FMA_ONE_SRC
},
686 { true, 0x019b0, "ATAN_LDEXP.Y.f32", FMA_TWO_SRC
},
687 { true, 0x019b8, "ATAN_LDEXP.X.f32", FMA_TWO_SRC
},
688 { true, 0x01c80, "LSHIFT_ADD_LOW32.u32", FMA_SHIFT_ADD64
},
689 { true, 0x01cc0, "LSHIFT_ADD_LOW32.i64", FMA_SHIFT_ADD64
},
690 { true, 0x01d80, "LSHIFT_ADD_LOW32.i32", FMA_SHIFT_ADD64
},
691 { true, 0x01e00, "SEL.XX.i16", FMA_TWO_SRC
},
692 { true, 0x01e08, "SEL.YX.i16", FMA_TWO_SRC
},
693 { true, 0x01e10, "SEL.XY.i16", FMA_TWO_SRC
},
694 { true, 0x01e18, "SEL.YY.i16", FMA_TWO_SRC
},
695 { true, 0x00800, "IMAD", FMA_THREE_SRC
},
696 { true, 0x078db, "POPCNT", FMA_ONE_SRC
},
699 static struct fma_op_info
find_fma_op_info(unsigned op
, bool extended
)
701 for (unsigned i
= 0; i
< ARRAY_SIZE(FMAOpInfos
); i
++) {
704 if (FMAOpInfos
[i
].extended
!= extended
)
710 switch (FMAOpInfos
[i
].src_type
) {
719 opCmp
= op
& ~0x1fff;
722 case FMA_SHIFT_ADD64
:
729 opCmp
= op
& ~0x3fff;
733 opCmp
= op
& ~0x3ffff;
740 opCmp
= op
& ~0x7fff;
746 if (FMAOpInfos
[i
].op
== opCmp
)
747 return FMAOpInfos
[i
];
750 struct fma_op_info info
;
751 snprintf(info
.name
, sizeof(info
.name
), "op%04x", op
);
753 info
.src_type
= FMA_THREE_SRC
;
757 static void dump_fcmp(FILE *fp
, unsigned op
)
779 fprintf(fp
, ".unk%d", op
);
784 static void dump_16swizzle(FILE *fp
, unsigned swiz
)
788 fprintf(fp
, ".%c%c", "xy"[swiz
& 1], "xy"[(swiz
>> 1) & 1]);
791 static void dump_fma_expand_src0(FILE *fp
, unsigned ctrl
)
813 static void dump_fma_expand_src1(FILE *fp
, unsigned ctrl
)
836 bi_ldst_type_name(enum bifrost_ldst_type type
)
839 case BIFROST_LDST_F16
: return "f16";
840 case BIFROST_LDST_F32
: return "f32";
841 case BIFROST_LDST_I32
: return "i32";
842 case BIFROST_LDST_U32
: return "u32";
843 default: return "invalid";
847 static void dump_fma(FILE *fp
, uint64_t word
, struct bifrost_regs regs
, struct bifrost_regs next_regs
, uint64_t *consts
, bool verbose
)
850 fprintf(fp
, "# FMA: %016" PRIx64
"\n", word
);
852 struct bifrost_fma_inst FMA
;
853 memcpy((char *) &FMA
, (char *) &word
, sizeof(struct bifrost_fma_inst
));
854 struct fma_op_info info
= find_fma_op_info(FMA
.op
, (FMA
.op
& 0xe0000) == 0xe0000);
856 fprintf(fp
, "%s", info
.name
);
857 if (info
.src_type
== FMA_FADD
||
858 info
.src_type
== FMA_FMINMAX
||
859 info
.src_type
== FMA_FMA
||
860 info
.src_type
== FMA_FADD16
||
861 info
.src_type
== FMA_FMINMAX16
||
862 info
.src_type
== FMA_FMA16
) {
863 dump_output_mod(fp
, bits(FMA
.op
, 12, 14));
864 switch (info
.src_type
) {
869 dump_round_mode(fp
, bits(FMA
.op
, 10, 12));
873 dump_minmax_mode(fp
, bits(FMA
.op
, 10, 12));
878 } else if (info
.src_type
== FMA_FCMP
|| info
.src_type
== FMA_FCMP16
) {
879 dump_fcmp(fp
, bits(FMA
.op
, 10, 13));
880 if (info
.src_type
== FMA_FCMP
)
883 fprintf(fp
, ".v2f16");
884 } else if (info
.src_type
== FMA_FMA_MSCALE
) {
885 if (FMA
.op
& (1 << 11)) {
886 switch ((FMA
.op
>> 9) & 0x3) {
888 /* This mode seems to do a few things:
889 * - Makes 0 * infinity (and incidentally 0 * nan) return 0,
890 * since generating a nan would poison the result of
891 * 1/infinity and 1/0.
892 * - Fiddles with which nan is returned in nan * nan,
893 * presumably to make sure that the same exact nan is
894 * returned for 1/nan.
896 fprintf(fp
, ".rcp_mode");
899 /* Similar to the above, but src0 always wins when multiplying
902 fprintf(fp
, ".sqrt_mode");
905 fprintf(fp
, ".unk%d_mode", (int) (FMA
.op
>> 9) & 0x3);
908 dump_output_mod(fp
, bits(FMA
.op
, 9, 11));
910 } else if (info
.src_type
== FMA_SHIFT
) {
911 struct bifrost_shift_fma shift
;
912 memcpy(&shift
, &FMA
, sizeof(shift
));
914 if (shift
.half
== 0x7)
915 fprintf(fp
, ".v2i16");
916 else if (shift
.half
== 0)
918 else if (shift
.half
== 0x4)
919 fprintf(fp
, ".v4i8");
921 fprintf(fp
, ".unk%u", shift
.half
);
924 fprintf(fp
, ".no_unk");
927 fprintf(fp
, ".invert_1");
930 fprintf(fp
, ".invert_2");
935 struct bifrost_reg_ctrl next_ctrl
= DecodeRegCtrl(fp
, next_regs
);
936 if (next_ctrl
.fma_write_unit
!= REG_WRITE_NONE
) {
937 fprintf(fp
, "{R%d, T0}, ", GetRegToWrite(next_ctrl
.fma_write_unit
, next_regs
));
942 switch (info
.src_type
) {
944 dump_src(fp
, FMA
.src0
, regs
, consts
, true);
947 dump_src(fp
, FMA
.src0
, regs
, consts
, true);
949 dump_src(fp
, FMA
.op
& 0x7, regs
, consts
, true);
957 dump_src(fp
, FMA
.src0
, regs
, consts
, true);
958 dump_fma_expand_src0(fp
, (FMA
.op
>> 6) & 0x7);
966 dump_src(fp
, FMA
.op
& 0x7, regs
, consts
, true);
967 dump_fma_expand_src1(fp
, (FMA
.op
>> 6) & 0x7);
972 case FMA_FMINMAX16
: {
973 bool abs1
= FMA
.op
& 0x8;
974 bool abs2
= (FMA
.op
& 0x7) < FMA
.src0
;
979 dump_src(fp
, FMA
.src0
, regs
, consts
, true);
980 dump_16swizzle(fp
, (FMA
.op
>> 6) & 0x3);
988 dump_src(fp
, FMA
.op
& 0x7, regs
, consts
, true);
989 dump_16swizzle(fp
, (FMA
.op
>> 8) & 0x3);
997 dump_src(fp
, FMA
.src0
, regs
, consts
, true);
998 dump_fma_expand_src0(fp
, (FMA
.op
>> 6) & 0x7);
1005 fprintf(fp
, "abs(");
1006 dump_src(fp
, FMA
.op
& 0x7, regs
, consts
, true);
1007 dump_fma_expand_src1(fp
, (FMA
.op
>> 6) & 0x7);
1012 dump_src(fp
, FMA
.src0
, regs
, consts
, true);
1013 // Note: this is kinda a guess, I haven't seen the blob set this to
1014 // anything other than the identity, but it matches FMA_TWO_SRCFmod16
1015 dump_16swizzle(fp
, (FMA
.op
>> 6) & 0x3);
1017 dump_src(fp
, FMA
.op
& 0x7, regs
, consts
, true);
1018 dump_16swizzle(fp
, (FMA
.op
>> 8) & 0x3);
1020 case FMA_SHIFT_ADD64
:
1021 dump_src(fp
, FMA
.src0
, regs
, consts
, true);
1023 dump_src(fp
, FMA
.op
& 0x7, regs
, consts
, true);
1025 fprintf(fp
, "shift:%u", (FMA
.op
>> 3) & 0x7);
1028 dump_src(fp
, FMA
.src0
, regs
, consts
, true);
1030 dump_src(fp
, FMA
.op
& 0x7, regs
, consts
, true);
1032 dump_src(fp
, (FMA
.op
>> 3) & 0x7, regs
, consts
, true);
1035 struct bifrost_shift_fma shift
;
1036 memcpy(&shift
, &FMA
, sizeof(shift
));
1038 dump_src(fp
, shift
.src0
, regs
, consts
, true);
1040 dump_src(fp
, shift
.src1
, regs
, consts
, true);
1042 dump_src(fp
, shift
.src2
, regs
, consts
, true);
1046 if (FMA
.op
& (1 << 14))
1048 if (FMA
.op
& (1 << 9))
1049 fprintf(fp
, "abs(");
1050 dump_src(fp
, FMA
.src0
, regs
, consts
, true);
1051 dump_fma_expand_src0(fp
, (FMA
.op
>> 6) & 0x7);
1052 if (FMA
.op
& (1 << 9))
1055 if (FMA
.op
& (1 << 16))
1056 fprintf(fp
, "abs(");
1057 dump_src(fp
, FMA
.op
& 0x7, regs
, consts
, true);
1058 dump_fma_expand_src1(fp
, (FMA
.op
>> 6) & 0x7);
1059 if (FMA
.op
& (1 << 16))
1062 if (FMA
.op
& (1 << 15))
1064 if (FMA
.op
& (1 << 17))
1065 fprintf(fp
, "abs(");
1066 dump_src(fp
, (FMA
.op
>> 3) & 0x7, regs
, consts
, true);
1067 if (FMA
.op
& (1 << 17))
1071 if (FMA
.op
& (1 << 14))
1073 dump_src(fp
, FMA
.src0
, regs
, consts
, true);
1074 dump_16swizzle(fp
, (FMA
.op
>> 6) & 0x3);
1076 dump_src(fp
, FMA
.op
& 0x7, regs
, consts
, true);
1077 dump_16swizzle(fp
, (FMA
.op
>> 8) & 0x3);
1079 if (FMA
.op
& (1 << 15))
1081 dump_src(fp
, (FMA
.op
>> 3) & 0x7, regs
, consts
, true);
1082 dump_16swizzle(fp
, (FMA
.op
>> 16) & 0x3);
1085 struct bifrost_csel4 csel
;
1086 memcpy(&csel
, &FMA
, sizeof(csel
));
1087 fprintf(fp
, ".%s ", csel_cond_name(csel
.cond
));
1089 dump_src(fp
, csel
.src0
, regs
, consts
, true);
1091 dump_src(fp
, csel
.src1
, regs
, consts
, true);
1093 dump_src(fp
, csel
.src2
, regs
, consts
, true);
1095 dump_src(fp
, csel
.src3
, regs
, consts
, true);
1098 case FMA_FMA_MSCALE
:
1099 if (FMA
.op
& (1 << 12))
1100 fprintf(fp
, "abs(");
1101 dump_src(fp
, FMA
.src0
, regs
, consts
, true);
1102 if (FMA
.op
& (1 << 12))
1105 if (FMA
.op
& (1 << 13))
1107 dump_src(fp
, FMA
.op
& 0x7, regs
, consts
, true);
1109 if (FMA
.op
& (1 << 14))
1111 dump_src(fp
, (FMA
.op
>> 3) & 0x7, regs
, consts
, true);
1113 dump_src(fp
, (FMA
.op
>> 6) & 0x7, regs
, consts
, true);
1119 static const struct add_op_info add_op_infos
[] = {
1120 { 0x00000, "MAX.f32", ADD_FMINMAX
},
1121 { 0x02000, "MIN.f32", ADD_FMINMAX
},
1122 { 0x04000, "ADD.f32", ADD_FADD
},
1123 { 0x06000, "FCMP.GL", ADD_FCMP
},
1124 { 0x07000, "FCMP.D3D", ADD_FCMP
},
1125 { 0x07856, "F16_TO_I16", ADD_ONE_SRC
},
1126 { 0x07857, "F16_TO_U16", ADD_ONE_SRC
},
1127 { 0x078c0, "I16_TO_F16.XX", ADD_ONE_SRC
},
1128 { 0x078c1, "U16_TO_F16.XX", ADD_ONE_SRC
},
1129 { 0x078c8, "I16_TO_F16.YX", ADD_ONE_SRC
},
1130 { 0x078c9, "U16_TO_F16.YX", ADD_ONE_SRC
},
1131 { 0x078d0, "I16_TO_F16.XY", ADD_ONE_SRC
},
1132 { 0x078d1, "U16_TO_F16.XY", ADD_ONE_SRC
},
1133 { 0x078d8, "I16_TO_F16.YY", ADD_ONE_SRC
},
1134 { 0x078d9, "U16_TO_F16.YY", ADD_ONE_SRC
},
1135 { 0x07936, "F32_TO_I32", ADD_ONE_SRC
},
1136 { 0x07937, "F32_TO_U32", ADD_ONE_SRC
},
1137 { 0x07978, "I32_TO_F32", ADD_ONE_SRC
},
1138 { 0x07979, "U32_TO_F32", ADD_ONE_SRC
},
1139 { 0x07998, "I16_TO_I32.X", ADD_ONE_SRC
},
1140 { 0x07999, "U16_TO_U32.X", ADD_ONE_SRC
},
1141 { 0x0799a, "I16_TO_I32.Y", ADD_ONE_SRC
},
1142 { 0x0799b, "U16_TO_U32.Y", ADD_ONE_SRC
},
1143 { 0x0799c, "I16_TO_F32.X", ADD_ONE_SRC
},
1144 { 0x0799d, "U16_TO_F32.X", ADD_ONE_SRC
},
1145 { 0x0799e, "I16_TO_F32.Y", ADD_ONE_SRC
},
1146 { 0x0799f, "U16_TO_F32.Y", ADD_ONE_SRC
},
1147 { 0x079a2, "F16_TO_F32.X", ADD_ONE_SRC
},
1148 { 0x079a3, "F16_TO_F32.Y", ADD_ONE_SRC
},
1149 { 0x07b2b, "SWZ.YX.v2i16", ADD_ONE_SRC
},
1150 { 0x07b2c, "NOP", ADD_ONE_SRC
},
1151 { 0x07b29, "SWZ.XX.v2i16", ADD_ONE_SRC
},
1152 { 0x07b2d, "MOV", ADD_ONE_SRC
},
1153 { 0x07b2f, "SWZ.YY.v2i16", ADD_ONE_SRC
},
1154 { 0x07b65, "FRCP_FREXPM", ADD_ONE_SRC
},
1155 { 0x07b75, "FSQRT_FREXPM", ADD_ONE_SRC
},
1156 { 0x07b8d, "FRCP_FREXPE", ADD_ONE_SRC
},
1157 { 0x07ba5, "FSQRT_FREXPE", ADD_ONE_SRC
},
1158 { 0x07bad, "FRSQ_FREXPE", ADD_ONE_SRC
},
1159 { 0x07bc5, "FLOG_FREXPE", ADD_ONE_SRC
},
1160 { 0x07d45, "CEIL", ADD_ONE_SRC
},
1161 { 0x07d85, "FLOOR", ADD_ONE_SRC
},
1162 { 0x07dc5, "TRUNC", ADD_ONE_SRC
},
1163 { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC
},
1164 { 0x08000, "LD_ATTR", ADD_LOAD_ATTR
, true },
1165 { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP
, true },
1166 { 0x0b000, "TEX", ADD_TEX_COMPACT
, true },
1167 { 0x0c188, "LOAD.i32", ADD_TWO_SRC
, true },
1168 { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC
, true },
1169 { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC
, true },
1170 { 0x0c1c8, "LOAD.v2i32", ADD_TWO_SRC
, true },
1171 { 0x0c1e0, "LD_UBO.v2i32", ADD_TWO_SRC
, true },
1172 { 0x0c1f8, "LD_SCRATCH.v2i32", ADD_TWO_SRC
, true },
1173 { 0x0c208, "LOAD.v4i32", ADD_TWO_SRC
, true },
1174 { 0x0c220, "LD_UBO.v4i32", ADD_TWO_SRC
, true },
1175 { 0x0c238, "LD_SCRATCH.v4i32", ADD_TWO_SRC
, true },
1176 { 0x0c248, "STORE.v4i32", ADD_TWO_SRC
, true },
1177 { 0x0c278, "ST_SCRATCH.v4i32", ADD_TWO_SRC
, true },
1178 { 0x0c588, "STORE.i32", ADD_TWO_SRC
, true },
1179 { 0x0c5b8, "ST_SCRATCH.i32", ADD_TWO_SRC
, true },
1180 { 0x0c5c8, "STORE.v2i32", ADD_TWO_SRC
, true },
1181 { 0x0c5f8, "ST_SCRATCH.v2i32", ADD_TWO_SRC
, true },
1182 { 0x0c648, "LOAD.u16", ADD_TWO_SRC
, true }, // zero-extends
1183 { 0x0ca88, "LOAD.v3i32", ADD_TWO_SRC
, true },
1184 { 0x0caa0, "LD_UBO.v3i32", ADD_TWO_SRC
, true },
1185 { 0x0cab8, "LD_SCRATCH.v3i32", ADD_TWO_SRC
, true },
1186 { 0x0cb88, "STORE.v3i32", ADD_TWO_SRC
, true },
1187 { 0x0cbb8, "ST_SCRATCH.v3i32", ADD_TWO_SRC
, true },
1188 { 0x0cc00, "FRCP_FAST.f32", ADD_ONE_SRC
},
1189 { 0x0cc20, "FRSQ_FAST.f32", ADD_ONE_SRC
},
1190 { 0x0ce00, "FRCP_TABLE", ADD_ONE_SRC
},
1191 { 0x0ce10, "FRCP_FAST.f16.X", ADD_ONE_SRC
},
1192 { 0x0ce20, "FRSQ_TABLE", ADD_ONE_SRC
},
1193 { 0x0ce30, "FRCP_FAST.f16.Y", ADD_ONE_SRC
},
1194 { 0x0ce50, "FRSQ_FAST.f16.X", ADD_ONE_SRC
},
1195 { 0x0ce60, "FRCP_APPROX", ADD_ONE_SRC
},
1196 { 0x0ce70, "FRSQ_FAST.f16.Y", ADD_ONE_SRC
},
1197 { 0x0cf40, "ATAN_ASSIST", ADD_TWO_SRC
},
1198 { 0x0cf48, "ATAN_TABLE", ADD_TWO_SRC
},
1199 { 0x0cf50, "SIN_TABLE", ADD_ONE_SRC
},
1200 { 0x0cf51, "COS_TABLE", ADD_ONE_SRC
},
1201 { 0x0cf58, "EXP_TABLE", ADD_ONE_SRC
},
1202 { 0x0cf60, "FLOG2_TABLE", ADD_ONE_SRC
},
1203 { 0x0cf64, "FLOGE_TABLE", ADD_ONE_SRC
},
1204 { 0x0d000, "BRANCH", ADD_BRANCH
},
1205 { 0x0e8c0, "MUX", ADD_THREE_SRC
},
1206 { 0x0e9b0, "ATAN_LDEXP.Y.f32", ADD_TWO_SRC
},
1207 { 0x0e9b8, "ATAN_LDEXP.X.f32", ADD_TWO_SRC
},
1208 { 0x0ea60, "SEL.XX.i16", ADD_TWO_SRC
},
1209 { 0x0ea70, "SEL.XY.i16", ADD_TWO_SRC
},
1210 { 0x0ea68, "SEL.YX.i16", ADD_TWO_SRC
},
1211 { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC
},
1212 { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC
},
1213 { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC
}, // src0 > src1 ? 1 : 0
1214 { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC
},
1215 { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC
},
1216 { 0x0f658, "UCMP.GL.GE", ADD_TWO_SRC
},
1217 { 0x0f660, "ICMP.GL.EQ", ADD_TWO_SRC
},
1218 { 0x0f669, "ICMP.GL.NEQ", ADD_TWO_SRC
},
1219 { 0x0f6c0, "ICMP.D3D.GT", ADD_TWO_SRC
}, // src0 > src1 ? ~0 : 0
1220 { 0x0f6c8, "ICMP.D3D.GE", ADD_TWO_SRC
},
1221 { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC
},
1222 { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC
},
1223 { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC
},
1224 { 0x10000, "MAX.v2f16", ADD_FMINMAX16
},
1225 { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale
},
1226 { 0x12000, "MIN.v2f16", ADD_FMINMAX16
},
1227 { 0x14000, "ADD.v2f16", ADD_FADD16
},
1228 { 0x17000, "FCMP.D3D", ADD_FCMP16
},
1229 { 0x178c0, "ADD.i32", ADD_TWO_SRC
},
1230 { 0x17900, "ADD.v2i16", ADD_TWO_SRC
},
1231 { 0x17ac0, "SUB.i32", ADD_TWO_SRC
},
1232 { 0x17c10, "ADDC.i32", ADD_TWO_SRC
}, // adds src0 to the bottom bit of src1
1233 { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC
},
1234 { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC
},
1235 { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC
},
1236 { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC
},
1237 { 0x18000, "LD_VAR_ADDR", ADD_VARYING_ADDRESS
, true },
1238 { 0x19181, "DISCARD.FEQ.f32", ADD_TWO_SRC
, true },
1239 { 0x19189, "DISCARD.FNE.f32", ADD_TWO_SRC
, true },
1240 { 0x1918C, "DISCARD.GL.f32", ADD_TWO_SRC
, true }, /* Consumes ICMP.GL/etc with fixed 0 argument */
1241 { 0x19190, "DISCARD.FLE.f32", ADD_TWO_SRC
, true },
1242 { 0x19198, "DISCARD.FLT.f32", ADD_TWO_SRC
, true },
1243 { 0x191e8, "ATEST.f32", ADD_TWO_SRC
, true },
1244 { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC
, true },
1245 { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC
, true },
1246 { 0x19300, "ST_VAR.v1", ADD_THREE_SRC
, true },
1247 { 0x19340, "ST_VAR.v2", ADD_THREE_SRC
, true },
1248 { 0x19380, "ST_VAR.v3", ADD_THREE_SRC
, true },
1249 { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC
, true },
1250 { 0x1952c, "BLEND", ADD_BLENDING
, true },
1251 { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP
, true },
1252 { 0x1ae60, "TEX", ADD_TEX
, true },
1253 { 0x1c000, "RSHIFT_NAND.i32", ADD_SHIFT
},
1254 { 0x1c400, "RSHIFT_AND.i32", ADD_SHIFT
},
1255 { 0x1c800, "LSHIFT_NAND.i32", ADD_SHIFT
},
1256 { 0x1cc00, "LSHIFT_AND.i32", ADD_SHIFT
},
1257 { 0x1d000, "RSHIFT_XOR.i32", ADD_SHIFT
},
1258 { 0x1d400, "LSHIFT_ADD.i32", ADD_SHIFT
},
1259 { 0x1d800, "RSHIFT_SUB.i32", ADD_SHIFT
},
1260 { 0x1dd18, "OR.i32", ADD_TWO_SRC
},
1261 { 0x1dd20, "AND.i32", ADD_TWO_SRC
},
1262 { 0x1dd60, "LSHIFT.i32", ADD_TWO_SRC
},
1263 { 0x1dd50, "XOR.i32", ADD_TWO_SRC
},
1264 { 0x1dd80, "RSHIFT.i32", ADD_TWO_SRC
},
1265 { 0x1dda0, "ARSHIFT.i32", ADD_TWO_SRC
},
1268 static struct add_op_info
find_add_op_info(unsigned op
)
1270 for (unsigned i
= 0; i
< ARRAY_SIZE(add_op_infos
); i
++) {
1271 unsigned opCmp
= ~0;
1272 switch (add_op_infos
[i
].src_type
) {
1284 opCmp
= op
& ~0x3ff;
1292 opCmp
= op
& ~0x1fff;
1295 case ADD_FADDMscale
:
1296 opCmp
= op
& ~0xfff;
1300 opCmp
= op
& ~0x7ff;
1302 case ADD_TEX_COMPACT
:
1303 opCmp
= op
& ~0x3ff;
1305 case ADD_VARYING_INTERP
:
1306 opCmp
= op
& ~0x7ff;
1308 case ADD_VARYING_ADDRESS
:
1309 opCmp
= op
& ~0xfff;
1313 opCmp
= op
& ~0xfff;
1319 if (add_op_infos
[i
].op
== opCmp
)
1320 return add_op_infos
[i
];
1323 struct add_op_info info
;
1324 snprintf(info
.name
, sizeof(info
.name
), "op%04x", op
);
1326 info
.src_type
= ADD_TWO_SRC
;
1327 info
.has_data_reg
= true;
1331 static void dump_add(FILE *fp
, uint64_t word
, struct bifrost_regs regs
,
1332 struct bifrost_regs next_regs
, uint64_t *consts
,
1333 unsigned data_reg
, unsigned offset
, bool verbose
)
1336 fprintf(fp
, "# ADD: %016" PRIx64
"\n", word
);
1338 struct bifrost_add_inst ADD
;
1339 memcpy((char *) &ADD
, (char *) &word
, sizeof(ADD
));
1340 struct add_op_info info
= find_add_op_info(ADD
.op
);
1342 fprintf(fp
, "%s", info
.name
);
1344 // float16 seems like it doesn't support output modifiers
1345 if (info
.src_type
== ADD_FADD
|| info
.src_type
== ADD_FMINMAX
) {
1347 dump_output_mod(fp
, bits(ADD
.op
, 8, 10));
1348 if (info
.src_type
== ADD_FADD
)
1349 dump_round_mode(fp
, bits(ADD
.op
, 10, 12));
1351 dump_minmax_mode(fp
, bits(ADD
.op
, 10, 12));
1352 } else if (info
.src_type
== ADD_FCMP
|| info
.src_type
== ADD_FCMP16
) {
1353 dump_fcmp(fp
, bits(ADD
.op
, 3, 6));
1354 if (info
.src_type
== ADD_FCMP
)
1355 fprintf(fp
, ".f32");
1357 fprintf(fp
, ".v2f16");
1358 } else if (info
.src_type
== ADD_FADDMscale
) {
1359 switch ((ADD
.op
>> 6) & 0x7) {
1362 // causes GPU hangs on G71
1364 fprintf(fp
, ".invalid");
1366 // Same as usual outmod value.
1368 fprintf(fp
, ".clamp_0_1");
1370 // If src0 is infinite or NaN, flush it to zero so that the other
1371 // source is passed through unmodified.
1373 fprintf(fp
, ".flush_src0_inf_nan");
1377 fprintf(fp
, ".flush_src1_inf_nan");
1379 // Every other case seems to behave the same as the above?
1381 fprintf(fp
, ".unk%d", (ADD
.op
>> 6) & 0x7);
1384 } else if (info
.src_type
== ADD_VARYING_INTERP
) {
1386 fprintf(fp
, ".reuse");
1388 fprintf(fp
, ".flat");
1389 switch ((ADD
.op
>> 7) & 0x3) {
1391 fprintf(fp
, ".per_frag");
1394 fprintf(fp
, ".centroid");
1399 fprintf(fp
, ".explicit");
1402 fprintf(fp
, ".v%d", ((ADD
.op
>> 5) & 0x3) + 1);
1403 } else if (info
.src_type
== ADD_BRANCH
) {
1404 enum branch_code branchCode
= (enum branch_code
) ((ADD
.op
>> 6) & 0x3f);
1405 if (branchCode
== BR_ALWAYS
) {
1406 // unconditional branch
1408 enum branch_cond cond
= (enum branch_cond
) ((ADD
.op
>> 6) & 0x7);
1409 enum branch_bit_size size
= (enum branch_bit_size
) ((ADD
.op
>> 9) & 0x7);
1410 bool portSwapped
= (ADD
.op
& 0x7) < ADD
.src0
;
1411 // See the comment in branch_bit_size
1412 if (size
== BR_SIZE_16YX0
)
1414 if (size
== BR_SIZE_16YX1
)
1415 portSwapped
= false;
1416 // These sizes are only for floating point comparisons, so the
1417 // non-floating-point comparisons are reused to encode the flipped
1419 if (size
== BR_SIZE_32_AND_16X
|| size
== BR_SIZE_32_AND_16Y
)
1420 portSwapped
= false;
1421 // There's only one argument, so we reuse the extra argument to
1423 if (size
== BR_SIZE_ZERO
)
1424 portSwapped
= !(ADD
.op
& 1);
1429 fprintf(fp
, ".LT.u");
1431 fprintf(fp
, ".LT.i");
1434 if (size
== BR_SIZE_32_AND_16X
|| size
== BR_SIZE_32_AND_16Y
) {
1435 fprintf(fp
, ".UNE.f");
1438 fprintf(fp
, ".LE.u");
1440 fprintf(fp
, ".LE.i");
1445 fprintf(fp
, ".GT.u");
1447 fprintf(fp
, ".GT.i");
1451 fprintf(fp
, ".GE.u");
1453 fprintf(fp
, ".GE.i");
1457 fprintf(fp
, ".NE.i");
1459 fprintf(fp
, ".EQ.i");
1463 fprintf(fp
, ".UNE.f");
1465 fprintf(fp
, ".OEQ.f");
1469 fprintf(fp
, ".OGT.unk.f");
1471 fprintf(fp
, ".OGT.f");
1475 fprintf(fp
, ".OLT.unk.f");
1477 fprintf(fp
, ".OLT.f");
1482 case BR_SIZE_32_AND_16X
:
1483 case BR_SIZE_32_AND_16Y
:
1492 case BR_SIZE_ZERO
: {
1493 unsigned ctrl
= (ADD
.op
>> 1) & 0x3;
1495 fprintf(fp
, "32.Z");
1497 fprintf(fp
, "16.Z");
1502 } else if (info
.src_type
== ADD_SHIFT
) {
1503 struct bifrost_shift_add shift
;
1504 memcpy(&shift
, &ADD
, sizeof(ADD
));
1507 fprintf(fp
, ".invert_1");
1510 fprintf(fp
, ".invert_2");
1513 fprintf(fp
, ".unk%u", shift
.zero
);
1514 } else if (info
.src_type
== ADD_VARYING_ADDRESS
) {
1515 struct bifrost_ld_var_addr ld
;
1516 memcpy(&ld
, &ADD
, sizeof(ADD
));
1517 fprintf(fp
, ".%s", bi_ldst_type_name(ld
.type
));
1518 } else if (info
.src_type
== ADD_LOAD_ATTR
) {
1519 struct bifrost_ld_attr ld
;
1520 memcpy(&ld
, &ADD
, sizeof(ADD
));
1523 fprintf(fp
, ".v%d%s", ld
.channels
+ 1, bi_ldst_type_name(ld
.type
));
1525 fprintf(fp
, ".%s", bi_ldst_type_name(ld
.type
));
1530 struct bifrost_reg_ctrl next_ctrl
= DecodeRegCtrl(fp
, next_regs
);
1531 if (next_ctrl
.add_write_unit
!= REG_WRITE_NONE
) {
1532 fprintf(fp
, "{R%d, T1}, ", GetRegToWrite(next_ctrl
.add_write_unit
, next_regs
));
1534 fprintf(fp
, "T1, ");
1537 switch (info
.src_type
) {
1539 // Note: in this case, regs.uniform_const == location | 0x8
1540 // This probably means we can't load uniforms or immediates in the
1541 // same instruction. This re-uses the encoding that normally means
1542 // "disabled", where the low 4 bits are ignored. Perhaps the extra
1543 // 0x8 or'd in indicates this is happening.
1544 fprintf(fp
, "location:%d, ", regs
.uniform_const
& 0x7);
1547 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1550 case ADD_TEX_COMPACT
: {
1553 bool dualTex
= false;
1554 if (info
.src_type
== ADD_TEX_COMPACT
) {
1555 tex_index
= (ADD
.op
>> 3) & 0x7;
1556 sampler_index
= (ADD
.op
>> 7) & 0x7;
1557 bool unknown
= (ADD
.op
& 0x40);
1558 // TODO: figure out if the unknown bit is ever 0
1560 fprintf(fp
, "unknown ");
1562 uint64_t constVal
= get_const(consts
, regs
);
1563 uint32_t controlBits
= (ADD
.op
& 0x8) ? (constVal
>> 32) : constVal
;
1564 struct bifrost_tex_ctrl ctrl
;
1565 memcpy((char *) &ctrl
, (char *) &controlBits
, sizeof(ctrl
));
1567 // TODO: figure out what actually triggers dual-tex
1568 if (ctrl
.result_type
== 9) {
1569 struct bifrost_dual_tex_ctrl dualCtrl
;
1570 memcpy((char *) &dualCtrl
, (char *) &controlBits
, sizeof(ctrl
));
1571 fprintf(fp
, "(dualtex) tex0:%d samp0:%d tex1:%d samp1:%d ",
1572 dualCtrl
.tex_index0
, dualCtrl
.sampler_index0
,
1573 dualCtrl
.tex_index1
, dualCtrl
.sampler_index1
);
1574 if (dualCtrl
.unk0
!= 3)
1575 fprintf(fp
, "unk:%d ", dualCtrl
.unk0
);
1578 if (ctrl
.no_merge_index
) {
1579 tex_index
= ctrl
.tex_index
;
1580 sampler_index
= ctrl
.sampler_index
;
1582 tex_index
= sampler_index
= ctrl
.tex_index
;
1583 unsigned unk
= ctrl
.sampler_index
>> 2;
1585 fprintf(fp
, "unk:%d ", unk
);
1586 if (ctrl
.sampler_index
& 1)
1588 if (ctrl
.sampler_index
& 2)
1593 fprintf(fp
, "unk0:%d ", ctrl
.unk0
);
1595 fprintf(fp
, "unk1 ");
1596 if (ctrl
.unk2
!= 0xf)
1597 fprintf(fp
, "unk2:%x ", ctrl
.unk2
);
1599 switch (ctrl
.result_type
) {
1601 fprintf(fp
, "f32 ");
1604 fprintf(fp
, "i32 ");
1607 fprintf(fp
, "u32 ");
1610 fprintf(fp
, "unktype(%x) ", ctrl
.result_type
);
1613 switch (ctrl
.tex_type
) {
1615 fprintf(fp
, "cube ");
1618 fprintf(fp
, "buffer ");
1629 fprintf(fp
, "shadow ");
1631 fprintf(fp
, "array ");
1634 if (ctrl
.calc_gradients
) {
1635 int comp
= (controlBits
>> 20) & 0x3;
1636 fprintf(fp
, "txg comp:%d ", comp
);
1638 fprintf(fp
, "txf ");
1641 if (!ctrl
.not_supply_lod
) {
1642 if (ctrl
.compute_lod
)
1643 fprintf(fp
, "lod_bias ");
1645 fprintf(fp
, "lod ");
1648 if (!ctrl
.calc_gradients
)
1649 fprintf(fp
, "grad ");
1652 if (ctrl
.texel_offset
)
1653 fprintf(fp
, "offset ");
1658 if (tex_index
== -1)
1659 fprintf(fp
, "tex:indirect ");
1661 fprintf(fp
, "tex:%d ", tex_index
);
1663 if (sampler_index
== -1)
1664 fprintf(fp
, "samp:indirect ");
1666 fprintf(fp
, "samp:%d ", sampler_index
);
1670 case ADD_VARYING_INTERP
: {
1671 unsigned addr
= ADD
.op
& 0x1f;
1672 if (addr
< 0b10100) {
1674 fprintf(fp
, "%d", addr
);
1675 } else if (addr
< 0b11000) {
1677 fprintf(fp
, "fragw");
1678 else if (addr
== 23)
1679 fprintf(fp
, "fragz");
1681 fprintf(fp
, "unk%d", addr
);
1683 dump_src(fp
, ADD
.op
& 0x7, regs
, consts
, false);
1686 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1689 case ADD_VARYING_ADDRESS
: {
1690 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1692 dump_src(fp
, ADD
.op
& 0x7, regs
, consts
, false);
1694 unsigned location
= (ADD
.op
>> 3) & 0x1f;
1695 if (location
< 16) {
1696 fprintf(fp
, "location:%d", location
);
1697 } else if (location
== 20) {
1698 fprintf(fp
, "location:%u", (uint32_t) get_const(consts
, regs
));
1699 } else if (location
== 21) {
1700 fprintf(fp
, "location:%u", (uint32_t) (get_const(consts
, regs
) >> 32));
1702 fprintf(fp
, "location:%d(unk)", location
);
1707 fprintf(fp
, "location:%d, ", (ADD
.op
>> 3) & 0x1f);
1709 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1711 dump_src(fp
, ADD
.op
& 0x7, regs
, consts
, false);
1714 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1716 dump_src(fp
, ADD
.op
& 0x7, regs
, consts
, false);
1718 dump_src(fp
, (ADD
.op
>> 3) & 0x7, regs
, consts
, false);
1721 struct bifrost_shift_add shift
;
1722 memcpy(&shift
, &ADD
, sizeof(ADD
));
1723 dump_src(fp
, shift
.src0
, regs
, consts
, false);
1725 dump_src(fp
, shift
.src1
, regs
, consts
, false);
1727 dump_src(fp
, shift
.src2
, regs
, consts
, false);
1734 if (ADD
.op
& 0x1000)
1735 fprintf(fp
, "abs(");
1736 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1737 switch ((ADD
.op
>> 6) & 0x3) {
1744 if (ADD
.op
& 0x1000)
1750 fprintf(fp
, "abs(");
1751 dump_src(fp
, ADD
.op
& 0x7, regs
, consts
, false);
1752 switch ((ADD
.op
>> 6) & 0x3) {
1763 fprintf(fp
, ".unk");
1772 if (ADD
.op
& 0x1000)
1773 fprintf(fp
, "abs(");
1774 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1775 if (ADD
.op
& 0x1000)
1777 dump_16swizzle(fp
, (ADD
.op
>> 6) & 0x3);
1782 fprintf(fp
, "abs(");
1783 dump_src(fp
, ADD
.op
& 0x7, regs
, consts
, false);
1784 dump_16swizzle(fp
, (ADD
.op
>> 8) & 0x3);
1788 case ADD_FMINMAX16
: {
1789 bool abs1
= ADD
.op
& 0x8;
1790 bool abs2
= (ADD
.op
& 0x7) < ADD
.src0
;
1794 fprintf(fp
, "abs(");
1795 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1796 dump_16swizzle(fp
, (ADD
.op
>> 6) & 0x3);
1803 fprintf(fp
, "abs(");
1804 dump_src(fp
, ADD
.op
& 0x7, regs
, consts
, false);
1805 dump_16swizzle(fp
, (ADD
.op
>> 8) & 0x3);
1810 case ADD_FADDMscale
: {
1814 fprintf(fp
, "abs(");
1815 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1823 dump_src(fp
, ADD
.op
& 0x7, regs
, consts
, false);
1827 dump_src(fp
, (ADD
.op
>> 3) & 0x7, regs
, consts
, false);
1831 if (ADD
.op
& 0x400) {
1834 if (ADD
.op
& 0x100) {
1835 fprintf(fp
, "abs(");
1837 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1838 switch ((ADD
.op
>> 6) & 0x3) {
1845 if (ADD
.op
& 0x100) {
1849 if (ADD
.op
& 0x200) {
1850 fprintf(fp
, "abs(");
1852 dump_src(fp
, ADD
.op
& 0x7, regs
, consts
, false);
1853 switch ((ADD
.op
>> 6) & 0x3) {
1864 fprintf(fp
, ".unk");
1867 if (ADD
.op
& 0x200) {
1872 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1873 dump_16swizzle(fp
, (ADD
.op
>> 6) & 0x3);
1875 dump_src(fp
, ADD
.op
& 0x7, regs
, consts
, false);
1876 dump_16swizzle(fp
, (ADD
.op
>> 8) & 0x3);
1879 enum branch_code code
= (enum branch_code
) ((ADD
.op
>> 6) & 0x3f);
1880 enum branch_bit_size size
= (enum branch_bit_size
) ((ADD
.op
>> 9) & 0x7);
1881 if (code
!= BR_ALWAYS
) {
1882 dump_src(fp
, ADD
.src0
, regs
, consts
, false);
1892 case BR_SIZE_ZERO
: {
1893 unsigned ctrl
= (ADD
.op
>> 1) & 0x3;
1910 if (code
!= BR_ALWAYS
&& size
!= BR_SIZE_ZERO
) {
1911 dump_src(fp
, ADD
.op
& 0x7, regs
, consts
, false);
1916 case BR_SIZE_32_AND_16X
:
1920 case BR_SIZE_32_AND_16Y
:
1928 // I haven't had the chance to test if this actually specifies the
1929 // branch offset, since I couldn't get it to produce values other
1930 // than 5 (uniform/const high), but these three bits are always
1931 // consistent across branch instructions, so it makes sense...
1932 int offsetSrc
= (ADD
.op
>> 3) & 0x7;
1933 if (offsetSrc
== 4 || offsetSrc
== 5) {
1934 // If the offset is known/constant, we can decode it
1935 uint32_t raw_offset
;
1937 raw_offset
= get_const(consts
, regs
);
1939 raw_offset
= get_const(consts
, regs
) >> 32;
1940 // The high 4 bits are flags, while the rest is the
1941 // twos-complement offset in bytes (here we convert to
1943 int32_t branch_offset
= ((int32_t) raw_offset
<< 4) >> 8;
1945 // If high4 is the high 4 bits of the last 64-bit constant,
1946 // this is calculated as (high4 + 4) & 0xf, or 0 if the branch
1947 // offset itself is the last constant. Not sure if this is
1948 // actually used, or just garbage in unused bits, but in any
1949 // case, we can just ignore it here since it's redundant. Note
1950 // that if there is any padding, this will be 4 since the
1951 // padding counts as the last constant.
1952 unsigned flags
= raw_offset
>> 28;
1955 // Note: the offset is in bytes, relative to the beginning of the
1956 // current clause, so a zero offset would be a loop back to the
1957 // same clause (annoyingly different from Midgard).
1958 fprintf(fp
, "clause_%d", offset
+ branch_offset
);
1960 dump_src(fp
, offsetSrc
, regs
, consts
, false);
1964 if (info
.has_data_reg
) {
1965 fprintf(fp
, ", R%d", data_reg
);
1970 void dump_instr(FILE *fp
, const struct bifrost_alu_inst
*instr
,
1971 struct bifrost_regs next_regs
, uint64_t *consts
,
1972 unsigned data_reg
, unsigned offset
, bool verbose
)
1974 struct bifrost_regs regs
;
1975 memcpy((char *) ®s
, (char *) &instr
->reg_bits
, sizeof(regs
));
1978 fprintf(fp
, "# regs: %016" PRIx64
"\n", instr
->reg_bits
);
1979 dump_regs(fp
, regs
);
1981 dump_fma(fp
, instr
->fma_bits
, regs
, next_regs
, consts
, verbose
);
1982 dump_add(fp
, instr
->add_bits
, regs
, next_regs
, consts
, data_reg
, offset
, verbose
);
1985 bool dump_clause(FILE *fp
, uint32_t *words
, unsigned *size
, unsigned offset
, bool verbose
)
1987 // State for a decoded clause
1988 struct bifrost_alu_inst instrs
[8] = {};
1989 uint64_t consts
[6] = {};
1990 unsigned num_instrs
= 0;
1991 unsigned num_consts
= 0;
1992 uint64_t header_bits
= 0;
1993 bool stopbit
= false;
1996 for (i
= 0; ; i
++, words
+= 4) {
1999 for (int j
= 0; j
< 4; j
++)
2000 fprintf(fp
, "%08x ", words
[3 - j
]); // low bit on the right
2003 unsigned tag
= bits(words
[0], 0, 8);
2005 // speculatively decode some things that are common between many formats, so we can share some code
2006 struct bifrost_alu_inst main_instr
= {};
2008 main_instr
.add_bits
= bits(words
[2], 2, 32 - 13);
2010 main_instr
.fma_bits
= bits(words
[1], 11, 32) | bits(words
[2], 0, 2) << (32 - 11);
2012 main_instr
.reg_bits
= ((uint64_t) bits(words
[1], 0, 11)) << 24 | (uint64_t) bits(words
[0], 8, 32);
2014 uint64_t const0
= bits(words
[0], 8, 32) << 4 | (uint64_t) words
[1] << 28 | bits(words
[2], 0, 4) << 60;
2015 uint64_t const1
= bits(words
[2], 4, 32) << 4 | (uint64_t) words
[3] << 32;
2017 bool stop
= tag
& 0x40;
2020 fprintf(fp
, "# tag: 0x%02x\n", tag
);
2023 unsigned idx
= stop
? 5 : 2;
2024 main_instr
.add_bits
|= ((tag
>> 3) & 0x7) << 17;
2025 instrs
[idx
+ 1] = main_instr
;
2026 instrs
[idx
].add_bits
= bits(words
[3], 0, 17) | ((tag
& 0x7) << 17);
2027 instrs
[idx
].fma_bits
|= bits(words
[2], 19, 32) << 10;
2028 consts
[0] = bits(words
[3], 17, 32) << 4;
2031 switch ((tag
>> 3) & 0x7) {
2033 switch (tag
& 0x7) {
2035 main_instr
.add_bits
|= bits(words
[3], 29, 32) << 17;
2036 instrs
[1] = main_instr
;
2041 instrs
[2].add_bits
= bits(words
[3], 0, 17) | bits(words
[3], 29, 32) << 17;
2042 instrs
[2].fma_bits
|= bits(words
[2], 19, 32) << 10;
2050 instrs
[2].add_bits
= bits(words
[3], 0, 17) | bits(words
[3], 29, 32) << 17;
2051 instrs
[2].fma_bits
|= bits(words
[2], 19, 32) << 10;
2052 main_instr
.add_bits
|= bits(words
[3], 26, 29) << 17;
2053 instrs
[3] = main_instr
;
2054 if ((tag
& 0x7) == 0x5) {
2060 instrs
[5].add_bits
= bits(words
[3], 0, 17) | bits(words
[3], 29, 32) << 17;
2061 instrs
[5].fma_bits
|= bits(words
[2], 19, 32) << 10;
2068 instrs
[5].add_bits
= bits(words
[3], 0, 17) | bits(words
[3], 29, 32) << 17;
2069 instrs
[5].fma_bits
|= bits(words
[2], 19, 32) << 10;
2070 main_instr
.add_bits
|= bits(words
[3], 26, 29) << 17;
2071 instrs
[6] = main_instr
;
2076 fprintf(fp
, "unknown tag bits 0x%02x\n", tag
);
2081 unsigned idx
= ((tag
>> 3) & 0x7) == 2 ? 4 : 7;
2082 main_instr
.add_bits
|= (tag
& 0x7) << 17;
2083 instrs
[idx
] = main_instr
;
2084 consts
[0] |= (bits(words
[2], 19, 32) | ((uint64_t) words
[3] << 13)) << 19;
2086 num_instrs
= idx
+ 1;
2091 unsigned idx
= stop
? 4 : 1;
2092 main_instr
.add_bits
|= (tag
& 0x7) << 17;
2093 instrs
[idx
] = main_instr
;
2094 instrs
[idx
+ 1].fma_bits
|= bits(words
[3], 22, 32);
2095 instrs
[idx
+ 1].reg_bits
= bits(words
[2], 19, 32) | (bits(words
[3], 0, 22) << (32 - 19));
2099 // only constants can come after this
2103 header_bits
= bits(words
[2], 19, 32) | ((uint64_t) words
[3] << (32 - 19));
2104 main_instr
.add_bits
|= (tag
& 0x7) << 17;
2105 instrs
[0] = main_instr
;
2109 unsigned pos
= tag
& 0xf;
2110 // note that `pos' encodes both the total number of
2111 // instructions and the position in the constant stream,
2112 // presumably because decoded constants and instructions
2113 // share a buffer in the decoder, but we only care about
2114 // the position in the constant stream; the total number of
2115 // instructions is redundant.
2116 unsigned const_idx
= 0;
2143 fprintf(fp
, "# unknown pos 0x%x\n", pos
);
2147 if (num_consts
< const_idx
+ 2)
2148 num_consts
= const_idx
+ 2;
2150 consts
[const_idx
] = const0
;
2151 consts
[const_idx
+ 1] = const1
;
2167 fprintf(fp
, "# header: %012" PRIx64
"\n", header_bits
);
2170 struct bifrost_header header
;
2171 memcpy((char *) &header
, (char *) &header_bits
, sizeof(struct bifrost_header
));
2172 dump_header(fp
, header
, verbose
);
2173 if (!header
.no_end_of_shader
)
2177 for (i
= 0; i
< num_instrs
; i
++) {
2178 struct bifrost_regs next_regs
;
2179 if (i
+ 1 == num_instrs
) {
2180 memcpy((char *) &next_regs
, (char *) &instrs
[0].reg_bits
,
2183 memcpy((char *) &next_regs
, (char *) &instrs
[i
+ 1].reg_bits
,
2187 dump_instr(fp
, &instrs
[i
], next_regs
, consts
, header
.datareg
, offset
, verbose
);
2192 for (unsigned i
= 0; i
< num_consts
; i
++) {
2193 fprintf(fp
, "# const%d: %08" PRIx64
"\n", 2 * i
, consts
[i
] & 0xffffffff);
2194 fprintf(fp
, "# const%d: %08" PRIx64
"\n", 2 * i
+ 1, consts
[i
] >> 32);
2200 void disassemble_bifrost(FILE *fp
, uint8_t *code
, size_t size
, bool verbose
)
2202 uint32_t *words
= (uint32_t *) code
;
2203 uint32_t *words_end
= words
+ (size
/ 4);
2204 // used for displaying branch targets
2205 unsigned offset
= 0;
2206 while (words
!= words_end
) {
2207 // we don't know what the program-end bit is quite yet, so for now just
2208 // assume that an all-0 quadword is padding
2209 uint32_t zero
[4] = {};
2210 if (memcmp(words
, zero
, 4 * sizeof(uint32_t)) == 0)
2212 fprintf(fp
, "clause_%d:\n", offset
);
2214 if (dump_clause(fp
, words
, &size
, offset
, verbose
) == true) {