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pan/bi: Add f16 TEXC.vtx op
[mesa.git] / src / panfrost / bifrost / disassemble.c
1 /*
2 * Copyright (C) 2019 Connor Abbott <cwabbott0@gmail.com>
3 * Copyright (C) 2019 Lyude Paul <thatslyude@gmail.com>
4 * Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #include <stdbool.h>
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <assert.h>
30 #include <inttypes.h>
31 #include <string.h>
32
33 #include "bifrost.h"
34 #include "disassemble.h"
35 #include "bi_print.h"
36 #include "util/macros.h"
37
38 // return bits (high, lo]
39 static uint64_t bits(uint32_t word, unsigned lo, unsigned high)
40 {
41 if (high == 32)
42 return word >> lo;
43 return (word & ((1 << high) - 1)) >> lo;
44 }
45
46 // each of these structs represents an instruction that's dispatched in one
47 // cycle. Note that these instructions are packed in funny ways within the
48 // clause, hence the need for a separate struct.
49 struct bifrost_alu_inst {
50 uint32_t fma_bits;
51 uint32_t add_bits;
52 uint64_t reg_bits;
53 };
54
55 static unsigned get_reg0(struct bifrost_regs regs)
56 {
57 if (regs.ctrl == 0)
58 return regs.reg0 | ((regs.reg1 & 0x1) << 5);
59
60 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0;
61 }
62
63 static unsigned get_reg1(struct bifrost_regs regs)
64 {
65 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1;
66 }
67
68 // this represents the decoded version of the ctrl register field.
69 struct bifrost_reg_ctrl {
70 bool read_reg0;
71 bool read_reg1;
72 bool read_reg3;
73 enum bifrost_reg_write_unit fma_write_unit;
74 enum bifrost_reg_write_unit add_write_unit;
75 bool clause_start;
76 };
77
78 enum fma_src_type {
79 FMA_ONE_SRC,
80 FMA_TWO_SRC,
81 FMA_FADD,
82 FMA_FMINMAX,
83 FMA_FADD16,
84 FMA_FMINMAX16,
85 FMA_FCMP,
86 FMA_FCMP16,
87 FMA_THREE_SRC,
88 FMA_SHIFT,
89 FMA_FMA,
90 FMA_FMA16,
91 FMA_CSEL4,
92 FMA_FMA_MSCALE,
93 FMA_SHIFT_ADD64,
94 };
95
96 struct fma_op_info {
97 bool extended;
98 unsigned op;
99 char name[30];
100 enum fma_src_type src_type;
101 };
102
103 enum add_src_type {
104 ADD_ONE_SRC,
105 ADD_TWO_SRC,
106 ADD_FADD,
107 ADD_FMINMAX,
108 ADD_FADD16,
109 ADD_FMINMAX16,
110 ADD_THREE_SRC,
111 ADD_SHIFT,
112 ADD_FADDMscale,
113 ADD_FCMP,
114 ADD_FCMP16,
115 ADD_TEX_COMPACT, // texture instruction with embedded sampler
116 ADD_TEX, // texture instruction with sampler/etc. in uniform port
117 ADD_VARYING_INTERP,
118 ADD_BLENDING,
119 ADD_LOAD_ATTR,
120 ADD_VARYING_ADDRESS,
121 ADD_BRANCH,
122 };
123
124 struct add_op_info {
125 unsigned op;
126 char name[30];
127 enum add_src_type src_type;
128 bool has_data_reg;
129 };
130
131 void dump_header(FILE *fp, struct bifrost_header header, bool verbose);
132 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
133 struct bifrost_regs next_regs, uint64_t *consts,
134 unsigned data_reg, unsigned offset, bool verbose);
135 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose);
136
137 void dump_header(FILE *fp, struct bifrost_header header, bool verbose)
138 {
139 fprintf(fp, "id(%du) ", header.scoreboard_index);
140
141 if (header.clause_type != 0) {
142 const char *name = bi_clause_type_name(header.clause_type);
143
144 if (name[0] == '?')
145 fprintf(fp, "unk%u ", header.clause_type);
146 else
147 fprintf(fp, "%s ", name);
148 }
149
150 if (header.scoreboard_deps != 0) {
151 fprintf(fp, "next-wait(");
152 bool first = true;
153 for (unsigned i = 0; i < 8; i++) {
154 if (header.scoreboard_deps & (1 << i)) {
155 if (!first) {
156 fprintf(fp, ", ");
157 }
158 fprintf(fp, "%d", i);
159 first = false;
160 }
161 }
162 fprintf(fp, ") ");
163 }
164
165 if (header.datareg_writebarrier)
166 fprintf(fp, "data-reg-barrier ");
167
168 if (!header.no_end_of_shader)
169 fprintf(fp, "eos ");
170
171 if (!header.back_to_back) {
172 fprintf(fp, "nbb ");
173 if (header.branch_cond)
174 fprintf(fp, "branch-cond ");
175 else
176 fprintf(fp, "branch-uncond ");
177 }
178
179 if (header.elide_writes)
180 fprintf(fp, "we ");
181
182 if (header.suppress_inf)
183 fprintf(fp, "suppress-inf ");
184 if (header.suppress_nan)
185 fprintf(fp, "suppress-nan ");
186
187 if (header.unk0)
188 fprintf(fp, "unk0 ");
189 if (header.unk1)
190 fprintf(fp, "unk1 ");
191 if (header.unk2)
192 fprintf(fp, "unk2 ");
193 if (header.unk3)
194 fprintf(fp, "unk3 ");
195 if (header.unk4)
196 fprintf(fp, "unk4 ");
197
198 fprintf(fp, "\n");
199
200 if (verbose) {
201 fprintf(fp, "# clause type %d, next clause type %d\n",
202 header.clause_type, header.next_clause_type);
203 }
204 }
205
206 static struct bifrost_reg_ctrl DecodeRegCtrl(FILE *fp, struct bifrost_regs regs)
207 {
208 struct bifrost_reg_ctrl decoded = {};
209 unsigned ctrl;
210 if (regs.ctrl == 0) {
211 ctrl = regs.reg1 >> 2;
212 decoded.read_reg0 = !(regs.reg1 & 0x2);
213 decoded.read_reg1 = false;
214 } else {
215 ctrl = regs.ctrl;
216 decoded.read_reg0 = decoded.read_reg1 = true;
217 }
218 switch (ctrl) {
219 case 1:
220 decoded.fma_write_unit = REG_WRITE_TWO;
221 break;
222 case 2:
223 case 3:
224 decoded.fma_write_unit = REG_WRITE_TWO;
225 decoded.read_reg3 = true;
226 break;
227 case 4:
228 decoded.read_reg3 = true;
229 break;
230 case 5:
231 decoded.add_write_unit = REG_WRITE_TWO;
232 break;
233 case 6:
234 decoded.add_write_unit = REG_WRITE_TWO;
235 decoded.read_reg3 = true;
236 break;
237 case 8:
238 decoded.clause_start = true;
239 break;
240 case 9:
241 decoded.fma_write_unit = REG_WRITE_TWO;
242 decoded.clause_start = true;
243 break;
244 case 11:
245 break;
246 case 12:
247 decoded.read_reg3 = true;
248 decoded.clause_start = true;
249 break;
250 case 13:
251 decoded.add_write_unit = REG_WRITE_TWO;
252 decoded.clause_start = true;
253 break;
254
255 case 7:
256 case 15:
257 decoded.fma_write_unit = REG_WRITE_THREE;
258 decoded.add_write_unit = REG_WRITE_TWO;
259 break;
260 default:
261 fprintf(fp, "# unknown reg ctrl %d\n", ctrl);
262 }
263
264 return decoded;
265 }
266
267 // Pass in the add_write_unit or fma_write_unit, and this returns which register
268 // the ADD/FMA units are writing to
269 static unsigned GetRegToWrite(enum bifrost_reg_write_unit unit, struct bifrost_regs regs)
270 {
271 switch (unit) {
272 case REG_WRITE_TWO:
273 return regs.reg2;
274 case REG_WRITE_THREE:
275 return regs.reg3;
276 default: /* REG_WRITE_NONE */
277 assert(0);
278 return 0;
279 }
280 }
281
282 static void dump_regs(FILE *fp, struct bifrost_regs srcs)
283 {
284 struct bifrost_reg_ctrl ctrl = DecodeRegCtrl(fp, srcs);
285 fprintf(fp, "# ");
286 if (ctrl.read_reg0)
287 fprintf(fp, "port 0: R%d ", get_reg0(srcs));
288 if (ctrl.read_reg1)
289 fprintf(fp, "port 1: R%d ", get_reg1(srcs));
290
291 if (ctrl.fma_write_unit == REG_WRITE_TWO)
292 fprintf(fp, "port 2: R%d (write FMA) ", srcs.reg2);
293 else if (ctrl.add_write_unit == REG_WRITE_TWO)
294 fprintf(fp, "port 2: R%d (write ADD) ", srcs.reg2);
295
296 if (ctrl.fma_write_unit == REG_WRITE_THREE)
297 fprintf(fp, "port 3: R%d (write FMA) ", srcs.reg3);
298 else if (ctrl.add_write_unit == REG_WRITE_THREE)
299 fprintf(fp, "port 3: R%d (write ADD) ", srcs.reg3);
300 else if (ctrl.read_reg3)
301 fprintf(fp, "port 3: R%d (read) ", srcs.reg3);
302
303 if (srcs.uniform_const) {
304 if (srcs.uniform_const & 0x80) {
305 fprintf(fp, "uniform: U%d", (srcs.uniform_const & 0x7f) * 2);
306 }
307 }
308
309 fprintf(fp, "\n");
310 }
311 static void dump_const_imm(FILE *fp, uint32_t imm)
312 {
313 union {
314 float f;
315 uint32_t i;
316 } fi;
317 fi.i = imm;
318 fprintf(fp, "0x%08x /* %f */", imm, fi.f);
319 }
320
321 static uint64_t get_const(uint64_t *consts, struct bifrost_regs srcs)
322 {
323 unsigned low_bits = srcs.uniform_const & 0xf;
324 uint64_t imm;
325 switch (srcs.uniform_const >> 4) {
326 case 4:
327 imm = consts[0];
328 break;
329 case 5:
330 imm = consts[1];
331 break;
332 case 6:
333 imm = consts[2];
334 break;
335 case 7:
336 imm = consts[3];
337 break;
338 case 2:
339 imm = consts[4];
340 break;
341 case 3:
342 imm = consts[5];
343 break;
344 default:
345 assert(0);
346 break;
347 }
348 return imm | low_bits;
349 }
350
351 static void dump_uniform_const_src(FILE *fp, struct bifrost_regs srcs, uint64_t *consts, bool high32)
352 {
353 if (srcs.uniform_const & 0x80) {
354 unsigned uniform = (srcs.uniform_const & 0x7f) * 2;
355 fprintf(fp, "U%d", uniform + (high32 ? 1 : 0));
356 } else if (srcs.uniform_const >= 0x20) {
357 uint64_t imm = get_const(consts, srcs);
358 if (high32)
359 dump_const_imm(fp, imm >> 32);
360 else
361 dump_const_imm(fp, imm);
362 } else {
363 switch (srcs.uniform_const) {
364 case 0:
365 fprintf(fp, "0");
366 break;
367 case 5:
368 fprintf(fp, "atest-data");
369 break;
370 case 6:
371 fprintf(fp, "sample-ptr");
372 break;
373 case 8:
374 case 9:
375 case 10:
376 case 11:
377 case 12:
378 case 13:
379 case 14:
380 case 15:
381 fprintf(fp, "blend-descriptor%u", (unsigned) srcs.uniform_const - 8);
382 break;
383 default:
384 fprintf(fp, "unkConst%u", (unsigned) srcs.uniform_const);
385 break;
386 }
387
388 if (high32)
389 fprintf(fp, ".y");
390 else
391 fprintf(fp, ".x");
392 }
393 }
394
395 static void dump_src(FILE *fp, unsigned src, struct bifrost_regs srcs, uint64_t *consts, bool isFMA)
396 {
397 switch (src) {
398 case 0:
399 fprintf(fp, "R%d", get_reg0(srcs));
400 break;
401 case 1:
402 fprintf(fp, "R%d", get_reg1(srcs));
403 break;
404 case 2:
405 fprintf(fp, "R%d", srcs.reg3);
406 break;
407 case 3:
408 if (isFMA)
409 fprintf(fp, "0");
410 else
411 fprintf(fp, "T"); // i.e. the output of FMA this cycle
412 break;
413 case 4:
414 dump_uniform_const_src(fp, srcs, consts, false);
415 break;
416 case 5:
417 dump_uniform_const_src(fp, srcs, consts, true);
418 break;
419 case 6:
420 fprintf(fp, "T0");
421 break;
422 case 7:
423 fprintf(fp, "T1");
424 break;
425 }
426 }
427
428 static const struct fma_op_info FMAOpInfos[] = {
429 { false, 0x00000, "FMA.f32", FMA_FMA },
430 { false, 0x40000, "MAX.f32", FMA_FMINMAX },
431 { false, 0x44000, "MIN.f32", FMA_FMINMAX },
432 { false, 0x48000, "FCMP.GL", FMA_FCMP },
433 { false, 0x4c000, "FCMP.D3D", FMA_FCMP },
434 { false, 0x4ff98, "ADD.i32", FMA_TWO_SRC },
435 { false, 0x4ffd8, "SUB.i32", FMA_TWO_SRC },
436 { false, 0x4fff0, "SUBB.i32", FMA_TWO_SRC },
437 { false, 0x50000, "FMA_MSCALE", FMA_FMA_MSCALE },
438 { false, 0x58000, "ADD.f32", FMA_FADD },
439 { false, 0x5c000, "CSEL4", FMA_CSEL4 },
440 { false, 0x5d8d0, "ICMP.D3D.GT.v2i16", FMA_TWO_SRC },
441 { false, 0x5d9d0, "UCMP.D3D.GT.v2i16", FMA_TWO_SRC },
442 { false, 0x5dad0, "ICMP.D3D.GE.v2i16", FMA_TWO_SRC },
443 { false, 0x5dbd0, "UCMP.D3D.GE.v2i16", FMA_TWO_SRC },
444 { false, 0x5dcd0, "ICMP.D3D.EQ.v2i16", FMA_TWO_SRC },
445 { false, 0x5de40, "ICMP.GL.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? 1 : 0
446 { false, 0x5de48, "ICMP.GL.GE.i32", FMA_TWO_SRC },
447 { false, 0x5de50, "UCMP.GL.GT.i32", FMA_TWO_SRC },
448 { false, 0x5de58, "UCMP.GL.GE.i32", FMA_TWO_SRC },
449 { false, 0x5de60, "ICMP.GL.EQ.i32", FMA_TWO_SRC },
450 { false, 0x5dec0, "ICMP.D3D.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? ~0 : 0
451 { false, 0x5dec8, "ICMP.D3D.GE.i32", FMA_TWO_SRC },
452 { false, 0x5ded0, "UCMP.D3D.GT.i32", FMA_TWO_SRC },
453 { false, 0x5ded8, "UCMP.D3D.GE.i32", FMA_TWO_SRC },
454 { false, 0x5dee0, "ICMP.D3D.EQ.i32", FMA_TWO_SRC },
455 { false, 0x60000, "RSHIFT_NAND", FMA_SHIFT },
456 { false, 0x61000, "RSHIFT_AND", FMA_SHIFT },
457 { false, 0x62000, "LSHIFT_NAND", FMA_SHIFT },
458 { false, 0x63000, "LSHIFT_AND", FMA_SHIFT }, // (src0 << src2) & src1
459 { false, 0x64000, "RSHIFT_XOR", FMA_SHIFT },
460 { false, 0x65200, "LSHIFT_ADD.i32", FMA_THREE_SRC },
461 { false, 0x65600, "LSHIFT_SUB.i32", FMA_THREE_SRC }, // (src0 << src2) - src1
462 { false, 0x65a00, "LSHIFT_RSUB.i32", FMA_THREE_SRC }, // src1 - (src0 << src2)
463 { false, 0x65e00, "RSHIFT_ADD.i32", FMA_THREE_SRC },
464 { false, 0x66200, "RSHIFT_SUB.i32", FMA_THREE_SRC },
465 { false, 0x66600, "RSHIFT_RSUB.i32", FMA_THREE_SRC },
466 { false, 0x66a00, "ARSHIFT_ADD.i32", FMA_THREE_SRC },
467 { false, 0x66e00, "ARSHIFT_SUB.i32", FMA_THREE_SRC },
468 { false, 0x67200, "ARSHIFT_RSUB.i32", FMA_THREE_SRC },
469 { false, 0x80000, "FMA.v2f16", FMA_FMA16 },
470 { false, 0xc0000, "MAX.v2f16", FMA_FMINMAX16 },
471 { false, 0xc4000, "MIN.v2f16", FMA_FMINMAX16 },
472 { false, 0xc8000, "FCMP.GL", FMA_FCMP16 },
473 { false, 0xcc000, "FCMP.D3D", FMA_FCMP16 },
474 { false, 0xcf900, "ADD.v2i16", FMA_TWO_SRC },
475 { false, 0xcfc10, "ADDC.i32", FMA_TWO_SRC },
476 { false, 0xcfd80, "ADD.i32.i16.X", FMA_TWO_SRC },
477 { false, 0xcfd90, "ADD.i32.u16.X", FMA_TWO_SRC },
478 { false, 0xcfdc0, "ADD.i32.i16.Y", FMA_TWO_SRC },
479 { false, 0xcfdd0, "ADD.i32.u16.Y", FMA_TWO_SRC },
480 { false, 0xd8000, "ADD.v2f16", FMA_FADD16 },
481 { false, 0xdc000, "CSEL4.v16", FMA_CSEL4 },
482 { false, 0xdd000, "F32_TO_F16", FMA_TWO_SRC },
483
484 /* TODO: Combine to bifrost_fma_f2i_i2f16 */
485 { true, 0x00046, "F16_TO_I16.XX", FMA_ONE_SRC },
486 { true, 0x00047, "F16_TO_U16.XX", FMA_ONE_SRC },
487 { true, 0x0004e, "F16_TO_I16.YX", FMA_ONE_SRC },
488 { true, 0x0004f, "F16_TO_U16.YX", FMA_ONE_SRC },
489 { true, 0x00056, "F16_TO_I16.XY", FMA_ONE_SRC },
490 { true, 0x00057, "F16_TO_U16.XY", FMA_ONE_SRC },
491 { true, 0x0005e, "F16_TO_I16.YY", FMA_ONE_SRC },
492 { true, 0x0005f, "F16_TO_U16.YY", FMA_ONE_SRC },
493 { true, 0x000c0, "I16_TO_F16.XX", FMA_ONE_SRC },
494 { true, 0x000c1, "U16_TO_F16.XX", FMA_ONE_SRC },
495 { true, 0x000c8, "I16_TO_F16.YX", FMA_ONE_SRC },
496 { true, 0x000c9, "U16_TO_F16.YX", FMA_ONE_SRC },
497 { true, 0x000d0, "I16_TO_F16.XY", FMA_ONE_SRC },
498 { true, 0x000d1, "U16_TO_F16.XY", FMA_ONE_SRC },
499 { true, 0x000d8, "I16_TO_F16.YY", FMA_ONE_SRC },
500 { true, 0x000d9, "U16_TO_F16.YY", FMA_ONE_SRC },
501
502 { true, 0x00136, "F32_TO_I32", FMA_ONE_SRC },
503 { true, 0x00137, "F32_TO_U32", FMA_ONE_SRC },
504 { true, 0x00178, "I32_TO_F32", FMA_ONE_SRC },
505 { true, 0x00179, "U32_TO_F32", FMA_ONE_SRC },
506
507 /* TODO: cleanup to use bifrost_fma_int16_to_32 */
508 { true, 0x00198, "I16_TO_I32.X", FMA_ONE_SRC },
509 { true, 0x00199, "U16_TO_U32.X", FMA_ONE_SRC },
510 { true, 0x0019a, "I16_TO_I32.Y", FMA_ONE_SRC },
511 { true, 0x0019b, "U16_TO_U32.Y", FMA_ONE_SRC },
512 { true, 0x0019c, "I16_TO_F32.X", FMA_ONE_SRC },
513 { true, 0x0019d, "U16_TO_F32.X", FMA_ONE_SRC },
514 { true, 0x0019e, "I16_TO_F32.Y", FMA_ONE_SRC },
515 { true, 0x0019f, "U16_TO_F32.Y", FMA_ONE_SRC },
516
517 { true, 0x001a2, "F16_TO_F32.X", FMA_ONE_SRC },
518 { true, 0x001a3, "F16_TO_F32.Y", FMA_ONE_SRC },
519
520 { true, 0x0032c, "NOP", FMA_ONE_SRC },
521 { true, 0x0032d, "MOV", FMA_ONE_SRC },
522 { true, 0x0032f, "SWZ.YY.v2i16", FMA_ONE_SRC },
523 { true, 0x00345, "LOG_FREXPM", FMA_ONE_SRC },
524 { true, 0x00365, "FRCP_FREXPM", FMA_ONE_SRC },
525 { true, 0x00375, "FSQRT_FREXPM", FMA_ONE_SRC },
526 { true, 0x0038d, "FRCP_FREXPE", FMA_ONE_SRC },
527 { true, 0x003a5, "FSQRT_FREXPE", FMA_ONE_SRC },
528 { true, 0x003ad, "FRSQ_FREXPE", FMA_ONE_SRC },
529 { true, 0x003c5, "LOG_FREXPE", FMA_ONE_SRC },
530 { true, 0x003fa, "CLZ", FMA_ONE_SRC },
531 { true, 0x00b80, "IMAX3", FMA_THREE_SRC },
532 { true, 0x00bc0, "UMAX3", FMA_THREE_SRC },
533 { true, 0x00c00, "IMIN3", FMA_THREE_SRC },
534 { true, 0x00c40, "UMIN3", FMA_THREE_SRC },
535 { true, 0x00ec2, "ROUND.v2f16", FMA_ONE_SRC },
536 { true, 0x00ec5, "ROUND.f32", FMA_ONE_SRC },
537 { true, 0x00f40, "CSEL", FMA_THREE_SRC }, // src2 != 0 ? src1 : src0
538 { true, 0x00fc0, "MUX.i32", FMA_THREE_SRC }, // see ADD comment
539 { true, 0x01802, "ROUNDEVEN.v2f16", FMA_ONE_SRC },
540 { true, 0x01805, "ROUNDEVEN.f32", FMA_ONE_SRC },
541 { true, 0x01842, "CEIL.v2f16", FMA_ONE_SRC },
542 { true, 0x01845, "CEIL.f32", FMA_ONE_SRC },
543 { true, 0x01882, "FLOOR.v2f16", FMA_ONE_SRC },
544 { true, 0x01885, "FLOOR.f32", FMA_ONE_SRC },
545 { true, 0x018c2, "TRUNC.v2f16", FMA_ONE_SRC },
546 { true, 0x018c5, "TRUNC.f32", FMA_ONE_SRC },
547 { true, 0x019b0, "ATAN_LDEXP.Y.f32", FMA_TWO_SRC },
548 { true, 0x019b8, "ATAN_LDEXP.X.f32", FMA_TWO_SRC },
549 { true, 0x01c80, "LSHIFT_ADD_LOW32.u32", FMA_SHIFT_ADD64 },
550 { true, 0x01cc0, "LSHIFT_ADD_LOW32.i64", FMA_SHIFT_ADD64 },
551 { true, 0x01d80, "LSHIFT_ADD_LOW32.i32", FMA_SHIFT_ADD64 },
552 { true, 0x01e00, "SEL.XX.i16", FMA_TWO_SRC },
553 { true, 0x01e08, "SEL.YX.i16", FMA_TWO_SRC },
554 { true, 0x01e10, "SEL.XY.i16", FMA_TWO_SRC },
555 { true, 0x01e18, "SEL.YY.i16", FMA_TWO_SRC },
556 { true, 0x01e80, "ADD_FREXPM.f32", FMA_TWO_SRC },
557 { true, 0x02000, "SWZ.XXXX.v4i8", FMA_ONE_SRC },
558 { true, 0x03e00, "SWZ.ZZZZ.v4i8", FMA_ONE_SRC },
559 { true, 0x00800, "IMAD", FMA_THREE_SRC },
560 { true, 0x078db, "POPCNT", FMA_ONE_SRC },
561 };
562
563 static struct fma_op_info find_fma_op_info(unsigned op, bool extended)
564 {
565 for (unsigned i = 0; i < ARRAY_SIZE(FMAOpInfos); i++) {
566 unsigned opCmp = ~0;
567
568 if (FMAOpInfos[i].extended != extended)
569 continue;
570
571 if (extended)
572 op &= ~0xe0000;
573
574 switch (FMAOpInfos[i].src_type) {
575 case FMA_ONE_SRC:
576 opCmp = op;
577 break;
578 case FMA_TWO_SRC:
579 opCmp = op & ~0x7;
580 break;
581 case FMA_FCMP:
582 case FMA_FCMP16:
583 opCmp = op & ~0x1fff;
584 break;
585 case FMA_THREE_SRC:
586 case FMA_SHIFT_ADD64:
587 opCmp = op & ~0x3f;
588 break;
589 case FMA_FADD:
590 case FMA_FMINMAX:
591 case FMA_FADD16:
592 case FMA_FMINMAX16:
593 opCmp = op & ~0x3fff;
594 break;
595 case FMA_FMA:
596 case FMA_FMA16:
597 opCmp = op & ~0x3ffff;
598 break;
599 case FMA_CSEL4:
600 case FMA_SHIFT:
601 opCmp = op & ~0xfff;
602 break;
603 case FMA_FMA_MSCALE:
604 opCmp = op & ~0x7fff;
605 break;
606 default:
607 opCmp = ~0;
608 break;
609 }
610 if (FMAOpInfos[i].op == opCmp)
611 return FMAOpInfos[i];
612 }
613
614 struct fma_op_info info;
615 snprintf(info.name, sizeof(info.name), "op%04x", op);
616 info.op = op;
617 info.src_type = FMA_THREE_SRC;
618 return info;
619 }
620
621 static void dump_fcmp(FILE *fp, unsigned op)
622 {
623 switch (op) {
624 case 0:
625 fprintf(fp, ".OEQ");
626 break;
627 case 1:
628 fprintf(fp, ".OGT");
629 break;
630 case 2:
631 fprintf(fp, ".OGE");
632 break;
633 case 3:
634 fprintf(fp, ".UNE");
635 break;
636 case 4:
637 fprintf(fp, ".OLT");
638 break;
639 case 5:
640 fprintf(fp, ".OLE");
641 break;
642 default:
643 fprintf(fp, ".unk%d", op);
644 break;
645 }
646 }
647
648 static void dump_16swizzle(FILE *fp, unsigned swiz)
649 {
650 if (swiz == 2)
651 return;
652 fprintf(fp, ".%c%c", "xy"[swiz & 1], "xy"[(swiz >> 1) & 1]);
653 }
654
655 static void dump_fma_expand_src0(FILE *fp, unsigned ctrl)
656 {
657 switch (ctrl) {
658 case 3:
659 case 4:
660 case 6:
661 fprintf(fp, ".x");
662 break;
663 case 5:
664 case 7:
665 fprintf(fp, ".y");
666 break;
667 case 0:
668 case 1:
669 case 2:
670 break;
671 default:
672 fprintf(fp, ".unk");
673 break;
674 }
675 }
676
677 static void dump_fma_expand_src1(FILE *fp, unsigned ctrl)
678 {
679 switch (ctrl) {
680 case 1:
681 case 3:
682 fprintf(fp, ".x");
683 break;
684 case 2:
685 case 4:
686 case 5:
687 fprintf(fp, ".y");
688 break;
689 case 0:
690 case 6:
691 case 7:
692 break;
693 default:
694 fprintf(fp, ".unk");
695 break;
696 }
697 }
698
699 static void dump_fma(FILE *fp, uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts, bool verbose)
700 {
701 if (verbose) {
702 fprintf(fp, "# FMA: %016" PRIx64 "\n", word);
703 }
704 struct bifrost_fma_inst FMA;
705 memcpy((char *) &FMA, (char *) &word, sizeof(struct bifrost_fma_inst));
706 struct fma_op_info info = find_fma_op_info(FMA.op, (FMA.op & 0xe0000) == 0xe0000);
707
708 fprintf(fp, "%s", info.name);
709 if (info.src_type == FMA_FADD ||
710 info.src_type == FMA_FMINMAX ||
711 info.src_type == FMA_FMA ||
712 info.src_type == FMA_FADD16 ||
713 info.src_type == FMA_FMINMAX16 ||
714 info.src_type == FMA_FMA16) {
715 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 12, 14)));
716 switch (info.src_type) {
717 case FMA_FADD:
718 case FMA_FMA:
719 case FMA_FADD16:
720 case FMA_FMA16:
721 fprintf(fp, "%s", bi_round_mode_name(bits(FMA.op, 10, 12)));
722 break;
723 case FMA_FMINMAX:
724 case FMA_FMINMAX16:
725 fprintf(fp, "%s", bi_minmax_mode_name(bits(FMA.op, 10, 12)));
726 break;
727 default:
728 assert(0);
729 }
730 } else if (info.src_type == FMA_FCMP || info.src_type == FMA_FCMP16) {
731 dump_fcmp(fp, bits(FMA.op, 10, 13));
732 if (info.src_type == FMA_FCMP)
733 fprintf(fp, ".f32");
734 else
735 fprintf(fp, ".v2f16");
736 } else if (info.src_type == FMA_FMA_MSCALE) {
737 if (FMA.op & (1 << 11)) {
738 switch ((FMA.op >> 9) & 0x3) {
739 case 0:
740 /* This mode seems to do a few things:
741 * - Makes 0 * infinity (and incidentally 0 * nan) return 0,
742 * since generating a nan would poison the result of
743 * 1/infinity and 1/0.
744 * - Fiddles with which nan is returned in nan * nan,
745 * presumably to make sure that the same exact nan is
746 * returned for 1/nan.
747 */
748 fprintf(fp, ".rcp_mode");
749 break;
750 case 3:
751 /* Similar to the above, but src0 always wins when multiplying
752 * 0 by infinity.
753 */
754 fprintf(fp, ".sqrt_mode");
755 break;
756 default:
757 fprintf(fp, ".unk%d_mode", (int) (FMA.op >> 9) & 0x3);
758 }
759 } else {
760 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 9, 11)));
761 }
762 } else if (info.src_type == FMA_SHIFT) {
763 struct bifrost_shift_fma shift;
764 memcpy(&shift, &FMA, sizeof(shift));
765
766 if (shift.half == 0x7)
767 fprintf(fp, ".v2i16");
768 else if (shift.half == 0)
769 fprintf(fp, ".i32");
770 else if (shift.half == 0x4)
771 fprintf(fp, ".v4i8");
772 else
773 fprintf(fp, ".unk%u", shift.half);
774
775 if (!shift.unk)
776 fprintf(fp, ".no_unk");
777
778 if (shift.invert_1)
779 fprintf(fp, ".invert_1");
780
781 if (shift.invert_2)
782 fprintf(fp, ".invert_2");
783 }
784
785 fprintf(fp, " ");
786
787 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
788 if (next_ctrl.fma_write_unit != REG_WRITE_NONE) {
789 fprintf(fp, "{R%d, T0}, ", GetRegToWrite(next_ctrl.fma_write_unit, next_regs));
790 } else {
791 fprintf(fp, "T0, ");
792 }
793
794 switch (info.src_type) {
795 case FMA_ONE_SRC:
796 dump_src(fp, FMA.src0, regs, consts, true);
797 break;
798 case FMA_TWO_SRC:
799 dump_src(fp, FMA.src0, regs, consts, true);
800 fprintf(fp, ", ");
801 dump_src(fp, FMA.op & 0x7, regs, consts, true);
802 break;
803 case FMA_FADD:
804 case FMA_FMINMAX:
805 if (FMA.op & 0x10)
806 fprintf(fp, "-");
807 if (FMA.op & 0x200)
808 fprintf(fp, "abs(");
809 dump_src(fp, FMA.src0, regs, consts, true);
810 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
811 if (FMA.op & 0x200)
812 fprintf(fp, ")");
813 fprintf(fp, ", ");
814 if (FMA.op & 0x20)
815 fprintf(fp, "-");
816 if (FMA.op & 0x8)
817 fprintf(fp, "abs(");
818 dump_src(fp, FMA.op & 0x7, regs, consts, true);
819 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
820 if (FMA.op & 0x8)
821 fprintf(fp, ")");
822 break;
823 case FMA_FADD16:
824 case FMA_FMINMAX16: {
825 bool abs1 = FMA.op & 0x8;
826 bool abs2 = (FMA.op & 0x7) < FMA.src0;
827 if (FMA.op & 0x10)
828 fprintf(fp, "-");
829 if (abs1 || abs2)
830 fprintf(fp, "abs(");
831 dump_src(fp, FMA.src0, regs, consts, true);
832 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
833 if (abs1 || abs2)
834 fprintf(fp, ")");
835 fprintf(fp, ", ");
836 if (FMA.op & 0x20)
837 fprintf(fp, "-");
838 if (abs1 && abs2)
839 fprintf(fp, "abs(");
840 dump_src(fp, FMA.op & 0x7, regs, consts, true);
841 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
842 if (abs1 && abs2)
843 fprintf(fp, ")");
844 break;
845 }
846 case FMA_FCMP:
847 if (FMA.op & 0x200)
848 fprintf(fp, "abs(");
849 dump_src(fp, FMA.src0, regs, consts, true);
850 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
851 if (FMA.op & 0x200)
852 fprintf(fp, ")");
853 fprintf(fp, ", ");
854 if (FMA.op & 0x20)
855 fprintf(fp, "-");
856 if (FMA.op & 0x8)
857 fprintf(fp, "abs(");
858 dump_src(fp, FMA.op & 0x7, regs, consts, true);
859 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
860 if (FMA.op & 0x8)
861 fprintf(fp, ")");
862 break;
863 case FMA_FCMP16:
864 dump_src(fp, FMA.src0, regs, consts, true);
865 // Note: this is kinda a guess, I haven't seen the blob set this to
866 // anything other than the identity, but it matches FMA_TWO_SRCFmod16
867 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
868 fprintf(fp, ", ");
869 dump_src(fp, FMA.op & 0x7, regs, consts, true);
870 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
871 break;
872 case FMA_SHIFT_ADD64:
873 dump_src(fp, FMA.src0, regs, consts, true);
874 fprintf(fp, ", ");
875 dump_src(fp, FMA.op & 0x7, regs, consts, true);
876 fprintf(fp, ", ");
877 fprintf(fp, "shift:%u", (FMA.op >> 3) & 0x7);
878 break;
879 case FMA_THREE_SRC:
880 dump_src(fp, FMA.src0, regs, consts, true);
881 fprintf(fp, ", ");
882 dump_src(fp, FMA.op & 0x7, regs, consts, true);
883 fprintf(fp, ", ");
884 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
885 break;
886 case FMA_SHIFT: {
887 struct bifrost_shift_fma shift;
888 memcpy(&shift, &FMA, sizeof(shift));
889
890 dump_src(fp, shift.src0, regs, consts, true);
891 fprintf(fp, ", ");
892 dump_src(fp, shift.src1, regs, consts, true);
893 fprintf(fp, ", ");
894 dump_src(fp, shift.src2, regs, consts, true);
895 break;
896 }
897 case FMA_FMA:
898 if (FMA.op & (1 << 14))
899 fprintf(fp, "-");
900 if (FMA.op & (1 << 9))
901 fprintf(fp, "abs(");
902 dump_src(fp, FMA.src0, regs, consts, true);
903 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
904 if (FMA.op & (1 << 9))
905 fprintf(fp, ")");
906 fprintf(fp, ", ");
907 if (FMA.op & (1 << 16))
908 fprintf(fp, "abs(");
909 dump_src(fp, FMA.op & 0x7, regs, consts, true);
910 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
911 if (FMA.op & (1 << 16))
912 fprintf(fp, ")");
913 fprintf(fp, ", ");
914 if (FMA.op & (1 << 15))
915 fprintf(fp, "-");
916 if (FMA.op & (1 << 17))
917 fprintf(fp, "abs(");
918 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
919 if (FMA.op & (1 << 17))
920 fprintf(fp, ")");
921 break;
922 case FMA_FMA16:
923 if (FMA.op & (1 << 14))
924 fprintf(fp, "-");
925 dump_src(fp, FMA.src0, regs, consts, true);
926 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
927 fprintf(fp, ", ");
928 dump_src(fp, FMA.op & 0x7, regs, consts, true);
929 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
930 fprintf(fp, ", ");
931 if (FMA.op & (1 << 15))
932 fprintf(fp, "-");
933 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
934 dump_16swizzle(fp, (FMA.op >> 16) & 0x3);
935 break;
936 case FMA_CSEL4: {
937 struct bifrost_csel4 csel;
938 memcpy(&csel, &FMA, sizeof(csel));
939 fprintf(fp, ".%s ", bi_csel_cond_name(csel.cond));
940
941 dump_src(fp, csel.src0, regs, consts, true);
942 fprintf(fp, ", ");
943 dump_src(fp, csel.src1, regs, consts, true);
944 fprintf(fp, ", ");
945 dump_src(fp, csel.src2, regs, consts, true);
946 fprintf(fp, ", ");
947 dump_src(fp, csel.src3, regs, consts, true);
948 break;
949 }
950 case FMA_FMA_MSCALE:
951 if (FMA.op & (1 << 12))
952 fprintf(fp, "abs(");
953 dump_src(fp, FMA.src0, regs, consts, true);
954 if (FMA.op & (1 << 12))
955 fprintf(fp, ")");
956 fprintf(fp, ", ");
957 if (FMA.op & (1 << 13))
958 fprintf(fp, "-");
959 dump_src(fp, FMA.op & 0x7, regs, consts, true);
960 fprintf(fp, ", ");
961 if (FMA.op & (1 << 14))
962 fprintf(fp, "-");
963 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
964 fprintf(fp, ", ");
965 dump_src(fp, (FMA.op >> 6) & 0x7, regs, consts, true);
966 break;
967 }
968 fprintf(fp, "\n");
969 }
970
971 static const struct add_op_info add_op_infos[] = {
972 { 0x00000, "MAX.f32", ADD_FMINMAX },
973 { 0x02000, "MIN.f32", ADD_FMINMAX },
974 { 0x04000, "ADD.f32", ADD_FADD },
975 { 0x06000, "FCMP.GL", ADD_FCMP },
976 { 0x07000, "FCMP.D3D", ADD_FCMP },
977 { 0x07856, "F16_TO_I16", ADD_ONE_SRC },
978 { 0x07857, "F16_TO_U16", ADD_ONE_SRC },
979 { 0x078c0, "I16_TO_F16.XX", ADD_ONE_SRC },
980 { 0x078c1, "U16_TO_F16.XX", ADD_ONE_SRC },
981 { 0x078c8, "I16_TO_F16.YX", ADD_ONE_SRC },
982 { 0x078c9, "U16_TO_F16.YX", ADD_ONE_SRC },
983 { 0x078d0, "I16_TO_F16.XY", ADD_ONE_SRC },
984 { 0x078d1, "U16_TO_F16.XY", ADD_ONE_SRC },
985 { 0x078d8, "I16_TO_F16.YY", ADD_ONE_SRC },
986 { 0x078d9, "U16_TO_F16.YY", ADD_ONE_SRC },
987 { 0x07909, "B1_TO_F16", ADD_ONE_SRC },
988 { 0x07936, "F32_TO_I32", ADD_ONE_SRC },
989 { 0x07937, "F32_TO_U32", ADD_ONE_SRC },
990 { 0x07971, "B1_TO_F32", ADD_ONE_SRC },
991 { 0x07978, "I32_TO_F32", ADD_ONE_SRC },
992 { 0x07979, "U32_TO_F32", ADD_ONE_SRC },
993 { 0x07998, "I16_TO_I32.X", ADD_ONE_SRC },
994 { 0x07999, "U16_TO_U32.X", ADD_ONE_SRC },
995 { 0x0799a, "I16_TO_I32.Y", ADD_ONE_SRC },
996 { 0x0799b, "U16_TO_U32.Y", ADD_ONE_SRC },
997 { 0x0799c, "I16_TO_F32.X", ADD_ONE_SRC },
998 { 0x0799d, "U16_TO_F32.X", ADD_ONE_SRC },
999 { 0x0799e, "I16_TO_F32.Y", ADD_ONE_SRC },
1000 { 0x0799f, "U16_TO_F32.Y", ADD_ONE_SRC },
1001 { 0x079a2, "F16_TO_F32.X", ADD_ONE_SRC },
1002 { 0x079a3, "F16_TO_F32.Y", ADD_ONE_SRC },
1003 { 0x07b2b, "SWZ.YX.v2i16", ADD_ONE_SRC },
1004 { 0x07b2c, "NOP", ADD_ONE_SRC },
1005 { 0x07b29, "SWZ.XX.v2i16", ADD_ONE_SRC },
1006 { 0x07b2d, "MOV", ADD_ONE_SRC },
1007 { 0x07b2f, "SWZ.YY.v2i16", ADD_ONE_SRC },
1008 { 0x07b65, "FRCP_FREXPM", ADD_ONE_SRC },
1009 { 0x07b75, "FSQRT_FREXPM", ADD_ONE_SRC },
1010 { 0x07b8d, "FRCP_FREXPE", ADD_ONE_SRC },
1011 { 0x07ba5, "FSQRT_FREXPE", ADD_ONE_SRC },
1012 { 0x07bad, "FRSQ_FREXPE", ADD_ONE_SRC },
1013 { 0x07bc5, "FLOG_FREXPE", ADD_ONE_SRC },
1014 { 0x07d42, "CEIL.v2f16", ADD_ONE_SRC },
1015 { 0x07d45, "CEIL.f32", ADD_ONE_SRC },
1016 { 0x07d82, "FLOOR.v2f16", ADD_ONE_SRC },
1017 { 0x07d85, "FLOOR.f32", ADD_ONE_SRC },
1018 { 0x07dc2, "TRUNC.v2f16", ADD_ONE_SRC },
1019 { 0x07dc5, "TRUNC.f32", ADD_ONE_SRC },
1020 { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC },
1021 { 0x08000, "LD_ATTR", ADD_LOAD_ATTR, true },
1022 { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP, true },
1023 { 0x0b000, "TEXC", ADD_TEX_COMPACT, true },
1024 { 0x0b400, "TEXC.vtx", ADD_TEX_COMPACT, true },
1025 { 0x0c188, "LOAD.i32", ADD_TWO_SRC, true },
1026 { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC, true },
1027 { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1028 { 0x0c1c8, "LOAD.v2i32", ADD_TWO_SRC, true },
1029 { 0x0c1e0, "LD_UBO.v2i32", ADD_TWO_SRC, true },
1030 { 0x0c1f8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1031 { 0x0c208, "LOAD.v4i32", ADD_TWO_SRC, true },
1032 { 0x0c220, "LD_UBO.v4i32", ADD_TWO_SRC, true },
1033 { 0x0c238, "LD_SCRATCH.v4i32", ADD_TWO_SRC, true },
1034 { 0x0c248, "STORE.v4i32", ADD_TWO_SRC, true },
1035 { 0x0c278, "ST_SCRATCH.v4i32", ADD_TWO_SRC, true },
1036 { 0x0c588, "STORE.i32", ADD_TWO_SRC, true },
1037 { 0x0c5b8, "ST_SCRATCH.i32", ADD_TWO_SRC, true },
1038 { 0x0c5c8, "STORE.v2i32", ADD_TWO_SRC, true },
1039 { 0x0c5f8, "ST_SCRATCH.v2i32", ADD_TWO_SRC, true },
1040 { 0x0c648, "LOAD.u16", ADD_TWO_SRC, true }, // zero-extends
1041 { 0x0ca88, "LOAD.v3i32", ADD_TWO_SRC, true },
1042 { 0x0caa0, "LD_UBO.v3i32", ADD_TWO_SRC, true },
1043 { 0x0cab8, "LD_SCRATCH.v3i32", ADD_TWO_SRC, true },
1044 { 0x0cb88, "STORE.v3i32", ADD_TWO_SRC, true },
1045 { 0x0cbb8, "ST_SCRATCH.v3i32", ADD_TWO_SRC, true },
1046 { 0x0cc00, "FRCP_FAST.f32", ADD_ONE_SRC },
1047 { 0x0cc20, "FRSQ_FAST.f32", ADD_ONE_SRC },
1048 { 0x0cc68, "FLOG2_U.f32", ADD_ONE_SRC },
1049 { 0x0cd58, "FEXP2_FAST.f32", ADD_ONE_SRC },
1050 { 0x0ce00, "FRCP_TABLE", ADD_ONE_SRC },
1051 { 0x0ce10, "FRCP_FAST.f16.X", ADD_ONE_SRC },
1052 { 0x0ce20, "FRSQ_TABLE", ADD_ONE_SRC },
1053 { 0x0ce30, "FRCP_FAST.f16.Y", ADD_ONE_SRC },
1054 { 0x0ce50, "FRSQ_FAST.f16.X", ADD_ONE_SRC },
1055 { 0x0ce60, "FRCP_APPROX", ADD_ONE_SRC },
1056 { 0x0ce70, "FRSQ_FAST.f16.Y", ADD_ONE_SRC },
1057 { 0x0cf40, "ATAN_ASSIST", ADD_TWO_SRC },
1058 { 0x0cf48, "ATAN_TABLE", ADD_TWO_SRC },
1059 { 0x0cf50, "SIN_TABLE", ADD_ONE_SRC },
1060 { 0x0cf51, "COS_TABLE", ADD_ONE_SRC },
1061 { 0x0cf58, "EXP_TABLE", ADD_ONE_SRC },
1062 { 0x0cf60, "FLOG2_TABLE", ADD_ONE_SRC },
1063 { 0x0cf64, "FLOGE_TABLE", ADD_ONE_SRC },
1064 { 0x0d000, "BRANCH", ADD_BRANCH },
1065 { 0x0e8c0, "MUX", ADD_THREE_SRC },
1066 { 0x0e9b0, "ATAN_LDEXP.Y.f32", ADD_TWO_SRC },
1067 { 0x0e9b8, "ATAN_LDEXP.X.f32", ADD_TWO_SRC },
1068 { 0x0ea60, "SEL.XX.i16", ADD_TWO_SRC },
1069 { 0x0ea70, "SEL.XY.i16", ADD_TWO_SRC },
1070 { 0x0ea68, "SEL.YX.i16", ADD_TWO_SRC },
1071 { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC },
1072 { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC },
1073 { 0x0e840, "CSEL.64", ADD_THREE_SRC }, // u2u32(src2) ? src0 : src1
1074 { 0x0e940, "CSEL.8", ADD_THREE_SRC }, // (src2 != 0) ? src0 : src1
1075 { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC }, // src0 > src1 ? 1 : 0
1076 { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC },
1077 { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC },
1078 { 0x0f658, "UCMP.GL.GE", ADD_TWO_SRC },
1079 { 0x0f660, "ICMP.GL.EQ", ADD_TWO_SRC },
1080 { 0x0f669, "ICMP.GL.NEQ", ADD_TWO_SRC },
1081 { 0x0f690, "UCMP.8.GT", ADD_TWO_SRC },
1082 { 0x0f698, "UCMP.8.GE", ADD_TWO_SRC },
1083 { 0x0f6a8, "ICMP.8.NE", ADD_TWO_SRC },
1084 { 0x0f6c0, "ICMP.D3D.GT", ADD_TWO_SRC }, // src0 > src1 ? ~0 : 0
1085 { 0x0f6c8, "ICMP.D3D.GE", ADD_TWO_SRC },
1086 { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC },
1087 { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC },
1088 { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC },
1089 { 0x0f700, "ICMP.64.GT.PT1", ADD_TWO_SRC },
1090 { 0x0f708, "ICMP.64.GE.PT1", ADD_TWO_SRC },
1091 { 0x0f710, "UCMP.64.GT.PT1", ADD_TWO_SRC },
1092 { 0x0f718, "UCMP.64.GE.PT1", ADD_TWO_SRC },
1093 { 0x0f720, "ICMP.64.EQ.PT1", ADD_TWO_SRC },
1094 { 0x0f728, "ICMP.64.NE.PT1", ADD_TWO_SRC },
1095 { 0x0f7c0, "ICMP.64.PT2", ADD_THREE_SRC }, // src3 = result of PT1
1096 { 0x10000, "MAX.v2f16", ADD_FMINMAX16 },
1097 { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale },
1098 { 0x12000, "MIN.v2f16", ADD_FMINMAX16 },
1099 { 0x14000, "ADD.v2f16", ADD_FADD16 },
1100 { 0x16000, "FCMP.GL", ADD_FCMP16 },
1101 { 0x17000, "FCMP.D3D", ADD_FCMP16 },
1102 { 0x17880, "ADD.v4i8", ADD_TWO_SRC },
1103 { 0x178c0, "ADD.i32", ADD_TWO_SRC },
1104 { 0x17900, "ADD.v2i16", ADD_TWO_SRC },
1105 { 0x17a80, "SUB.v4i8", ADD_TWO_SRC },
1106 { 0x17ac0, "SUB.i32", ADD_TWO_SRC },
1107 { 0x17b00, "SUB.v2i16", ADD_TWO_SRC },
1108 { 0x17c10, "ADDC.i32", ADD_TWO_SRC }, // adds src0 to the bottom bit of src1
1109 { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC },
1110 { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC },
1111 { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC },
1112 { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC },
1113 { 0x18000, "LD_VAR_ADDR", ADD_VARYING_ADDRESS, false },
1114 { 0x19100, "DISCARD.FEQ.f16", ADD_TWO_SRC, false },
1115 { 0x19108, "DISCARD.FNE.f16", ADD_TWO_SRC, false },
1116 { 0x19110, "DISCARD.FLE.f16", ADD_TWO_SRC, false },
1117 { 0x19118, "DISCARD.FLT.f16", ADD_TWO_SRC, false },
1118 { 0x19180, "DISCARD.FEQ.f32", ADD_TWO_SRC, false },
1119 { 0x19188, "DISCARD.FNE.f32", ADD_TWO_SRC, false },
1120 { 0x19190, "DISCARD.FLE.f32", ADD_TWO_SRC, false },
1121 { 0x19198, "DISCARD.FLT.f32", ADD_TWO_SRC, false },
1122 { 0x191e8, "ATEST.f32", ADD_TWO_SRC, true },
1123 { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC, true },
1124 { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC, true },
1125 { 0x19300, "ST_VAR.v1", ADD_THREE_SRC, true },
1126 { 0x19340, "ST_VAR.v2", ADD_THREE_SRC, true },
1127 { 0x19380, "ST_VAR.v3", ADD_THREE_SRC, true },
1128 { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC, true },
1129 { 0x1952c, "BLEND", ADD_BLENDING, true },
1130 { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP, true },
1131 { 0x1ae20, "TEX.vtx", ADD_TEX, true },
1132 { 0x1ae60, "TEX", ADD_TEX, true },
1133 { 0x1b000, "TEXC.f16", ADD_TEX_COMPACT, true },
1134 { 0x1b400, "TEXC.vtx.f16", ADD_TEX_COMPACT, true },
1135 { 0x1c000, "RSHIFT_NAND.i32", ADD_SHIFT },
1136 { 0x1c400, "RSHIFT_AND.i32", ADD_SHIFT },
1137 { 0x1c800, "LSHIFT_NAND.i32", ADD_SHIFT },
1138 { 0x1cc00, "LSHIFT_AND.i32", ADD_SHIFT },
1139 { 0x1d000, "RSHIFT_XOR.i32", ADD_SHIFT },
1140 { 0x1d400, "LSHIFT_ADD.i32", ADD_SHIFT },
1141 { 0x1d800, "RSHIFT_SUB.i32", ADD_SHIFT },
1142 { 0x1dd18, "OR.i32", ADD_TWO_SRC },
1143 { 0x1dd20, "AND.i32", ADD_TWO_SRC },
1144 { 0x1dd60, "LSHIFT.i32", ADD_TWO_SRC },
1145 { 0x1dd50, "XOR.i32", ADD_TWO_SRC },
1146 { 0x1dd80, "RSHIFT.i32", ADD_TWO_SRC },
1147 { 0x1dda0, "ARSHIFT.i32", ADD_TWO_SRC },
1148 };
1149
1150 static struct add_op_info find_add_op_info(unsigned op)
1151 {
1152 for (unsigned i = 0; i < ARRAY_SIZE(add_op_infos); i++) {
1153 unsigned opCmp = ~0;
1154 switch (add_op_infos[i].src_type) {
1155 case ADD_ONE_SRC:
1156 case ADD_BLENDING:
1157 opCmp = op;
1158 break;
1159 case ADD_TWO_SRC:
1160 opCmp = op & ~0x7;
1161 break;
1162 case ADD_THREE_SRC:
1163 opCmp = op & ~0x3f;
1164 break;
1165 case ADD_SHIFT:
1166 opCmp = op & ~0x3ff;
1167 break;
1168 case ADD_TEX:
1169 opCmp = op & ~0xf;
1170 break;
1171 case ADD_FADD:
1172 case ADD_FMINMAX:
1173 case ADD_FADD16:
1174 opCmp = op & ~0x1fff;
1175 break;
1176 case ADD_FMINMAX16:
1177 case ADD_FADDMscale:
1178 opCmp = op & ~0xfff;
1179 break;
1180 case ADD_FCMP:
1181 case ADD_FCMP16:
1182 opCmp = op & ~0x7ff;
1183 break;
1184 case ADD_TEX_COMPACT:
1185 opCmp = op & ~0x3ff;
1186 break;
1187 case ADD_VARYING_INTERP:
1188 opCmp = op & ~0x7ff;
1189 break;
1190 case ADD_VARYING_ADDRESS:
1191 opCmp = op & ~0xfff;
1192 break;
1193 case ADD_LOAD_ATTR:
1194 case ADD_BRANCH:
1195 opCmp = op & ~0xfff;
1196 break;
1197 default:
1198 opCmp = ~0;
1199 break;
1200 }
1201 if (add_op_infos[i].op == opCmp)
1202 return add_op_infos[i];
1203 }
1204
1205 struct add_op_info info;
1206 snprintf(info.name, sizeof(info.name), "op%04x", op);
1207 info.op = op;
1208 info.src_type = ADD_TWO_SRC;
1209 info.has_data_reg = true;
1210 return info;
1211 }
1212
1213 static void dump_add(FILE *fp, uint64_t word, struct bifrost_regs regs,
1214 struct bifrost_regs next_regs, uint64_t *consts,
1215 unsigned data_reg, unsigned offset, bool verbose)
1216 {
1217 if (verbose) {
1218 fprintf(fp, "# ADD: %016" PRIx64 "\n", word);
1219 }
1220 struct bifrost_add_inst ADD;
1221 memcpy((char *) &ADD, (char *) &word, sizeof(ADD));
1222 struct add_op_info info = find_add_op_info(ADD.op);
1223
1224 fprintf(fp, "%s", info.name);
1225
1226 // float16 seems like it doesn't support output modifiers
1227 if (info.src_type == ADD_FADD || info.src_type == ADD_FMINMAX) {
1228 // output modifiers
1229 fprintf(fp, "%s", bi_output_mod_name(bits(ADD.op, 8, 10)));
1230 if (info.src_type == ADD_FADD)
1231 fprintf(fp, "%s", bi_round_mode_name(bits(ADD.op, 10, 12)));
1232 else
1233 fprintf(fp, "%s", bi_minmax_mode_name(bits(ADD.op, 10, 12)));
1234 } else if (info.src_type == ADD_FCMP || info.src_type == ADD_FCMP16) {
1235 dump_fcmp(fp, bits(ADD.op, 3, 6));
1236 if (info.src_type == ADD_FCMP)
1237 fprintf(fp, ".f32");
1238 else
1239 fprintf(fp, ".v2f16");
1240 } else if (info.src_type == ADD_FADDMscale) {
1241 switch ((ADD.op >> 6) & 0x7) {
1242 case 0:
1243 break;
1244 // causes GPU hangs on G71
1245 case 1:
1246 fprintf(fp, ".invalid");
1247 break;
1248 // Same as usual outmod value.
1249 case 2:
1250 fprintf(fp, ".clamp_0_1");
1251 break;
1252 // If src0 is infinite or NaN, flush it to zero so that the other
1253 // source is passed through unmodified.
1254 case 3:
1255 fprintf(fp, ".flush_src0_inf_nan");
1256 break;
1257 // Vice versa.
1258 case 4:
1259 fprintf(fp, ".flush_src1_inf_nan");
1260 break;
1261 // Every other case seems to behave the same as the above?
1262 default:
1263 fprintf(fp, ".unk%d", (ADD.op >> 6) & 0x7);
1264 break;
1265 }
1266 } else if (info.src_type == ADD_VARYING_INTERP) {
1267 if (ADD.op & 0x200)
1268 fprintf(fp, ".reuse");
1269 if (ADD.op & 0x400)
1270 fprintf(fp, ".flat");
1271 fprintf(fp, "%s", bi_interp_mode_name((ADD.op >> 7) & 0x3));
1272 fprintf(fp, ".v%d", ((ADD.op >> 5) & 0x3) + 1);
1273 } else if (info.src_type == ADD_BRANCH) {
1274 enum bifrost_branch_code branchCode = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1275 if (branchCode == BR_ALWAYS) {
1276 // unconditional branch
1277 } else {
1278 enum bifrost_branch_cond cond = (enum bifrost_branch_cond) ((ADD.op >> 6) & 0x7);
1279 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1280 bool portSwapped = (ADD.op & 0x7) < ADD.src0;
1281 // See the comment in branch_bit_size
1282 if (size == BR_SIZE_16YX0)
1283 portSwapped = true;
1284 if (size == BR_SIZE_16YX1)
1285 portSwapped = false;
1286 // These sizes are only for floating point comparisons, so the
1287 // non-floating-point comparisons are reused to encode the flipped
1288 // versions.
1289 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y)
1290 portSwapped = false;
1291 // There's only one argument, so we reuse the extra argument to
1292 // encode this.
1293 if (size == BR_SIZE_ZERO)
1294 portSwapped = !(ADD.op & 1);
1295
1296 switch (cond) {
1297 case BR_COND_LT:
1298 if (portSwapped)
1299 fprintf(fp, ".LT.u");
1300 else
1301 fprintf(fp, ".LT.i");
1302 break;
1303 case BR_COND_LE:
1304 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y) {
1305 fprintf(fp, ".UNE.f");
1306 } else {
1307 if (portSwapped)
1308 fprintf(fp, ".LE.u");
1309 else
1310 fprintf(fp, ".LE.i");
1311 }
1312 break;
1313 case BR_COND_GT:
1314 if (portSwapped)
1315 fprintf(fp, ".GT.u");
1316 else
1317 fprintf(fp, ".GT.i");
1318 break;
1319 case BR_COND_GE:
1320 if (portSwapped)
1321 fprintf(fp, ".GE.u");
1322 else
1323 fprintf(fp, ".GE.i");
1324 break;
1325 case BR_COND_EQ:
1326 if (portSwapped)
1327 fprintf(fp, ".NE.i");
1328 else
1329 fprintf(fp, ".EQ.i");
1330 break;
1331 case BR_COND_OEQ:
1332 if (portSwapped)
1333 fprintf(fp, ".UNE.f");
1334 else
1335 fprintf(fp, ".OEQ.f");
1336 break;
1337 case BR_COND_OGT:
1338 if (portSwapped)
1339 fprintf(fp, ".OGT.unk.f");
1340 else
1341 fprintf(fp, ".OGT.f");
1342 break;
1343 case BR_COND_OLT:
1344 if (portSwapped)
1345 fprintf(fp, ".OLT.unk.f");
1346 else
1347 fprintf(fp, ".OLT.f");
1348 break;
1349 }
1350 switch (size) {
1351 case BR_SIZE_32:
1352 case BR_SIZE_32_AND_16X:
1353 case BR_SIZE_32_AND_16Y:
1354 fprintf(fp, "32");
1355 break;
1356 case BR_SIZE_16XX:
1357 case BR_SIZE_16YY:
1358 case BR_SIZE_16YX0:
1359 case BR_SIZE_16YX1:
1360 fprintf(fp, "16");
1361 break;
1362 case BR_SIZE_ZERO: {
1363 unsigned ctrl = (ADD.op >> 1) & 0x3;
1364 if (ctrl == 0)
1365 fprintf(fp, "32.Z");
1366 else
1367 fprintf(fp, "16.Z");
1368 break;
1369 }
1370 }
1371 }
1372 } else if (info.src_type == ADD_SHIFT) {
1373 struct bifrost_shift_add shift;
1374 memcpy(&shift, &ADD, sizeof(ADD));
1375
1376 if (shift.invert_1)
1377 fprintf(fp, ".invert_1");
1378
1379 if (shift.invert_2)
1380 fprintf(fp, ".invert_2");
1381
1382 if (shift.zero)
1383 fprintf(fp, ".unk%u", shift.zero);
1384 } else if (info.src_type == ADD_VARYING_ADDRESS) {
1385 struct bifrost_ld_var_addr ld;
1386 memcpy(&ld, &ADD, sizeof(ADD));
1387 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1388 } else if (info.src_type == ADD_LOAD_ATTR) {
1389 struct bifrost_ld_attr ld;
1390 memcpy(&ld, &ADD, sizeof(ADD));
1391
1392 if (ld.channels)
1393 fprintf(fp, ".v%d%s", ld.channels + 1, bi_ldst_type_name(ld.type));
1394 else
1395 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1396 }
1397
1398 fprintf(fp, " ");
1399
1400 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
1401 if (next_ctrl.add_write_unit != REG_WRITE_NONE) {
1402 fprintf(fp, "{R%d, T1}, ", GetRegToWrite(next_ctrl.add_write_unit, next_regs));
1403 } else {
1404 fprintf(fp, "T1, ");
1405 }
1406
1407 switch (info.src_type) {
1408 case ADD_BLENDING:
1409 // Note: in this case, regs.uniform_const == location | 0x8
1410 // This probably means we can't load uniforms or immediates in the
1411 // same instruction. This re-uses the encoding that normally means
1412 // "disabled", where the low 4 bits are ignored. Perhaps the extra
1413 // 0x8 or'd in indicates this is happening.
1414 fprintf(fp, "location:%d, ", regs.uniform_const & 0x7);
1415 // fallthrough
1416 case ADD_ONE_SRC:
1417 dump_src(fp, ADD.src0, regs, consts, false);
1418 break;
1419 case ADD_TEX:
1420 case ADD_TEX_COMPACT: {
1421 int tex_index;
1422 int sampler_index;
1423 bool dualTex = false;
1424
1425 fprintf(fp, "coords <");
1426 dump_src(fp, ADD.src0, regs, consts, false);
1427 fprintf(fp, ", ");
1428 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1429 fprintf(fp, ">, ");
1430
1431 if (info.src_type == ADD_TEX_COMPACT) {
1432 tex_index = (ADD.op >> 3) & 0x7;
1433 sampler_index = (ADD.op >> 7) & 0x7;
1434 bool compute_lod = (ADD.op & 0x40);
1435 if (!compute_lod)
1436 fprintf(fp, "vtx lod 0 ");
1437 } else {
1438 uint64_t constVal = get_const(consts, regs);
1439 uint32_t controlBits = (ADD.op & 0x8) ? (constVal >> 32) : constVal;
1440 struct bifrost_tex_ctrl ctrl;
1441 memcpy((char *) &ctrl, (char *) &controlBits, sizeof(ctrl));
1442
1443 /* Dual-tex triggered for adjacent texturing
1444 * instructions with the same coordinates to different
1445 * textures/samplers. Observed for the compact
1446 * (2D/normal) case. */
1447
1448 if ((ctrl.result_type & 7) == 1) {
1449 bool f32 = ctrl.result_type & 8;
1450
1451 struct bifrost_dual_tex_ctrl dualCtrl;
1452 memcpy((char *) &dualCtrl, (char *) &controlBits, sizeof(ctrl));
1453 fprintf(fp, "(dualtex) tex0:%d samp0:%d tex1:%d samp1:%d %s",
1454 dualCtrl.tex_index0, dualCtrl.sampler_index0,
1455 dualCtrl.tex_index1, dualCtrl.sampler_index1,
1456 f32 ? "f32" : "f16");
1457 if (dualCtrl.unk0 != 3)
1458 fprintf(fp, "unk:%d ", dualCtrl.unk0);
1459 dualTex = true;
1460 } else {
1461 if (ctrl.no_merge_index) {
1462 tex_index = ctrl.tex_index;
1463 sampler_index = ctrl.sampler_index;
1464 } else {
1465 tex_index = sampler_index = ctrl.tex_index;
1466 unsigned unk = ctrl.sampler_index >> 2;
1467 if (unk != 3)
1468 fprintf(fp, "unk:%d ", unk);
1469 if (ctrl.sampler_index & 1)
1470 tex_index = -1;
1471 if (ctrl.sampler_index & 2)
1472 sampler_index = -1;
1473 }
1474
1475 if (ctrl.unk0 != 3)
1476 fprintf(fp, "unk0:%d ", ctrl.unk0);
1477 if (ctrl.unk1)
1478 fprintf(fp, "unk1 ");
1479 if (ctrl.unk2 != 0xf)
1480 fprintf(fp, "unk2:%x ", ctrl.unk2);
1481
1482 switch (ctrl.result_type) {
1483 case 0x4:
1484 fprintf(fp, "f32 ");
1485 break;
1486 case 0xe:
1487 fprintf(fp, "i32 ");
1488 break;
1489 case 0xf:
1490 fprintf(fp, "u32 ");
1491 break;
1492 default:
1493 fprintf(fp, "unktype(%x) ", ctrl.result_type);
1494 }
1495
1496 switch (ctrl.tex_type) {
1497 case 0:
1498 fprintf(fp, "cube ");
1499 break;
1500 case 1:
1501 fprintf(fp, "buffer ");
1502 break;
1503 case 2:
1504 fprintf(fp, "2D ");
1505 break;
1506 case 3:
1507 fprintf(fp, "3D ");
1508 break;
1509 }
1510
1511 if (ctrl.is_shadow)
1512 fprintf(fp, "shadow ");
1513 if (ctrl.is_array)
1514 fprintf(fp, "array ");
1515
1516 if (!ctrl.filter) {
1517 if (ctrl.calc_gradients) {
1518 int comp = (controlBits >> 20) & 0x3;
1519 fprintf(fp, "txg comp:%d ", comp);
1520 } else {
1521 fprintf(fp, "txf ");
1522 }
1523 } else {
1524 if (!ctrl.not_supply_lod) {
1525 if (ctrl.compute_lod)
1526 fprintf(fp, "lod_bias ");
1527 else
1528 fprintf(fp, "lod ");
1529 }
1530
1531 if (!ctrl.calc_gradients)
1532 fprintf(fp, "grad ");
1533 }
1534
1535 if (ctrl.texel_offset)
1536 fprintf(fp, "offset ");
1537 }
1538 }
1539
1540 if (!dualTex) {
1541 if (tex_index == -1)
1542 fprintf(fp, "tex:indirect ");
1543 else
1544 fprintf(fp, "tex:%d ", tex_index);
1545
1546 if (sampler_index == -1)
1547 fprintf(fp, "samp:indirect ");
1548 else
1549 fprintf(fp, "samp:%d ", sampler_index);
1550 }
1551 break;
1552 }
1553 case ADD_VARYING_INTERP: {
1554 unsigned addr = ADD.op & 0x1f;
1555 if (addr < 0b10100) {
1556 // direct addr
1557 fprintf(fp, "%d", addr);
1558 } else if (addr < 0b11000) {
1559 if (addr == 22)
1560 fprintf(fp, "fragw");
1561 else if (addr == 23)
1562 fprintf(fp, "fragz");
1563 else
1564 fprintf(fp, "unk%d", addr);
1565 } else {
1566 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1567 }
1568 fprintf(fp, ", ");
1569 dump_src(fp, ADD.src0, regs, consts, false);
1570 break;
1571 }
1572 case ADD_VARYING_ADDRESS: {
1573 dump_src(fp, ADD.src0, regs, consts, false);
1574 fprintf(fp, ", ");
1575 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1576 fprintf(fp, ", ");
1577 unsigned location = (ADD.op >> 3) & 0x1f;
1578 if (location < 16) {
1579 fprintf(fp, "location:%d", location);
1580 } else if (location == 20) {
1581 fprintf(fp, "location:%u", (uint32_t) get_const(consts, regs));
1582 } else if (location == 21) {
1583 fprintf(fp, "location:%u", (uint32_t) (get_const(consts, regs) >> 32));
1584 } else {
1585 fprintf(fp, "location:%d(unk)", location);
1586 }
1587 break;
1588 }
1589 case ADD_LOAD_ATTR:
1590 fprintf(fp, "location:%d, ", (ADD.op >> 3) & 0x1f);
1591 case ADD_TWO_SRC:
1592 dump_src(fp, ADD.src0, regs, consts, false);
1593 fprintf(fp, ", ");
1594 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1595 break;
1596 case ADD_THREE_SRC:
1597 dump_src(fp, ADD.src0, regs, consts, false);
1598 fprintf(fp, ", ");
1599 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1600 fprintf(fp, ", ");
1601 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1602 break;
1603 case ADD_SHIFT: {
1604 struct bifrost_shift_add shift;
1605 memcpy(&shift, &ADD, sizeof(ADD));
1606 dump_src(fp, shift.src0, regs, consts, false);
1607 fprintf(fp, ", ");
1608 dump_src(fp, shift.src1, regs, consts, false);
1609 fprintf(fp, ", ");
1610 dump_src(fp, shift.src2, regs, consts, false);
1611 break;
1612 }
1613 case ADD_FADD:
1614 case ADD_FMINMAX:
1615 if (ADD.op & 0x10)
1616 fprintf(fp, "-");
1617 if (ADD.op & 0x1000)
1618 fprintf(fp, "abs(");
1619 dump_src(fp, ADD.src0, regs, consts, false);
1620 switch ((ADD.op >> 6) & 0x3) {
1621 case 3:
1622 fprintf(fp, ".x");
1623 break;
1624 default:
1625 break;
1626 }
1627 if (ADD.op & 0x1000)
1628 fprintf(fp, ")");
1629 fprintf(fp, ", ");
1630 if (ADD.op & 0x20)
1631 fprintf(fp, "-");
1632 if (ADD.op & 0x8)
1633 fprintf(fp, "abs(");
1634 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1635 switch ((ADD.op >> 6) & 0x3) {
1636 case 1:
1637 case 3:
1638 fprintf(fp, ".x");
1639 break;
1640 case 2:
1641 fprintf(fp, ".y");
1642 break;
1643 case 0:
1644 break;
1645 default:
1646 fprintf(fp, ".unk");
1647 break;
1648 }
1649 if (ADD.op & 0x8)
1650 fprintf(fp, ")");
1651 break;
1652 case ADD_FADD16:
1653 if (ADD.op & 0x10)
1654 fprintf(fp, "-");
1655 if (ADD.op & 0x1000)
1656 fprintf(fp, "abs(");
1657 dump_src(fp, ADD.src0, regs, consts, false);
1658 if (ADD.op & 0x1000)
1659 fprintf(fp, ")");
1660 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1661 fprintf(fp, ", ");
1662 if (ADD.op & 0x20)
1663 fprintf(fp, "-");
1664 if (ADD.op & 0x8)
1665 fprintf(fp, "abs(");
1666 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1667 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1668 if (ADD.op & 0x8)
1669 fprintf(fp, ")");
1670 break;
1671 case ADD_FMINMAX16: {
1672 bool abs1 = ADD.op & 0x8;
1673 bool abs2 = (ADD.op & 0x7) < ADD.src0;
1674 if (ADD.op & 0x10)
1675 fprintf(fp, "-");
1676 if (abs1 || abs2)
1677 fprintf(fp, "abs(");
1678 dump_src(fp, ADD.src0, regs, consts, false);
1679 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1680 if (abs1 || abs2)
1681 fprintf(fp, ")");
1682 fprintf(fp, ", ");
1683 if (ADD.op & 0x20)
1684 fprintf(fp, "-");
1685 if (abs1 && abs2)
1686 fprintf(fp, "abs(");
1687 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1688 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1689 if (abs1 && abs2)
1690 fprintf(fp, ")");
1691 fprintf(fp, "/* %X */\n", (ADD.op >> 10) & 0x3); /* mode */
1692 break;
1693 }
1694 case ADD_FADDMscale: {
1695 if (ADD.op & 0x400)
1696 fprintf(fp, "-");
1697 if (ADD.op & 0x200)
1698 fprintf(fp, "abs(");
1699 dump_src(fp, ADD.src0, regs, consts, false);
1700 if (ADD.op & 0x200)
1701 fprintf(fp, ")");
1702
1703 fprintf(fp, ", ");
1704
1705 if (ADD.op & 0x800)
1706 fprintf(fp, "-");
1707 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1708
1709 fprintf(fp, ", ");
1710
1711 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1712 break;
1713 }
1714 case ADD_FCMP:
1715 if (ADD.op & 0x400) {
1716 fprintf(fp, "-");
1717 }
1718 if (ADD.op & 0x100) {
1719 fprintf(fp, "abs(");
1720 }
1721 dump_src(fp, ADD.src0, regs, consts, false);
1722 switch ((ADD.op >> 6) & 0x3) {
1723 case 3:
1724 fprintf(fp, ".x");
1725 break;
1726 default:
1727 break;
1728 }
1729 if (ADD.op & 0x100) {
1730 fprintf(fp, ")");
1731 }
1732 fprintf(fp, ", ");
1733 if (ADD.op & 0x200) {
1734 fprintf(fp, "abs(");
1735 }
1736 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1737 switch ((ADD.op >> 6) & 0x3) {
1738 case 1:
1739 case 3:
1740 fprintf(fp, ".x");
1741 break;
1742 case 2:
1743 fprintf(fp, ".y");
1744 break;
1745 case 0:
1746 break;
1747 default:
1748 fprintf(fp, ".unk");
1749 break;
1750 }
1751 if (ADD.op & 0x200) {
1752 fprintf(fp, ")");
1753 }
1754 break;
1755 case ADD_FCMP16:
1756 dump_src(fp, ADD.src0, regs, consts, false);
1757 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1758 fprintf(fp, ", ");
1759 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1760 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1761 break;
1762 case ADD_BRANCH: {
1763 enum bifrost_branch_code code = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1764 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1765 if (code != BR_ALWAYS) {
1766 dump_src(fp, ADD.src0, regs, consts, false);
1767 switch (size) {
1768 case BR_SIZE_16XX:
1769 fprintf(fp, ".x");
1770 break;
1771 case BR_SIZE_16YY:
1772 case BR_SIZE_16YX0:
1773 case BR_SIZE_16YX1:
1774 fprintf(fp, ".y");
1775 break;
1776 case BR_SIZE_ZERO: {
1777 unsigned ctrl = (ADD.op >> 1) & 0x3;
1778 switch (ctrl) {
1779 case 1:
1780 fprintf(fp, ".y");
1781 break;
1782 case 2:
1783 fprintf(fp, ".x");
1784 break;
1785 default:
1786 break;
1787 }
1788 }
1789 default:
1790 break;
1791 }
1792 fprintf(fp, ", ");
1793 }
1794 if (code != BR_ALWAYS && size != BR_SIZE_ZERO) {
1795 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1796 switch (size) {
1797 case BR_SIZE_16XX:
1798 case BR_SIZE_16YX0:
1799 case BR_SIZE_16YX1:
1800 case BR_SIZE_32_AND_16X:
1801 fprintf(fp, ".x");
1802 break;
1803 case BR_SIZE_16YY:
1804 case BR_SIZE_32_AND_16Y:
1805 fprintf(fp, ".y");
1806 break;
1807 default:
1808 break;
1809 }
1810 fprintf(fp, ", ");
1811 }
1812 // I haven't had the chance to test if this actually specifies the
1813 // branch offset, since I couldn't get it to produce values other
1814 // than 5 (uniform/const high), but these three bits are always
1815 // consistent across branch instructions, so it makes sense...
1816 int offsetSrc = (ADD.op >> 3) & 0x7;
1817 if (offsetSrc == 4 || offsetSrc == 5) {
1818 // If the offset is known/constant, we can decode it
1819 uint32_t raw_offset;
1820 if (offsetSrc == 4)
1821 raw_offset = get_const(consts, regs);
1822 else
1823 raw_offset = get_const(consts, regs) >> 32;
1824 // The high 4 bits are flags, while the rest is the
1825 // twos-complement offset in bytes (here we convert to
1826 // clauses).
1827 int32_t branch_offset = ((int32_t) raw_offset << 4) >> 8;
1828
1829 // If high4 is the high 4 bits of the last 64-bit constant,
1830 // this is calculated as (high4 + 4) & 0xf, or 0 if the branch
1831 // offset itself is the last constant. Not sure if this is
1832 // actually used, or just garbage in unused bits, but in any
1833 // case, we can just ignore it here since it's redundant. Note
1834 // that if there is any padding, this will be 4 since the
1835 // padding counts as the last constant.
1836 unsigned flags = raw_offset >> 28;
1837 (void) flags;
1838
1839 // Note: the offset is in bytes, relative to the beginning of the
1840 // current clause, so a zero offset would be a loop back to the
1841 // same clause (annoyingly different from Midgard).
1842 fprintf(fp, "clause_%d", offset + branch_offset);
1843 } else {
1844 dump_src(fp, offsetSrc, regs, consts, false);
1845 }
1846 }
1847 }
1848 if (info.has_data_reg) {
1849 fprintf(fp, ", R%d", data_reg);
1850 }
1851 fprintf(fp, "\n");
1852 }
1853
1854 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
1855 struct bifrost_regs next_regs, uint64_t *consts,
1856 unsigned data_reg, unsigned offset, bool verbose)
1857 {
1858 struct bifrost_regs regs;
1859 memcpy((char *) &regs, (char *) &instr->reg_bits, sizeof(regs));
1860
1861 if (verbose) {
1862 fprintf(fp, "# regs: %016" PRIx64 "\n", instr->reg_bits);
1863 dump_regs(fp, regs);
1864 }
1865 dump_fma(fp, instr->fma_bits, regs, next_regs, consts, verbose);
1866 dump_add(fp, instr->add_bits, regs, next_regs, consts, data_reg, offset, verbose);
1867 }
1868
1869 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose)
1870 {
1871 // State for a decoded clause
1872 struct bifrost_alu_inst instrs[8] = {};
1873 uint64_t consts[6] = {};
1874 unsigned num_instrs = 0;
1875 unsigned num_consts = 0;
1876 uint64_t header_bits = 0;
1877 bool stopbit = false;
1878
1879 unsigned i;
1880 for (i = 0; ; i++, words += 4) {
1881 if (verbose) {
1882 fprintf(fp, "# ");
1883 for (int j = 0; j < 4; j++)
1884 fprintf(fp, "%08x ", words[3 - j]); // low bit on the right
1885 fprintf(fp, "\n");
1886 }
1887 unsigned tag = bits(words[0], 0, 8);
1888
1889 // speculatively decode some things that are common between many formats, so we can share some code
1890 struct bifrost_alu_inst main_instr = {};
1891 // 20 bits
1892 main_instr.add_bits = bits(words[2], 2, 32 - 13);
1893 // 23 bits
1894 main_instr.fma_bits = bits(words[1], 11, 32) | bits(words[2], 0, 2) << (32 - 11);
1895 // 35 bits
1896 main_instr.reg_bits = ((uint64_t) bits(words[1], 0, 11)) << 24 | (uint64_t) bits(words[0], 8, 32);
1897
1898 uint64_t const0 = bits(words[0], 8, 32) << 4 | (uint64_t) words[1] << 28 | bits(words[2], 0, 4) << 60;
1899 uint64_t const1 = bits(words[2], 4, 32) << 4 | (uint64_t) words[3] << 32;
1900
1901 bool stop = tag & 0x40;
1902
1903 if (verbose) {
1904 fprintf(fp, "# tag: 0x%02x\n", tag);
1905 }
1906 if (tag & 0x80) {
1907 unsigned idx = stop ? 5 : 2;
1908 main_instr.add_bits |= ((tag >> 3) & 0x7) << 17;
1909 instrs[idx + 1] = main_instr;
1910 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17);
1911 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10;
1912 consts[0] = bits(words[3], 17, 32) << 4;
1913 } else {
1914 bool done = false;
1915 switch ((tag >> 3) & 0x7) {
1916 case 0x0:
1917 switch (tag & 0x7) {
1918 case 0x3:
1919 main_instr.add_bits |= bits(words[3], 29, 32) << 17;
1920 instrs[1] = main_instr;
1921 num_instrs = 2;
1922 done = stop;
1923 break;
1924 case 0x4:
1925 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1926 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1927 consts[0] = const0;
1928 num_instrs = 3;
1929 num_consts = 1;
1930 done = stop;
1931 break;
1932 case 0x1:
1933 case 0x5:
1934 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1935 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1936 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1937 instrs[3] = main_instr;
1938 if ((tag & 0x7) == 0x5) {
1939 num_instrs = 4;
1940 done = stop;
1941 }
1942 break;
1943 case 0x6:
1944 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1945 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1946 consts[0] = const0;
1947 num_instrs = 6;
1948 num_consts = 1;
1949 done = stop;
1950 break;
1951 case 0x7:
1952 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1953 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1954 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1955 instrs[6] = main_instr;
1956 num_instrs = 7;
1957 done = stop;
1958 break;
1959 default:
1960 fprintf(fp, "unknown tag bits 0x%02x\n", tag);
1961 }
1962 break;
1963 case 0x2:
1964 case 0x3: {
1965 unsigned idx = ((tag >> 3) & 0x7) == 2 ? 4 : 7;
1966 main_instr.add_bits |= (tag & 0x7) << 17;
1967 instrs[idx] = main_instr;
1968 consts[0] |= (bits(words[2], 19, 32) | ((uint64_t) words[3] << 13)) << 19;
1969 num_consts = 1;
1970 num_instrs = idx + 1;
1971 done = stop;
1972 break;
1973 }
1974 case 0x4: {
1975 unsigned idx = stop ? 4 : 1;
1976 main_instr.add_bits |= (tag & 0x7) << 17;
1977 instrs[idx] = main_instr;
1978 instrs[idx + 1].fma_bits |= bits(words[3], 22, 32);
1979 instrs[idx + 1].reg_bits = bits(words[2], 19, 32) | (bits(words[3], 0, 22) << (32 - 19));
1980 break;
1981 }
1982 case 0x1:
1983 // only constants can come after this
1984 num_instrs = 1;
1985 done = stop;
1986 case 0x5:
1987 header_bits = bits(words[2], 19, 32) | ((uint64_t) words[3] << (32 - 19));
1988 main_instr.add_bits |= (tag & 0x7) << 17;
1989 instrs[0] = main_instr;
1990 break;
1991 case 0x6:
1992 case 0x7: {
1993 unsigned pos = tag & 0xf;
1994 // note that `pos' encodes both the total number of
1995 // instructions and the position in the constant stream,
1996 // presumably because decoded constants and instructions
1997 // share a buffer in the decoder, but we only care about
1998 // the position in the constant stream; the total number of
1999 // instructions is redundant.
2000 unsigned const_idx = 0;
2001 switch (pos) {
2002 case 0:
2003 case 1:
2004 case 2:
2005 case 6:
2006 const_idx = 0;
2007 break;
2008 case 3:
2009 case 4:
2010 case 7:
2011 case 9:
2012 const_idx = 1;
2013 break;
2014 case 5:
2015 case 0xa:
2016 const_idx = 2;
2017 break;
2018 case 8:
2019 case 0xb:
2020 case 0xc:
2021 const_idx = 3;
2022 break;
2023 case 0xd:
2024 const_idx = 4;
2025 break;
2026 default:
2027 fprintf(fp, "# unknown pos 0x%x\n", pos);
2028 break;
2029 }
2030
2031 if (num_consts < const_idx + 2)
2032 num_consts = const_idx + 2;
2033
2034 consts[const_idx] = const0;
2035 consts[const_idx + 1] = const1;
2036 done = stop;
2037 break;
2038 }
2039 default:
2040 break;
2041 }
2042
2043 if (done)
2044 break;
2045 }
2046 }
2047
2048 *size = i + 1;
2049
2050 if (verbose) {
2051 fprintf(fp, "# header: %012" PRIx64 "\n", header_bits);
2052 }
2053
2054 struct bifrost_header header;
2055 memcpy((char *) &header, (char *) &header_bits, sizeof(struct bifrost_header));
2056 dump_header(fp, header, verbose);
2057 if (!header.no_end_of_shader)
2058 stopbit = true;
2059
2060 fprintf(fp, "{\n");
2061 for (i = 0; i < num_instrs; i++) {
2062 struct bifrost_regs next_regs;
2063 if (i + 1 == num_instrs) {
2064 memcpy((char *) &next_regs, (char *) &instrs[0].reg_bits,
2065 sizeof(next_regs));
2066 } else {
2067 memcpy((char *) &next_regs, (char *) &instrs[i + 1].reg_bits,
2068 sizeof(next_regs));
2069 }
2070
2071 dump_instr(fp, &instrs[i], next_regs, consts, header.datareg, offset, verbose);
2072 }
2073 fprintf(fp, "}\n");
2074
2075 if (verbose) {
2076 for (unsigned i = 0; i < num_consts; i++) {
2077 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i, consts[i] & 0xffffffff);
2078 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i + 1, consts[i] >> 32);
2079 }
2080 }
2081 return stopbit;
2082 }
2083
2084 void disassemble_bifrost(FILE *fp, uint8_t *code, size_t size, bool verbose)
2085 {
2086 uint32_t *words = (uint32_t *) code;
2087 uint32_t *words_end = words + (size / 4);
2088 // used for displaying branch targets
2089 unsigned offset = 0;
2090 while (words != words_end) {
2091 // we don't know what the program-end bit is quite yet, so for now just
2092 // assume that an all-0 quadword is padding
2093 uint32_t zero[4] = {};
2094 if (memcmp(words, zero, 4 * sizeof(uint32_t)) == 0)
2095 break;
2096 fprintf(fp, "clause_%d:\n", offset);
2097 unsigned size;
2098 if (dump_clause(fp, words, &size, offset, verbose) == true) {
2099 break;
2100 }
2101 words += size * 4;
2102 offset += size;
2103 }
2104 }
2105