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pan/bi: Gut old compiler
[mesa.git] / src / panfrost / bifrost / disassemble.c
1 /*
2 * Copyright (C) 2019 Connor Abbott <cwabbott0@gmail.com>
3 * Copyright (C) 2019 Lyude Paul <thatslyude@gmail.com>
4 * Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #include <stdbool.h>
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <assert.h>
30 #include <inttypes.h>
31 #include <string.h>
32
33 #include "bifrost.h"
34 #include "disassemble.h"
35 #include "util/macros.h"
36
37 // return bits (high, lo]
38 static uint64_t bits(uint32_t word, unsigned lo, unsigned high)
39 {
40 if (high == 32)
41 return word >> lo;
42 return (word & ((1 << high) - 1)) >> lo;
43 }
44
45 // each of these structs represents an instruction that's dispatched in one
46 // cycle. Note that these instructions are packed in funny ways within the
47 // clause, hence the need for a separate struct.
48 struct bifrost_alu_inst {
49 uint32_t fma_bits;
50 uint32_t add_bits;
51 uint64_t reg_bits;
52 };
53
54 static unsigned get_reg0(struct bifrost_regs regs)
55 {
56 if (regs.ctrl == 0)
57 return regs.reg0 | ((regs.reg1 & 0x1) << 5);
58
59 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0;
60 }
61
62 static unsigned get_reg1(struct bifrost_regs regs)
63 {
64 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1;
65 }
66
67 // this represents the decoded version of the ctrl register field.
68 struct bifrost_reg_ctrl {
69 bool read_reg0;
70 bool read_reg1;
71 bool read_reg3;
72 enum bifrost_reg_write_unit fma_write_unit;
73 enum bifrost_reg_write_unit add_write_unit;
74 bool clause_start;
75 };
76
77 enum fma_src_type {
78 FMA_ONE_SRC,
79 FMA_TWO_SRC,
80 FMA_FADD,
81 FMA_FMINMAX,
82 FMA_FADD16,
83 FMA_FMINMAX16,
84 FMA_FCMP,
85 FMA_FCMP16,
86 FMA_THREE_SRC,
87 FMA_SHIFT,
88 FMA_FMA,
89 FMA_FMA16,
90 FMA_CSEL4,
91 FMA_FMA_MSCALE,
92 FMA_SHIFT_ADD64,
93 };
94
95 struct fma_op_info {
96 bool extended;
97 unsigned op;
98 char name[30];
99 enum fma_src_type src_type;
100 };
101
102 enum add_src_type {
103 ADD_ONE_SRC,
104 ADD_TWO_SRC,
105 ADD_FADD,
106 ADD_FMINMAX,
107 ADD_FADD16,
108 ADD_FMINMAX16,
109 ADD_THREE_SRC,
110 ADD_SHIFT,
111 ADD_FADDMscale,
112 ADD_FCMP,
113 ADD_FCMP16,
114 ADD_TEX_COMPACT, // texture instruction with embedded sampler
115 ADD_TEX, // texture instruction with sampler/etc. in uniform port
116 ADD_VARYING_INTERP,
117 ADD_BLENDING,
118 ADD_LOAD_ATTR,
119 ADD_VARYING_ADDRESS,
120 ADD_BRANCH,
121 };
122
123 struct add_op_info {
124 unsigned op;
125 char name[30];
126 enum add_src_type src_type;
127 bool has_data_reg;
128 };
129
130 void dump_header(FILE *fp, struct bifrost_header header, bool verbose);
131 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
132 struct bifrost_regs next_regs, uint64_t *consts,
133 unsigned data_reg, unsigned offset, bool verbose);
134 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose);
135
136 void dump_header(FILE *fp, struct bifrost_header header, bool verbose)
137 {
138 if (header.clause_type != 0) {
139 fprintf(fp, "id(%du) ", header.scoreboard_index);
140 }
141
142 if (header.scoreboard_deps != 0) {
143 fprintf(fp, "next-wait(");
144 bool first = true;
145 for (unsigned i = 0; i < 8; i++) {
146 if (header.scoreboard_deps & (1 << i)) {
147 if (!first) {
148 fprintf(fp, ", ");
149 }
150 fprintf(fp, "%d", i);
151 first = false;
152 }
153 }
154 fprintf(fp, ") ");
155 }
156
157 if (header.datareg_writebarrier)
158 fprintf(fp, "data-reg-barrier ");
159
160 if (!header.no_end_of_shader)
161 fprintf(fp, "eos ");
162
163 if (!header.back_to_back) {
164 fprintf(fp, "nbb ");
165 if (header.branch_cond)
166 fprintf(fp, "branch-cond ");
167 else
168 fprintf(fp, "branch-uncond ");
169 }
170
171 if (header.elide_writes)
172 fprintf(fp, "we ");
173
174 if (header.suppress_inf)
175 fprintf(fp, "suppress-inf ");
176 if (header.suppress_nan)
177 fprintf(fp, "suppress-nan ");
178
179 if (header.unk0)
180 fprintf(fp, "unk0 ");
181 if (header.unk1)
182 fprintf(fp, "unk1 ");
183 if (header.unk2)
184 fprintf(fp, "unk2 ");
185 if (header.unk3)
186 fprintf(fp, "unk3 ");
187 if (header.unk4)
188 fprintf(fp, "unk4 ");
189
190 fprintf(fp, "\n");
191
192 if (verbose) {
193 fprintf(fp, "# clause type %d, next clause type %d\n",
194 header.clause_type, header.next_clause_type);
195 }
196 }
197
198 static struct bifrost_reg_ctrl DecodeRegCtrl(FILE *fp, struct bifrost_regs regs)
199 {
200 struct bifrost_reg_ctrl decoded = {};
201 unsigned ctrl;
202 if (regs.ctrl == 0) {
203 ctrl = regs.reg1 >> 2;
204 decoded.read_reg0 = !(regs.reg1 & 0x2);
205 decoded.read_reg1 = false;
206 } else {
207 ctrl = regs.ctrl;
208 decoded.read_reg0 = decoded.read_reg1 = true;
209 }
210 switch (ctrl) {
211 case 1:
212 decoded.fma_write_unit = REG_WRITE_TWO;
213 break;
214 case 2:
215 case 3:
216 decoded.fma_write_unit = REG_WRITE_TWO;
217 decoded.read_reg3 = true;
218 break;
219 case 4:
220 decoded.read_reg3 = true;
221 break;
222 case 5:
223 decoded.add_write_unit = REG_WRITE_TWO;
224 break;
225 case 6:
226 decoded.add_write_unit = REG_WRITE_TWO;
227 decoded.read_reg3 = true;
228 break;
229 case 8:
230 decoded.clause_start = true;
231 break;
232 case 9:
233 decoded.fma_write_unit = REG_WRITE_TWO;
234 decoded.clause_start = true;
235 break;
236 case 11:
237 break;
238 case 12:
239 decoded.read_reg3 = true;
240 decoded.clause_start = true;
241 break;
242 case 13:
243 decoded.add_write_unit = REG_WRITE_TWO;
244 decoded.clause_start = true;
245 break;
246
247 case 7:
248 case 15:
249 decoded.fma_write_unit = REG_WRITE_THREE;
250 decoded.add_write_unit = REG_WRITE_TWO;
251 break;
252 default:
253 fprintf(fp, "# unknown reg ctrl %d\n", ctrl);
254 }
255
256 return decoded;
257 }
258
259 // Pass in the add_write_unit or fma_write_unit, and this returns which register
260 // the ADD/FMA units are writing to
261 static unsigned GetRegToWrite(enum bifrost_reg_write_unit unit, struct bifrost_regs regs)
262 {
263 switch (unit) {
264 case REG_WRITE_TWO:
265 return regs.reg2;
266 case REG_WRITE_THREE:
267 return regs.reg3;
268 default: /* REG_WRITE_NONE */
269 assert(0);
270 return 0;
271 }
272 }
273
274 static void dump_regs(FILE *fp, struct bifrost_regs srcs)
275 {
276 struct bifrost_reg_ctrl ctrl = DecodeRegCtrl(fp, srcs);
277 fprintf(fp, "# ");
278 if (ctrl.read_reg0)
279 fprintf(fp, "port 0: R%d ", get_reg0(srcs));
280 if (ctrl.read_reg1)
281 fprintf(fp, "port 1: R%d ", get_reg1(srcs));
282
283 if (ctrl.fma_write_unit == REG_WRITE_TWO)
284 fprintf(fp, "port 2: R%d (write FMA) ", srcs.reg2);
285 else if (ctrl.add_write_unit == REG_WRITE_TWO)
286 fprintf(fp, "port 2: R%d (write ADD) ", srcs.reg2);
287
288 if (ctrl.fma_write_unit == REG_WRITE_THREE)
289 fprintf(fp, "port 3: R%d (write FMA) ", srcs.reg3);
290 else if (ctrl.add_write_unit == REG_WRITE_THREE)
291 fprintf(fp, "port 3: R%d (write ADD) ", srcs.reg3);
292 else if (ctrl.read_reg3)
293 fprintf(fp, "port 3: R%d (read) ", srcs.reg3);
294
295 if (srcs.uniform_const) {
296 if (srcs.uniform_const & 0x80) {
297 fprintf(fp, "uniform: U%d", (srcs.uniform_const & 0x7f) * 2);
298 }
299 }
300
301 fprintf(fp, "\n");
302 }
303 static void dump_const_imm(FILE *fp, uint32_t imm)
304 {
305 union {
306 float f;
307 uint32_t i;
308 } fi;
309 fi.i = imm;
310 fprintf(fp, "0x%08x /* %f */", imm, fi.f);
311 }
312
313 static uint64_t get_const(uint64_t *consts, struct bifrost_regs srcs)
314 {
315 unsigned low_bits = srcs.uniform_const & 0xf;
316 uint64_t imm;
317 switch (srcs.uniform_const >> 4) {
318 case 4:
319 imm = consts[0];
320 break;
321 case 5:
322 imm = consts[1];
323 break;
324 case 6:
325 imm = consts[2];
326 break;
327 case 7:
328 imm = consts[3];
329 break;
330 case 2:
331 imm = consts[4];
332 break;
333 case 3:
334 imm = consts[5];
335 break;
336 default:
337 assert(0);
338 break;
339 }
340 return imm | low_bits;
341 }
342
343 static void dump_uniform_const_src(FILE *fp, struct bifrost_regs srcs, uint64_t *consts, bool high32)
344 {
345 if (srcs.uniform_const & 0x80) {
346 unsigned uniform = (srcs.uniform_const & 0x7f) * 2;
347 fprintf(fp, "U%d", uniform + (high32 ? 1 : 0));
348 } else if (srcs.uniform_const >= 0x20) {
349 uint64_t imm = get_const(consts, srcs);
350 if (high32)
351 dump_const_imm(fp, imm >> 32);
352 else
353 dump_const_imm(fp, imm);
354 } else {
355 switch (srcs.uniform_const) {
356 case 0:
357 fprintf(fp, "0");
358 break;
359 case 5:
360 fprintf(fp, "atest-data");
361 break;
362 case 6:
363 fprintf(fp, "sample-ptr");
364 break;
365 case 8:
366 case 9:
367 case 10:
368 case 11:
369 case 12:
370 case 13:
371 case 14:
372 case 15:
373 fprintf(fp, "blend-descriptor%u", (unsigned) srcs.uniform_const - 8);
374 break;
375 default:
376 fprintf(fp, "unkConst%u", (unsigned) srcs.uniform_const);
377 break;
378 }
379
380 if (high32)
381 fprintf(fp, ".y");
382 else
383 fprintf(fp, ".x");
384 }
385 }
386
387 static void dump_src(FILE *fp, unsigned src, struct bifrost_regs srcs, uint64_t *consts, bool isFMA)
388 {
389 switch (src) {
390 case 0:
391 fprintf(fp, "R%d", get_reg0(srcs));
392 break;
393 case 1:
394 fprintf(fp, "R%d", get_reg1(srcs));
395 break;
396 case 2:
397 fprintf(fp, "R%d", srcs.reg3);
398 break;
399 case 3:
400 if (isFMA)
401 fprintf(fp, "0");
402 else
403 fprintf(fp, "T"); // i.e. the output of FMA this cycle
404 break;
405 case 4:
406 dump_uniform_const_src(fp, srcs, consts, false);
407 break;
408 case 5:
409 dump_uniform_const_src(fp, srcs, consts, true);
410 break;
411 case 6:
412 fprintf(fp, "T0");
413 break;
414 case 7:
415 fprintf(fp, "T1");
416 break;
417 }
418 }
419
420 static void dump_output_mod(FILE *fp, unsigned mod)
421 {
422 switch (mod) {
423 case BIFROST_NONE:
424 break;
425 case BIFROST_POS:
426 fprintf(fp, ".clamp_0_inf");
427 break; // max(out, 0)
428 case BIFROST_SAT_SIGNED:
429 fprintf(fp, ".clamp_m1_1");
430 break; // clamp(out, -1, 1)
431 case BIFROST_SAT:
432 fprintf(fp, ".clamp_0_1");
433 break; // clamp(out, 0, 1)
434 default:
435 break;
436 }
437 }
438
439 static void dump_minmax_mode(FILE *fp, unsigned mod)
440 {
441 switch (mod) {
442 case 0:
443 /* Same as fmax() and fmin() -- return the other number if any
444 * number is NaN. Also always return +0 if one argument is +0 and
445 * the other is -0.
446 */
447 break;
448 case 1:
449 /* Instead of never returning a NaN, always return one. The
450 * "greater"/"lesser" NaN is always returned, first by checking the
451 * sign and then the mantissa bits.
452 */
453 fprintf(fp, ".nan_wins");
454 break;
455 case 2:
456 /* For max, implement src0 > src1 ? src0 : src1
457 * For min, implement src0 < src1 ? src0 : src1
458 *
459 * This includes handling NaN's and signedness of 0 differently
460 * from above, since +0 and -0 compare equal and comparisons always
461 * return false for NaN's. As a result, this mode is *not*
462 * commutative.
463 */
464 fprintf(fp, ".src1_wins");
465 break;
466 case 3:
467 /* For max, implement src0 < src1 ? src1 : src0
468 * For min, implement src0 > src1 ? src1 : src0
469 */
470 fprintf(fp, ".src0_wins");
471 break;
472 default:
473 break;
474 }
475 }
476
477 static void dump_round_mode(FILE *fp, unsigned mod)
478 {
479 switch (mod) {
480 case BIFROST_RTE:
481 /* roundTiesToEven, the IEEE default. */
482 break;
483 case BIFROST_RTP:
484 /* roundTowardPositive in the IEEE spec. */
485 fprintf(fp, ".round_pos");
486 break;
487 case BIFROST_RTN:
488 /* roundTowardNegative in the IEEE spec. */
489 fprintf(fp, ".round_neg");
490 break;
491 case BIFROST_RTZ:
492 /* roundTowardZero in the IEEE spec. */
493 fprintf(fp, ".round_zero");
494 break;
495 default:
496 break;
497 }
498 }
499
500 static const char *
501 csel_cond_name(enum bifrost_csel_cond cond)
502 {
503 switch (cond) {
504 case BIFROST_FEQ_F: return "feq.f";
505 case BIFROST_FGT_F: return "fgt.f";
506 case BIFROST_FGE_F: return "fge.f";
507 case BIFROST_IEQ_F: return "ieq.f";
508 case BIFROST_IGT_I: return "igt.i";
509 case BIFROST_IGE_I: return "uge.i";
510 case BIFROST_UGT_I: return "ugt.i";
511 case BIFROST_UGE_I: return "uge.i";
512 default: return "invalid";
513 }
514 }
515
516 static const struct fma_op_info FMAOpInfos[] = {
517 { false, 0x00000, "FMA.f32", FMA_FMA },
518 { false, 0x40000, "MAX.f32", FMA_FMINMAX },
519 { false, 0x44000, "MIN.f32", FMA_FMINMAX },
520 { false, 0x48000, "FCMP.GL", FMA_FCMP },
521 { false, 0x4c000, "FCMP.D3D", FMA_FCMP },
522 { false, 0x4ff98, "ADD.i32", FMA_TWO_SRC },
523 { false, 0x4ffd8, "SUB.i32", FMA_TWO_SRC },
524 { false, 0x4fff0, "SUBB.i32", FMA_TWO_SRC },
525 { false, 0x50000, "FMA_MSCALE", FMA_FMA_MSCALE },
526 { false, 0x58000, "ADD.f32", FMA_FADD },
527 { false, 0x5c000, "CSEL4", FMA_CSEL4 },
528 { false, 0x5d8d0, "ICMP.D3D.GT.v2i16", FMA_TWO_SRC },
529 { false, 0x5d9d0, "UCMP.D3D.GT.v2i16", FMA_TWO_SRC },
530 { false, 0x5dad0, "ICMP.D3D.GE.v2i16", FMA_TWO_SRC },
531 { false, 0x5dbd0, "UCMP.D3D.GE.v2i16", FMA_TWO_SRC },
532 { false, 0x5dcd0, "ICMP.D3D.EQ.v2i16", FMA_TWO_SRC },
533 { false, 0x5de40, "ICMP.GL.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? 1 : 0
534 { false, 0x5de48, "ICMP.GL.GE.i32", FMA_TWO_SRC },
535 { false, 0x5de50, "UCMP.GL.GT.i32", FMA_TWO_SRC },
536 { false, 0x5de58, "UCMP.GL.GE.i32", FMA_TWO_SRC },
537 { false, 0x5de60, "ICMP.GL.EQ.i32", FMA_TWO_SRC },
538 { false, 0x5dec0, "ICMP.D3D.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? ~0 : 0
539 { false, 0x5dec8, "ICMP.D3D.GE.i32", FMA_TWO_SRC },
540 { false, 0x5ded0, "UCMP.D3D.GT.i32", FMA_TWO_SRC },
541 { false, 0x5ded8, "UCMP.D3D.GE.i32", FMA_TWO_SRC },
542 { false, 0x5dee0, "ICMP.D3D.EQ.i32", FMA_TWO_SRC },
543 { false, 0x60000, "RSHIFT_NAND", FMA_SHIFT },
544 { false, 0x61000, "RSHIFT_AND", FMA_SHIFT },
545 { false, 0x62000, "LSHIFT_NAND", FMA_SHIFT },
546 { false, 0x63000, "LSHIFT_AND", FMA_SHIFT }, // (src0 << src2) & src1
547 { false, 0x64000, "RSHIFT_XOR", FMA_SHIFT },
548 { false, 0x65200, "LSHIFT_ADD.i32", FMA_THREE_SRC },
549 { false, 0x65600, "LSHIFT_SUB.i32", FMA_THREE_SRC }, // (src0 << src2) - src1
550 { false, 0x65a00, "LSHIFT_RSUB.i32", FMA_THREE_SRC }, // src1 - (src0 << src2)
551 { false, 0x65e00, "RSHIFT_ADD.i32", FMA_THREE_SRC },
552 { false, 0x66200, "RSHIFT_SUB.i32", FMA_THREE_SRC },
553 { false, 0x66600, "RSHIFT_RSUB.i32", FMA_THREE_SRC },
554 { false, 0x66a00, "ARSHIFT_ADD.i32", FMA_THREE_SRC },
555 { false, 0x66e00, "ARSHIFT_SUB.i32", FMA_THREE_SRC },
556 { false, 0x67200, "ARSHIFT_RSUB.i32", FMA_THREE_SRC },
557 { false, 0x80000, "FMA.v2f16", FMA_FMA16 },
558 { false, 0xc0000, "MAX.v2f16", FMA_FMINMAX16 },
559 { false, 0xc4000, "MIN.v2f16", FMA_FMINMAX16 },
560 { false, 0xc8000, "FCMP.GL", FMA_FCMP16 },
561 { false, 0xcc000, "FCMP.D3D", FMA_FCMP16 },
562 { false, 0xcf900, "ADD.v2i16", FMA_TWO_SRC },
563 { false, 0xcfc10, "ADDC.i32", FMA_TWO_SRC },
564 { false, 0xcfd80, "ADD.i32.i16.X", FMA_TWO_SRC },
565 { false, 0xcfd90, "ADD.i32.u16.X", FMA_TWO_SRC },
566 { false, 0xcfdc0, "ADD.i32.i16.Y", FMA_TWO_SRC },
567 { false, 0xcfdd0, "ADD.i32.u16.Y", FMA_TWO_SRC },
568 { false, 0xd8000, "ADD.v2f16", FMA_FADD16 },
569 { false, 0xdc000, "CSEL4.v16", FMA_CSEL4 },
570 { false, 0xdd000, "F32_TO_F16", FMA_TWO_SRC },
571 { true, 0x00046, "F16_TO_I16.XX", FMA_ONE_SRC },
572 { true, 0x00047, "F16_TO_U16.XX", FMA_ONE_SRC },
573 { true, 0x0004e, "F16_TO_I16.YX", FMA_ONE_SRC },
574 { true, 0x0004f, "F16_TO_U16.YX", FMA_ONE_SRC },
575 { true, 0x00056, "F16_TO_I16.XY", FMA_ONE_SRC },
576 { true, 0x00057, "F16_TO_U16.XY", FMA_ONE_SRC },
577 { true, 0x0005e, "F16_TO_I16.YY", FMA_ONE_SRC },
578 { true, 0x0005f, "F16_TO_U16.YY", FMA_ONE_SRC },
579 { true, 0x000c0, "I16_TO_F16.XX", FMA_ONE_SRC },
580 { true, 0x000c1, "U16_TO_F16.XX", FMA_ONE_SRC },
581 { true, 0x000c8, "I16_TO_F16.YX", FMA_ONE_SRC },
582 { true, 0x000c9, "U16_TO_F16.YX", FMA_ONE_SRC },
583 { true, 0x000d0, "I16_TO_F16.XY", FMA_ONE_SRC },
584 { true, 0x000d1, "U16_TO_F16.XY", FMA_ONE_SRC },
585 { true, 0x000d8, "I16_TO_F16.YY", FMA_ONE_SRC },
586 { true, 0x000d9, "U16_TO_F16.YY", FMA_ONE_SRC },
587 { true, 0x00136, "F32_TO_I32", FMA_ONE_SRC },
588 { true, 0x00137, "F32_TO_U32", FMA_ONE_SRC },
589 { true, 0x00178, "I32_TO_F32", FMA_ONE_SRC },
590 { true, 0x00179, "U32_TO_F32", FMA_ONE_SRC },
591 { true, 0x00198, "I16_TO_I32.X", FMA_ONE_SRC },
592 { true, 0x00199, "U16_TO_U32.X", FMA_ONE_SRC },
593 { true, 0x0019a, "I16_TO_I32.Y", FMA_ONE_SRC },
594 { true, 0x0019b, "U16_TO_U32.Y", FMA_ONE_SRC },
595 { true, 0x0019c, "I16_TO_F32.X", FMA_ONE_SRC },
596 { true, 0x0019d, "U16_TO_F32.X", FMA_ONE_SRC },
597 { true, 0x0019e, "I16_TO_F32.Y", FMA_ONE_SRC },
598 { true, 0x0019f, "U16_TO_F32.Y", FMA_ONE_SRC },
599 { true, 0x001a2, "F16_TO_F32.X", FMA_ONE_SRC },
600 { true, 0x001a3, "F16_TO_F32.Y", FMA_ONE_SRC },
601 { true, 0x0032c, "NOP", FMA_ONE_SRC },
602 { true, 0x0032d, "MOV", FMA_ONE_SRC },
603 { true, 0x0032f, "SWZ.YY.v2i16", FMA_ONE_SRC },
604 { true, 0x00345, "LOG_FREXPM", FMA_ONE_SRC },
605 { true, 0x00365, "FRCP_FREXPM", FMA_ONE_SRC },
606 { true, 0x00375, "FSQRT_FREXPM", FMA_ONE_SRC },
607 { true, 0x0038d, "FRCP_FREXPE", FMA_ONE_SRC },
608 { true, 0x003a5, "FSQRT_FREXPE", FMA_ONE_SRC },
609 { true, 0x003ad, "FRSQ_FREXPE", FMA_ONE_SRC },
610 { true, 0x003c5, "LOG_FREXPE", FMA_ONE_SRC },
611 { true, 0x003fa, "CLZ", FMA_ONE_SRC },
612 { true, 0x00b80, "IMAX3", FMA_THREE_SRC },
613 { true, 0x00bc0, "UMAX3", FMA_THREE_SRC },
614 { true, 0x00c00, "IMIN3", FMA_THREE_SRC },
615 { true, 0x00c40, "UMIN3", FMA_THREE_SRC },
616 { true, 0x00ec5, "ROUND", FMA_ONE_SRC },
617 { true, 0x00f40, "CSEL", FMA_THREE_SRC }, // src2 != 0 ? src1 : src0
618 { true, 0x00fc0, "MUX.i32", FMA_THREE_SRC }, // see ADD comment
619 { true, 0x01805, "ROUNDEVEN", FMA_ONE_SRC },
620 { true, 0x01845, "CEIL", FMA_ONE_SRC },
621 { true, 0x01885, "FLOOR", FMA_ONE_SRC },
622 { true, 0x018c5, "TRUNC", FMA_ONE_SRC },
623 { true, 0x019b0, "ATAN_LDEXP.Y.f32", FMA_TWO_SRC },
624 { true, 0x019b8, "ATAN_LDEXP.X.f32", FMA_TWO_SRC },
625 { true, 0x01c80, "LSHIFT_ADD_LOW32.u32", FMA_SHIFT_ADD64 },
626 { true, 0x01cc0, "LSHIFT_ADD_LOW32.i64", FMA_SHIFT_ADD64 },
627 { true, 0x01d80, "LSHIFT_ADD_LOW32.i32", FMA_SHIFT_ADD64 },
628 { true, 0x01e00, "SEL.XX.i16", FMA_TWO_SRC },
629 { true, 0x01e08, "SEL.YX.i16", FMA_TWO_SRC },
630 { true, 0x01e10, "SEL.XY.i16", FMA_TWO_SRC },
631 { true, 0x01e18, "SEL.YY.i16", FMA_TWO_SRC },
632 { true, 0x00800, "IMAD", FMA_THREE_SRC },
633 { true, 0x078db, "POPCNT", FMA_ONE_SRC },
634 };
635
636 static struct fma_op_info find_fma_op_info(unsigned op, bool extended)
637 {
638 for (unsigned i = 0; i < ARRAY_SIZE(FMAOpInfos); i++) {
639 unsigned opCmp = ~0;
640
641 if (FMAOpInfos[i].extended != extended)
642 continue;
643
644 if (extended)
645 op &= ~0xe0000;
646
647 switch (FMAOpInfos[i].src_type) {
648 case FMA_ONE_SRC:
649 opCmp = op;
650 break;
651 case FMA_TWO_SRC:
652 opCmp = op & ~0x7;
653 break;
654 case FMA_FCMP:
655 case FMA_FCMP16:
656 opCmp = op & ~0x1fff;
657 break;
658 case FMA_THREE_SRC:
659 case FMA_SHIFT_ADD64:
660 opCmp = op & ~0x3f;
661 break;
662 case FMA_FADD:
663 case FMA_FMINMAX:
664 case FMA_FADD16:
665 case FMA_FMINMAX16:
666 opCmp = op & ~0x3fff;
667 break;
668 case FMA_FMA:
669 case FMA_FMA16:
670 opCmp = op & ~0x3ffff;
671 break;
672 case FMA_CSEL4:
673 case FMA_SHIFT:
674 opCmp = op & ~0xfff;
675 break;
676 case FMA_FMA_MSCALE:
677 opCmp = op & ~0x7fff;
678 break;
679 default:
680 opCmp = ~0;
681 break;
682 }
683 if (FMAOpInfos[i].op == opCmp)
684 return FMAOpInfos[i];
685 }
686
687 struct fma_op_info info;
688 snprintf(info.name, sizeof(info.name), "op%04x", op);
689 info.op = op;
690 info.src_type = FMA_THREE_SRC;
691 return info;
692 }
693
694 static void dump_fcmp(FILE *fp, unsigned op)
695 {
696 switch (op) {
697 case 0:
698 fprintf(fp, ".OEQ");
699 break;
700 case 1:
701 fprintf(fp, ".OGT");
702 break;
703 case 2:
704 fprintf(fp, ".OGE");
705 break;
706 case 3:
707 fprintf(fp, ".UNE");
708 break;
709 case 4:
710 fprintf(fp, ".OLT");
711 break;
712 case 5:
713 fprintf(fp, ".OLE");
714 break;
715 default:
716 fprintf(fp, ".unk%d", op);
717 break;
718 }
719 }
720
721 static void dump_16swizzle(FILE *fp, unsigned swiz)
722 {
723 if (swiz == 2)
724 return;
725 fprintf(fp, ".%c%c", "xy"[swiz & 1], "xy"[(swiz >> 1) & 1]);
726 }
727
728 static void dump_fma_expand_src0(FILE *fp, unsigned ctrl)
729 {
730 switch (ctrl) {
731 case 3:
732 case 4:
733 case 6:
734 fprintf(fp, ".x");
735 break;
736 case 5:
737 case 7:
738 fprintf(fp, ".y");
739 break;
740 case 0:
741 case 1:
742 case 2:
743 break;
744 default:
745 fprintf(fp, ".unk");
746 break;
747 }
748 }
749
750 static void dump_fma_expand_src1(FILE *fp, unsigned ctrl)
751 {
752 switch (ctrl) {
753 case 1:
754 case 3:
755 fprintf(fp, ".x");
756 break;
757 case 2:
758 case 4:
759 case 5:
760 fprintf(fp, ".y");
761 break;
762 case 0:
763 case 6:
764 case 7:
765 break;
766 default:
767 fprintf(fp, ".unk");
768 break;
769 }
770 }
771
772 static const char *
773 bi_ldst_type_name(enum bifrost_ldst_type type)
774 {
775 switch (type) {
776 case BIFROST_LDST_F16: return "f16";
777 case BIFROST_LDST_F32: return "f32";
778 case BIFROST_LDST_I32: return "i32";
779 case BIFROST_LDST_U32: return "u32";
780 default: return "invalid";
781 }
782 }
783
784 static void dump_fma(FILE *fp, uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts, bool verbose)
785 {
786 if (verbose) {
787 fprintf(fp, "# FMA: %016" PRIx64 "\n", word);
788 }
789 struct bifrost_fma_inst FMA;
790 memcpy((char *) &FMA, (char *) &word, sizeof(struct bifrost_fma_inst));
791 struct fma_op_info info = find_fma_op_info(FMA.op, (FMA.op & 0xe0000) == 0xe0000);
792
793 fprintf(fp, "%s", info.name);
794 if (info.src_type == FMA_FADD ||
795 info.src_type == FMA_FMINMAX ||
796 info.src_type == FMA_FMA ||
797 info.src_type == FMA_FADD16 ||
798 info.src_type == FMA_FMINMAX16 ||
799 info.src_type == FMA_FMA16) {
800 dump_output_mod(fp, bits(FMA.op, 12, 14));
801 switch (info.src_type) {
802 case FMA_FADD:
803 case FMA_FMA:
804 case FMA_FADD16:
805 case FMA_FMA16:
806 dump_round_mode(fp, bits(FMA.op, 10, 12));
807 break;
808 case FMA_FMINMAX:
809 case FMA_FMINMAX16:
810 dump_minmax_mode(fp, bits(FMA.op, 10, 12));
811 break;
812 default:
813 assert(0);
814 }
815 } else if (info.src_type == FMA_FCMP || info.src_type == FMA_FCMP16) {
816 dump_fcmp(fp, bits(FMA.op, 10, 13));
817 if (info.src_type == FMA_FCMP)
818 fprintf(fp, ".f32");
819 else
820 fprintf(fp, ".v2f16");
821 } else if (info.src_type == FMA_FMA_MSCALE) {
822 if (FMA.op & (1 << 11)) {
823 switch ((FMA.op >> 9) & 0x3) {
824 case 0:
825 /* This mode seems to do a few things:
826 * - Makes 0 * infinity (and incidentally 0 * nan) return 0,
827 * since generating a nan would poison the result of
828 * 1/infinity and 1/0.
829 * - Fiddles with which nan is returned in nan * nan,
830 * presumably to make sure that the same exact nan is
831 * returned for 1/nan.
832 */
833 fprintf(fp, ".rcp_mode");
834 break;
835 case 3:
836 /* Similar to the above, but src0 always wins when multiplying
837 * 0 by infinity.
838 */
839 fprintf(fp, ".sqrt_mode");
840 break;
841 default:
842 fprintf(fp, ".unk%d_mode", (int) (FMA.op >> 9) & 0x3);
843 }
844 } else {
845 dump_output_mod(fp, bits(FMA.op, 9, 11));
846 }
847 } else if (info.src_type == FMA_SHIFT) {
848 struct bifrost_shift_fma shift;
849 memcpy(&shift, &FMA, sizeof(shift));
850
851 if (shift.half == 0x7)
852 fprintf(fp, ".v2i16");
853 else if (shift.half == 0)
854 fprintf(fp, ".i32");
855 else if (shift.half == 0x4)
856 fprintf(fp, ".v4i8");
857 else
858 fprintf(fp, ".unk%u", shift.half);
859
860 if (!shift.unk)
861 fprintf(fp, ".no_unk");
862
863 if (shift.invert_1)
864 fprintf(fp, ".invert_1");
865
866 if (shift.invert_2)
867 fprintf(fp, ".invert_2");
868 }
869
870 fprintf(fp, " ");
871
872 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
873 if (next_ctrl.fma_write_unit != REG_WRITE_NONE) {
874 fprintf(fp, "{R%d, T0}, ", GetRegToWrite(next_ctrl.fma_write_unit, next_regs));
875 } else {
876 fprintf(fp, "T0, ");
877 }
878
879 switch (info.src_type) {
880 case FMA_ONE_SRC:
881 dump_src(fp, FMA.src0, regs, consts, true);
882 break;
883 case FMA_TWO_SRC:
884 dump_src(fp, FMA.src0, regs, consts, true);
885 fprintf(fp, ", ");
886 dump_src(fp, FMA.op & 0x7, regs, consts, true);
887 break;
888 case FMA_FADD:
889 case FMA_FMINMAX:
890 if (FMA.op & 0x10)
891 fprintf(fp, "-");
892 if (FMA.op & 0x200)
893 fprintf(fp, "abs(");
894 dump_src(fp, FMA.src0, regs, consts, true);
895 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
896 if (FMA.op & 0x200)
897 fprintf(fp, ")");
898 fprintf(fp, ", ");
899 if (FMA.op & 0x20)
900 fprintf(fp, "-");
901 if (FMA.op & 0x8)
902 fprintf(fp, "abs(");
903 dump_src(fp, FMA.op & 0x7, regs, consts, true);
904 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
905 if (FMA.op & 0x8)
906 fprintf(fp, ")");
907 break;
908 case FMA_FADD16:
909 case FMA_FMINMAX16: {
910 bool abs1 = FMA.op & 0x8;
911 bool abs2 = (FMA.op & 0x7) < FMA.src0;
912 if (FMA.op & 0x10)
913 fprintf(fp, "-");
914 if (abs1 || abs2)
915 fprintf(fp, "abs(");
916 dump_src(fp, FMA.src0, regs, consts, true);
917 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
918 if (abs1 || abs2)
919 fprintf(fp, ")");
920 fprintf(fp, ", ");
921 if (FMA.op & 0x20)
922 fprintf(fp, "-");
923 if (abs1 && abs2)
924 fprintf(fp, "abs(");
925 dump_src(fp, FMA.op & 0x7, regs, consts, true);
926 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
927 if (abs1 && abs2)
928 fprintf(fp, ")");
929 break;
930 }
931 case FMA_FCMP:
932 if (FMA.op & 0x200)
933 fprintf(fp, "abs(");
934 dump_src(fp, FMA.src0, regs, consts, true);
935 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
936 if (FMA.op & 0x200)
937 fprintf(fp, ")");
938 fprintf(fp, ", ");
939 if (FMA.op & 0x20)
940 fprintf(fp, "-");
941 if (FMA.op & 0x8)
942 fprintf(fp, "abs(");
943 dump_src(fp, FMA.op & 0x7, regs, consts, true);
944 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
945 if (FMA.op & 0x8)
946 fprintf(fp, ")");
947 break;
948 case FMA_FCMP16:
949 dump_src(fp, FMA.src0, regs, consts, true);
950 // Note: this is kinda a guess, I haven't seen the blob set this to
951 // anything other than the identity, but it matches FMA_TWO_SRCFmod16
952 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
953 fprintf(fp, ", ");
954 dump_src(fp, FMA.op & 0x7, regs, consts, true);
955 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
956 break;
957 case FMA_SHIFT_ADD64:
958 dump_src(fp, FMA.src0, regs, consts, true);
959 fprintf(fp, ", ");
960 dump_src(fp, FMA.op & 0x7, regs, consts, true);
961 fprintf(fp, ", ");
962 fprintf(fp, "shift:%u", (FMA.op >> 3) & 0x7);
963 break;
964 case FMA_THREE_SRC:
965 dump_src(fp, FMA.src0, regs, consts, true);
966 fprintf(fp, ", ");
967 dump_src(fp, FMA.op & 0x7, regs, consts, true);
968 fprintf(fp, ", ");
969 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
970 break;
971 case FMA_SHIFT: {
972 struct bifrost_shift_fma shift;
973 memcpy(&shift, &FMA, sizeof(shift));
974
975 dump_src(fp, shift.src0, regs, consts, true);
976 fprintf(fp, ", ");
977 dump_src(fp, shift.src1, regs, consts, true);
978 fprintf(fp, ", ");
979 dump_src(fp, shift.src2, regs, consts, true);
980 break;
981 }
982 case FMA_FMA:
983 if (FMA.op & (1 << 14))
984 fprintf(fp, "-");
985 if (FMA.op & (1 << 9))
986 fprintf(fp, "abs(");
987 dump_src(fp, FMA.src0, regs, consts, true);
988 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
989 if (FMA.op & (1 << 9))
990 fprintf(fp, ")");
991 fprintf(fp, ", ");
992 if (FMA.op & (1 << 16))
993 fprintf(fp, "abs(");
994 dump_src(fp, FMA.op & 0x7, regs, consts, true);
995 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
996 if (FMA.op & (1 << 16))
997 fprintf(fp, ")");
998 fprintf(fp, ", ");
999 if (FMA.op & (1 << 15))
1000 fprintf(fp, "-");
1001 if (FMA.op & (1 << 17))
1002 fprintf(fp, "abs(");
1003 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
1004 if (FMA.op & (1 << 17))
1005 fprintf(fp, ")");
1006 break;
1007 case FMA_FMA16:
1008 if (FMA.op & (1 << 14))
1009 fprintf(fp, "-");
1010 dump_src(fp, FMA.src0, regs, consts, true);
1011 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
1012 fprintf(fp, ", ");
1013 dump_src(fp, FMA.op & 0x7, regs, consts, true);
1014 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
1015 fprintf(fp, ", ");
1016 if (FMA.op & (1 << 15))
1017 fprintf(fp, "-");
1018 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
1019 dump_16swizzle(fp, (FMA.op >> 16) & 0x3);
1020 break;
1021 case FMA_CSEL4: {
1022 struct bifrost_csel4 csel;
1023 memcpy(&csel, &FMA, sizeof(csel));
1024 fprintf(fp, ".%s ", csel_cond_name(csel.cond));
1025
1026 dump_src(fp, csel.src0, regs, consts, true);
1027 fprintf(fp, ", ");
1028 dump_src(fp, csel.src1, regs, consts, true);
1029 fprintf(fp, ", ");
1030 dump_src(fp, csel.src2, regs, consts, true);
1031 fprintf(fp, ", ");
1032 dump_src(fp, csel.src3, regs, consts, true);
1033 break;
1034 }
1035 case FMA_FMA_MSCALE:
1036 if (FMA.op & (1 << 12))
1037 fprintf(fp, "abs(");
1038 dump_src(fp, FMA.src0, regs, consts, true);
1039 if (FMA.op & (1 << 12))
1040 fprintf(fp, ")");
1041 fprintf(fp, ", ");
1042 if (FMA.op & (1 << 13))
1043 fprintf(fp, "-");
1044 dump_src(fp, FMA.op & 0x7, regs, consts, true);
1045 fprintf(fp, ", ");
1046 if (FMA.op & (1 << 14))
1047 fprintf(fp, "-");
1048 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
1049 fprintf(fp, ", ");
1050 dump_src(fp, (FMA.op >> 6) & 0x7, regs, consts, true);
1051 break;
1052 }
1053 fprintf(fp, "\n");
1054 }
1055
1056 static const struct add_op_info add_op_infos[] = {
1057 { 0x00000, "MAX.f32", ADD_FMINMAX },
1058 { 0x02000, "MIN.f32", ADD_FMINMAX },
1059 { 0x04000, "ADD.f32", ADD_FADD },
1060 { 0x06000, "FCMP.GL", ADD_FCMP },
1061 { 0x07000, "FCMP.D3D", ADD_FCMP },
1062 { 0x07856, "F16_TO_I16", ADD_ONE_SRC },
1063 { 0x07857, "F16_TO_U16", ADD_ONE_SRC },
1064 { 0x078c0, "I16_TO_F16.XX", ADD_ONE_SRC },
1065 { 0x078c1, "U16_TO_F16.XX", ADD_ONE_SRC },
1066 { 0x078c8, "I16_TO_F16.YX", ADD_ONE_SRC },
1067 { 0x078c9, "U16_TO_F16.YX", ADD_ONE_SRC },
1068 { 0x078d0, "I16_TO_F16.XY", ADD_ONE_SRC },
1069 { 0x078d1, "U16_TO_F16.XY", ADD_ONE_SRC },
1070 { 0x078d8, "I16_TO_F16.YY", ADD_ONE_SRC },
1071 { 0x078d9, "U16_TO_F16.YY", ADD_ONE_SRC },
1072 { 0x07936, "F32_TO_I32", ADD_ONE_SRC },
1073 { 0x07937, "F32_TO_U32", ADD_ONE_SRC },
1074 { 0x07978, "I32_TO_F32", ADD_ONE_SRC },
1075 { 0x07979, "U32_TO_F32", ADD_ONE_SRC },
1076 { 0x07998, "I16_TO_I32.X", ADD_ONE_SRC },
1077 { 0x07999, "U16_TO_U32.X", ADD_ONE_SRC },
1078 { 0x0799a, "I16_TO_I32.Y", ADD_ONE_SRC },
1079 { 0x0799b, "U16_TO_U32.Y", ADD_ONE_SRC },
1080 { 0x0799c, "I16_TO_F32.X", ADD_ONE_SRC },
1081 { 0x0799d, "U16_TO_F32.X", ADD_ONE_SRC },
1082 { 0x0799e, "I16_TO_F32.Y", ADD_ONE_SRC },
1083 { 0x0799f, "U16_TO_F32.Y", ADD_ONE_SRC },
1084 { 0x079a2, "F16_TO_F32.X", ADD_ONE_SRC },
1085 { 0x079a3, "F16_TO_F32.Y", ADD_ONE_SRC },
1086 { 0x07b2b, "SWZ.YX.v2i16", ADD_ONE_SRC },
1087 { 0x07b2c, "NOP", ADD_ONE_SRC },
1088 { 0x07b29, "SWZ.XX.v2i16", ADD_ONE_SRC },
1089 { 0x07b2d, "MOV", ADD_ONE_SRC },
1090 { 0x07b2f, "SWZ.YY.v2i16", ADD_ONE_SRC },
1091 { 0x07b65, "FRCP_FREXPM", ADD_ONE_SRC },
1092 { 0x07b75, "FSQRT_FREXPM", ADD_ONE_SRC },
1093 { 0x07b8d, "FRCP_FREXPE", ADD_ONE_SRC },
1094 { 0x07ba5, "FSQRT_FREXPE", ADD_ONE_SRC },
1095 { 0x07bad, "FRSQ_FREXPE", ADD_ONE_SRC },
1096 { 0x07bc5, "FLOG_FREXPE", ADD_ONE_SRC },
1097 { 0x07d45, "CEIL", ADD_ONE_SRC },
1098 { 0x07d85, "FLOOR", ADD_ONE_SRC },
1099 { 0x07dc5, "TRUNC", ADD_ONE_SRC },
1100 { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC },
1101 { 0x08000, "LD_ATTR", ADD_LOAD_ATTR, true },
1102 { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP, true },
1103 { 0x0b000, "TEX", ADD_TEX_COMPACT, true },
1104 { 0x0c188, "LOAD.i32", ADD_TWO_SRC, true },
1105 { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC, true },
1106 { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1107 { 0x0c1c8, "LOAD.v2i32", ADD_TWO_SRC, true },
1108 { 0x0c1e0, "LD_UBO.v2i32", ADD_TWO_SRC, true },
1109 { 0x0c1f8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1110 { 0x0c208, "LOAD.v4i32", ADD_TWO_SRC, true },
1111 { 0x0c220, "LD_UBO.v4i32", ADD_TWO_SRC, true },
1112 { 0x0c238, "LD_SCRATCH.v4i32", ADD_TWO_SRC, true },
1113 { 0x0c248, "STORE.v4i32", ADD_TWO_SRC, true },
1114 { 0x0c278, "ST_SCRATCH.v4i32", ADD_TWO_SRC, true },
1115 { 0x0c588, "STORE.i32", ADD_TWO_SRC, true },
1116 { 0x0c5b8, "ST_SCRATCH.i32", ADD_TWO_SRC, true },
1117 { 0x0c5c8, "STORE.v2i32", ADD_TWO_SRC, true },
1118 { 0x0c5f8, "ST_SCRATCH.v2i32", ADD_TWO_SRC, true },
1119 { 0x0c648, "LOAD.u16", ADD_TWO_SRC, true }, // zero-extends
1120 { 0x0ca88, "LOAD.v3i32", ADD_TWO_SRC, true },
1121 { 0x0caa0, "LD_UBO.v3i32", ADD_TWO_SRC, true },
1122 { 0x0cab8, "LD_SCRATCH.v3i32", ADD_TWO_SRC, true },
1123 { 0x0cb88, "STORE.v3i32", ADD_TWO_SRC, true },
1124 { 0x0cbb8, "ST_SCRATCH.v3i32", ADD_TWO_SRC, true },
1125 { 0x0cc00, "FRCP_FAST.f32", ADD_ONE_SRC },
1126 { 0x0cc20, "FRSQ_FAST.f32", ADD_ONE_SRC },
1127 { 0x0ce00, "FRCP_TABLE", ADD_ONE_SRC },
1128 { 0x0ce10, "FRCP_FAST.f16.X", ADD_ONE_SRC },
1129 { 0x0ce20, "FRSQ_TABLE", ADD_ONE_SRC },
1130 { 0x0ce30, "FRCP_FAST.f16.Y", ADD_ONE_SRC },
1131 { 0x0ce50, "FRSQ_FAST.f16.X", ADD_ONE_SRC },
1132 { 0x0ce60, "FRCP_APPROX", ADD_ONE_SRC },
1133 { 0x0ce70, "FRSQ_FAST.f16.Y", ADD_ONE_SRC },
1134 { 0x0cf40, "ATAN_ASSIST", ADD_TWO_SRC },
1135 { 0x0cf48, "ATAN_TABLE", ADD_TWO_SRC },
1136 { 0x0cf50, "SIN_TABLE", ADD_ONE_SRC },
1137 { 0x0cf51, "COS_TABLE", ADD_ONE_SRC },
1138 { 0x0cf58, "EXP_TABLE", ADD_ONE_SRC },
1139 { 0x0cf60, "FLOG2_TABLE", ADD_ONE_SRC },
1140 { 0x0cf64, "FLOGE_TABLE", ADD_ONE_SRC },
1141 { 0x0d000, "BRANCH", ADD_BRANCH },
1142 { 0x0e8c0, "MUX", ADD_THREE_SRC },
1143 { 0x0e9b0, "ATAN_LDEXP.Y.f32", ADD_TWO_SRC },
1144 { 0x0e9b8, "ATAN_LDEXP.X.f32", ADD_TWO_SRC },
1145 { 0x0ea60, "SEL.XX.i16", ADD_TWO_SRC },
1146 { 0x0ea70, "SEL.XY.i16", ADD_TWO_SRC },
1147 { 0x0ea68, "SEL.YX.i16", ADD_TWO_SRC },
1148 { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC },
1149 { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC },
1150 { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC }, // src0 > src1 ? 1 : 0
1151 { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC },
1152 { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC },
1153 { 0x0f658, "UCMP.GL.GE", ADD_TWO_SRC },
1154 { 0x0f660, "ICMP.GL.EQ", ADD_TWO_SRC },
1155 { 0x0f669, "ICMP.GL.NEQ", ADD_TWO_SRC },
1156 { 0x0f6c0, "ICMP.D3D.GT", ADD_TWO_SRC }, // src0 > src1 ? ~0 : 0
1157 { 0x0f6c8, "ICMP.D3D.GE", ADD_TWO_SRC },
1158 { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC },
1159 { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC },
1160 { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC },
1161 { 0x10000, "MAX.v2f16", ADD_FMINMAX16 },
1162 { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale },
1163 { 0x12000, "MIN.v2f16", ADD_FMINMAX16 },
1164 { 0x14000, "ADD.v2f16", ADD_FADD16 },
1165 { 0x17000, "FCMP.D3D", ADD_FCMP16 },
1166 { 0x178c0, "ADD.i32", ADD_TWO_SRC },
1167 { 0x17900, "ADD.v2i16", ADD_TWO_SRC },
1168 { 0x17ac0, "SUB.i32", ADD_TWO_SRC },
1169 { 0x17c10, "ADDC.i32", ADD_TWO_SRC }, // adds src0 to the bottom bit of src1
1170 { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC },
1171 { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC },
1172 { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC },
1173 { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC },
1174 { 0x18000, "LD_VAR_ADDR", ADD_VARYING_ADDRESS, true },
1175 { 0x19181, "DISCARD.FEQ.f32", ADD_TWO_SRC, true },
1176 { 0x19189, "DISCARD.FNE.f32", ADD_TWO_SRC, true },
1177 { 0x1918C, "DISCARD.GL.f32", ADD_TWO_SRC, true }, /* Consumes ICMP.GL/etc with fixed 0 argument */
1178 { 0x19190, "DISCARD.FLE.f32", ADD_TWO_SRC, true },
1179 { 0x19198, "DISCARD.FLT.f32", ADD_TWO_SRC, true },
1180 { 0x191e8, "ATEST.f32", ADD_TWO_SRC, true },
1181 { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC, true },
1182 { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC, true },
1183 { 0x19300, "ST_VAR.v1", ADD_THREE_SRC, true },
1184 { 0x19340, "ST_VAR.v2", ADD_THREE_SRC, true },
1185 { 0x19380, "ST_VAR.v3", ADD_THREE_SRC, true },
1186 { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC, true },
1187 { 0x1952c, "BLEND", ADD_BLENDING, true },
1188 { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP, true },
1189 { 0x1ae60, "TEX", ADD_TEX, true },
1190 { 0x1c000, "RSHIFT_NAND.i32", ADD_SHIFT },
1191 { 0x1c400, "RSHIFT_AND.i32", ADD_SHIFT },
1192 { 0x1c800, "LSHIFT_NAND.i32", ADD_SHIFT },
1193 { 0x1cc00, "LSHIFT_AND.i32", ADD_SHIFT },
1194 { 0x1d000, "RSHIFT_XOR.i32", ADD_SHIFT },
1195 { 0x1d400, "LSHIFT_ADD.i32", ADD_SHIFT },
1196 { 0x1d800, "RSHIFT_SUB.i32", ADD_SHIFT },
1197 { 0x1dd18, "OR.i32", ADD_TWO_SRC },
1198 { 0x1dd20, "AND.i32", ADD_TWO_SRC },
1199 { 0x1dd60, "LSHIFT.i32", ADD_TWO_SRC },
1200 { 0x1dd50, "XOR.i32", ADD_TWO_SRC },
1201 { 0x1dd80, "RSHIFT.i32", ADD_TWO_SRC },
1202 { 0x1dda0, "ARSHIFT.i32", ADD_TWO_SRC },
1203 };
1204
1205 static struct add_op_info find_add_op_info(unsigned op)
1206 {
1207 for (unsigned i = 0; i < ARRAY_SIZE(add_op_infos); i++) {
1208 unsigned opCmp = ~0;
1209 switch (add_op_infos[i].src_type) {
1210 case ADD_ONE_SRC:
1211 case ADD_BLENDING:
1212 opCmp = op;
1213 break;
1214 case ADD_TWO_SRC:
1215 opCmp = op & ~0x7;
1216 break;
1217 case ADD_THREE_SRC:
1218 opCmp = op & ~0x3f;
1219 break;
1220 case ADD_SHIFT:
1221 opCmp = op & ~0x3ff;
1222 break;
1223 case ADD_TEX:
1224 opCmp = op & ~0xf;
1225 break;
1226 case ADD_FADD:
1227 case ADD_FMINMAX:
1228 case ADD_FADD16:
1229 opCmp = op & ~0x1fff;
1230 break;
1231 case ADD_FMINMAX16:
1232 case ADD_FADDMscale:
1233 opCmp = op & ~0xfff;
1234 break;
1235 case ADD_FCMP:
1236 case ADD_FCMP16:
1237 opCmp = op & ~0x7ff;
1238 break;
1239 case ADD_TEX_COMPACT:
1240 opCmp = op & ~0x3ff;
1241 break;
1242 case ADD_VARYING_INTERP:
1243 opCmp = op & ~0x7ff;
1244 break;
1245 case ADD_VARYING_ADDRESS:
1246 opCmp = op & ~0xfff;
1247 break;
1248 case ADD_LOAD_ATTR:
1249 case ADD_BRANCH:
1250 opCmp = op & ~0xfff;
1251 break;
1252 default:
1253 opCmp = ~0;
1254 break;
1255 }
1256 if (add_op_infos[i].op == opCmp)
1257 return add_op_infos[i];
1258 }
1259
1260 struct add_op_info info;
1261 snprintf(info.name, sizeof(info.name), "op%04x", op);
1262 info.op = op;
1263 info.src_type = ADD_TWO_SRC;
1264 info.has_data_reg = true;
1265 return info;
1266 }
1267
1268 static void dump_add(FILE *fp, uint64_t word, struct bifrost_regs regs,
1269 struct bifrost_regs next_regs, uint64_t *consts,
1270 unsigned data_reg, unsigned offset, bool verbose)
1271 {
1272 if (verbose) {
1273 fprintf(fp, "# ADD: %016" PRIx64 "\n", word);
1274 }
1275 struct bifrost_add_inst ADD;
1276 memcpy((char *) &ADD, (char *) &word, sizeof(ADD));
1277 struct add_op_info info = find_add_op_info(ADD.op);
1278
1279 fprintf(fp, "%s", info.name);
1280
1281 // float16 seems like it doesn't support output modifiers
1282 if (info.src_type == ADD_FADD || info.src_type == ADD_FMINMAX) {
1283 // output modifiers
1284 dump_output_mod(fp, bits(ADD.op, 8, 10));
1285 if (info.src_type == ADD_FADD)
1286 dump_round_mode(fp, bits(ADD.op, 10, 12));
1287 else
1288 dump_minmax_mode(fp, bits(ADD.op, 10, 12));
1289 } else if (info.src_type == ADD_FCMP || info.src_type == ADD_FCMP16) {
1290 dump_fcmp(fp, bits(ADD.op, 3, 6));
1291 if (info.src_type == ADD_FCMP)
1292 fprintf(fp, ".f32");
1293 else
1294 fprintf(fp, ".v2f16");
1295 } else if (info.src_type == ADD_FADDMscale) {
1296 switch ((ADD.op >> 6) & 0x7) {
1297 case 0:
1298 break;
1299 // causes GPU hangs on G71
1300 case 1:
1301 fprintf(fp, ".invalid");
1302 break;
1303 // Same as usual outmod value.
1304 case 2:
1305 fprintf(fp, ".clamp_0_1");
1306 break;
1307 // If src0 is infinite or NaN, flush it to zero so that the other
1308 // source is passed through unmodified.
1309 case 3:
1310 fprintf(fp, ".flush_src0_inf_nan");
1311 break;
1312 // Vice versa.
1313 case 4:
1314 fprintf(fp, ".flush_src1_inf_nan");
1315 break;
1316 // Every other case seems to behave the same as the above?
1317 default:
1318 fprintf(fp, ".unk%d", (ADD.op >> 6) & 0x7);
1319 break;
1320 }
1321 } else if (info.src_type == ADD_VARYING_INTERP) {
1322 if (ADD.op & 0x200)
1323 fprintf(fp, ".reuse");
1324 if (ADD.op & 0x400)
1325 fprintf(fp, ".flat");
1326 switch ((ADD.op >> 7) & 0x3) {
1327 case 0:
1328 fprintf(fp, ".per_frag");
1329 break;
1330 case 1:
1331 fprintf(fp, ".centroid");
1332 break;
1333 case 2:
1334 break;
1335 case 3:
1336 fprintf(fp, ".explicit");
1337 break;
1338 }
1339 fprintf(fp, ".v%d", ((ADD.op >> 5) & 0x3) + 1);
1340 } else if (info.src_type == ADD_BRANCH) {
1341 enum bifrost_branch_code branchCode = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1342 if (branchCode == BR_ALWAYS) {
1343 // unconditional branch
1344 } else {
1345 enum bifrost_branch_cond cond = (enum bifrost_branch_cond) ((ADD.op >> 6) & 0x7);
1346 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1347 bool portSwapped = (ADD.op & 0x7) < ADD.src0;
1348 // See the comment in branch_bit_size
1349 if (size == BR_SIZE_16YX0)
1350 portSwapped = true;
1351 if (size == BR_SIZE_16YX1)
1352 portSwapped = false;
1353 // These sizes are only for floating point comparisons, so the
1354 // non-floating-point comparisons are reused to encode the flipped
1355 // versions.
1356 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y)
1357 portSwapped = false;
1358 // There's only one argument, so we reuse the extra argument to
1359 // encode this.
1360 if (size == BR_SIZE_ZERO)
1361 portSwapped = !(ADD.op & 1);
1362
1363 switch (cond) {
1364 case BR_COND_LT:
1365 if (portSwapped)
1366 fprintf(fp, ".LT.u");
1367 else
1368 fprintf(fp, ".LT.i");
1369 break;
1370 case BR_COND_LE:
1371 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y) {
1372 fprintf(fp, ".UNE.f");
1373 } else {
1374 if (portSwapped)
1375 fprintf(fp, ".LE.u");
1376 else
1377 fprintf(fp, ".LE.i");
1378 }
1379 break;
1380 case BR_COND_GT:
1381 if (portSwapped)
1382 fprintf(fp, ".GT.u");
1383 else
1384 fprintf(fp, ".GT.i");
1385 break;
1386 case BR_COND_GE:
1387 if (portSwapped)
1388 fprintf(fp, ".GE.u");
1389 else
1390 fprintf(fp, ".GE.i");
1391 break;
1392 case BR_COND_EQ:
1393 if (portSwapped)
1394 fprintf(fp, ".NE.i");
1395 else
1396 fprintf(fp, ".EQ.i");
1397 break;
1398 case BR_COND_OEQ:
1399 if (portSwapped)
1400 fprintf(fp, ".UNE.f");
1401 else
1402 fprintf(fp, ".OEQ.f");
1403 break;
1404 case BR_COND_OGT:
1405 if (portSwapped)
1406 fprintf(fp, ".OGT.unk.f");
1407 else
1408 fprintf(fp, ".OGT.f");
1409 break;
1410 case BR_COND_OLT:
1411 if (portSwapped)
1412 fprintf(fp, ".OLT.unk.f");
1413 else
1414 fprintf(fp, ".OLT.f");
1415 break;
1416 }
1417 switch (size) {
1418 case BR_SIZE_32:
1419 case BR_SIZE_32_AND_16X:
1420 case BR_SIZE_32_AND_16Y:
1421 fprintf(fp, "32");
1422 break;
1423 case BR_SIZE_16XX:
1424 case BR_SIZE_16YY:
1425 case BR_SIZE_16YX0:
1426 case BR_SIZE_16YX1:
1427 fprintf(fp, "16");
1428 break;
1429 case BR_SIZE_ZERO: {
1430 unsigned ctrl = (ADD.op >> 1) & 0x3;
1431 if (ctrl == 0)
1432 fprintf(fp, "32.Z");
1433 else
1434 fprintf(fp, "16.Z");
1435 break;
1436 }
1437 }
1438 }
1439 } else if (info.src_type == ADD_SHIFT) {
1440 struct bifrost_shift_add shift;
1441 memcpy(&shift, &ADD, sizeof(ADD));
1442
1443 if (shift.invert_1)
1444 fprintf(fp, ".invert_1");
1445
1446 if (shift.invert_2)
1447 fprintf(fp, ".invert_2");
1448
1449 if (shift.zero)
1450 fprintf(fp, ".unk%u", shift.zero);
1451 } else if (info.src_type == ADD_VARYING_ADDRESS) {
1452 struct bifrost_ld_var_addr ld;
1453 memcpy(&ld, &ADD, sizeof(ADD));
1454 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1455 } else if (info.src_type == ADD_LOAD_ATTR) {
1456 struct bifrost_ld_attr ld;
1457 memcpy(&ld, &ADD, sizeof(ADD));
1458
1459 if (ld.channels)
1460 fprintf(fp, ".v%d%s", ld.channels + 1, bi_ldst_type_name(ld.type));
1461 else
1462 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1463 }
1464
1465 fprintf(fp, " ");
1466
1467 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
1468 if (next_ctrl.add_write_unit != REG_WRITE_NONE) {
1469 fprintf(fp, "{R%d, T1}, ", GetRegToWrite(next_ctrl.add_write_unit, next_regs));
1470 } else {
1471 fprintf(fp, "T1, ");
1472 }
1473
1474 switch (info.src_type) {
1475 case ADD_BLENDING:
1476 // Note: in this case, regs.uniform_const == location | 0x8
1477 // This probably means we can't load uniforms or immediates in the
1478 // same instruction. This re-uses the encoding that normally means
1479 // "disabled", where the low 4 bits are ignored. Perhaps the extra
1480 // 0x8 or'd in indicates this is happening.
1481 fprintf(fp, "location:%d, ", regs.uniform_const & 0x7);
1482 // fallthrough
1483 case ADD_ONE_SRC:
1484 dump_src(fp, ADD.src0, regs, consts, false);
1485 break;
1486 case ADD_TEX:
1487 case ADD_TEX_COMPACT: {
1488 int tex_index;
1489 int sampler_index;
1490 bool dualTex = false;
1491 if (info.src_type == ADD_TEX_COMPACT) {
1492 tex_index = (ADD.op >> 3) & 0x7;
1493 sampler_index = (ADD.op >> 7) & 0x7;
1494 bool unknown = (ADD.op & 0x40);
1495 // TODO: figure out if the unknown bit is ever 0
1496 if (!unknown)
1497 fprintf(fp, "unknown ");
1498 } else {
1499 uint64_t constVal = get_const(consts, regs);
1500 uint32_t controlBits = (ADD.op & 0x8) ? (constVal >> 32) : constVal;
1501 struct bifrost_tex_ctrl ctrl;
1502 memcpy((char *) &ctrl, (char *) &controlBits, sizeof(ctrl));
1503
1504 // TODO: figure out what actually triggers dual-tex
1505 if (ctrl.result_type == 9) {
1506 struct bifrost_dual_tex_ctrl dualCtrl;
1507 memcpy((char *) &dualCtrl, (char *) &controlBits, sizeof(ctrl));
1508 fprintf(fp, "(dualtex) tex0:%d samp0:%d tex1:%d samp1:%d ",
1509 dualCtrl.tex_index0, dualCtrl.sampler_index0,
1510 dualCtrl.tex_index1, dualCtrl.sampler_index1);
1511 if (dualCtrl.unk0 != 3)
1512 fprintf(fp, "unk:%d ", dualCtrl.unk0);
1513 dualTex = true;
1514 } else {
1515 if (ctrl.no_merge_index) {
1516 tex_index = ctrl.tex_index;
1517 sampler_index = ctrl.sampler_index;
1518 } else {
1519 tex_index = sampler_index = ctrl.tex_index;
1520 unsigned unk = ctrl.sampler_index >> 2;
1521 if (unk != 3)
1522 fprintf(fp, "unk:%d ", unk);
1523 if (ctrl.sampler_index & 1)
1524 tex_index = -1;
1525 if (ctrl.sampler_index & 2)
1526 sampler_index = -1;
1527 }
1528
1529 if (ctrl.unk0 != 3)
1530 fprintf(fp, "unk0:%d ", ctrl.unk0);
1531 if (ctrl.unk1)
1532 fprintf(fp, "unk1 ");
1533 if (ctrl.unk2 != 0xf)
1534 fprintf(fp, "unk2:%x ", ctrl.unk2);
1535
1536 switch (ctrl.result_type) {
1537 case 0x4:
1538 fprintf(fp, "f32 ");
1539 break;
1540 case 0xe:
1541 fprintf(fp, "i32 ");
1542 break;
1543 case 0xf:
1544 fprintf(fp, "u32 ");
1545 break;
1546 default:
1547 fprintf(fp, "unktype(%x) ", ctrl.result_type);
1548 }
1549
1550 switch (ctrl.tex_type) {
1551 case 0:
1552 fprintf(fp, "cube ");
1553 break;
1554 case 1:
1555 fprintf(fp, "buffer ");
1556 break;
1557 case 2:
1558 fprintf(fp, "2D ");
1559 break;
1560 case 3:
1561 fprintf(fp, "3D ");
1562 break;
1563 }
1564
1565 if (ctrl.is_shadow)
1566 fprintf(fp, "shadow ");
1567 if (ctrl.is_array)
1568 fprintf(fp, "array ");
1569
1570 if (!ctrl.filter) {
1571 if (ctrl.calc_gradients) {
1572 int comp = (controlBits >> 20) & 0x3;
1573 fprintf(fp, "txg comp:%d ", comp);
1574 } else {
1575 fprintf(fp, "txf ");
1576 }
1577 } else {
1578 if (!ctrl.not_supply_lod) {
1579 if (ctrl.compute_lod)
1580 fprintf(fp, "lod_bias ");
1581 else
1582 fprintf(fp, "lod ");
1583 }
1584
1585 if (!ctrl.calc_gradients)
1586 fprintf(fp, "grad ");
1587 }
1588
1589 if (ctrl.texel_offset)
1590 fprintf(fp, "offset ");
1591 }
1592 }
1593
1594 if (!dualTex) {
1595 if (tex_index == -1)
1596 fprintf(fp, "tex:indirect ");
1597 else
1598 fprintf(fp, "tex:%d ", tex_index);
1599
1600 if (sampler_index == -1)
1601 fprintf(fp, "samp:indirect ");
1602 else
1603 fprintf(fp, "samp:%d ", sampler_index);
1604 }
1605 break;
1606 }
1607 case ADD_VARYING_INTERP: {
1608 unsigned addr = ADD.op & 0x1f;
1609 if (addr < 0b10100) {
1610 // direct addr
1611 fprintf(fp, "%d", addr);
1612 } else if (addr < 0b11000) {
1613 if (addr == 22)
1614 fprintf(fp, "fragw");
1615 else if (addr == 23)
1616 fprintf(fp, "fragz");
1617 else
1618 fprintf(fp, "unk%d", addr);
1619 } else {
1620 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1621 }
1622 fprintf(fp, ", ");
1623 dump_src(fp, ADD.src0, regs, consts, false);
1624 break;
1625 }
1626 case ADD_VARYING_ADDRESS: {
1627 dump_src(fp, ADD.src0, regs, consts, false);
1628 fprintf(fp, ", ");
1629 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1630 fprintf(fp, ", ");
1631 unsigned location = (ADD.op >> 3) & 0x1f;
1632 if (location < 16) {
1633 fprintf(fp, "location:%d", location);
1634 } else if (location == 20) {
1635 fprintf(fp, "location:%u", (uint32_t) get_const(consts, regs));
1636 } else if (location == 21) {
1637 fprintf(fp, "location:%u", (uint32_t) (get_const(consts, regs) >> 32));
1638 } else {
1639 fprintf(fp, "location:%d(unk)", location);
1640 }
1641 break;
1642 }
1643 case ADD_LOAD_ATTR:
1644 fprintf(fp, "location:%d, ", (ADD.op >> 3) & 0x1f);
1645 case ADD_TWO_SRC:
1646 dump_src(fp, ADD.src0, regs, consts, false);
1647 fprintf(fp, ", ");
1648 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1649 break;
1650 case ADD_THREE_SRC:
1651 dump_src(fp, ADD.src0, regs, consts, false);
1652 fprintf(fp, ", ");
1653 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1654 fprintf(fp, ", ");
1655 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1656 break;
1657 case ADD_SHIFT: {
1658 struct bifrost_shift_add shift;
1659 memcpy(&shift, &ADD, sizeof(ADD));
1660 dump_src(fp, shift.src0, regs, consts, false);
1661 fprintf(fp, ", ");
1662 dump_src(fp, shift.src1, regs, consts, false);
1663 fprintf(fp, ", ");
1664 dump_src(fp, shift.src2, regs, consts, false);
1665 break;
1666 }
1667 case ADD_FADD:
1668 case ADD_FMINMAX:
1669 if (ADD.op & 0x10)
1670 fprintf(fp, "-");
1671 if (ADD.op & 0x1000)
1672 fprintf(fp, "abs(");
1673 dump_src(fp, ADD.src0, regs, consts, false);
1674 switch ((ADD.op >> 6) & 0x3) {
1675 case 3:
1676 fprintf(fp, ".x");
1677 break;
1678 default:
1679 break;
1680 }
1681 if (ADD.op & 0x1000)
1682 fprintf(fp, ")");
1683 fprintf(fp, ", ");
1684 if (ADD.op & 0x20)
1685 fprintf(fp, "-");
1686 if (ADD.op & 0x8)
1687 fprintf(fp, "abs(");
1688 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1689 switch ((ADD.op >> 6) & 0x3) {
1690 case 1:
1691 case 3:
1692 fprintf(fp, ".x");
1693 break;
1694 case 2:
1695 fprintf(fp, ".y");
1696 break;
1697 case 0:
1698 break;
1699 default:
1700 fprintf(fp, ".unk");
1701 break;
1702 }
1703 if (ADD.op & 0x8)
1704 fprintf(fp, ")");
1705 break;
1706 case ADD_FADD16:
1707 if (ADD.op & 0x10)
1708 fprintf(fp, "-");
1709 if (ADD.op & 0x1000)
1710 fprintf(fp, "abs(");
1711 dump_src(fp, ADD.src0, regs, consts, false);
1712 if (ADD.op & 0x1000)
1713 fprintf(fp, ")");
1714 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1715 fprintf(fp, ", ");
1716 if (ADD.op & 0x20)
1717 fprintf(fp, "-");
1718 if (ADD.op & 0x8)
1719 fprintf(fp, "abs(");
1720 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1721 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1722 if (ADD.op & 0x8)
1723 fprintf(fp, ")");
1724 break;
1725 case ADD_FMINMAX16: {
1726 bool abs1 = ADD.op & 0x8;
1727 bool abs2 = (ADD.op & 0x7) < ADD.src0;
1728 if (ADD.op & 0x10)
1729 fprintf(fp, "-");
1730 if (abs1 || abs2)
1731 fprintf(fp, "abs(");
1732 dump_src(fp, ADD.src0, regs, consts, false);
1733 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1734 if (abs1 || abs2)
1735 fprintf(fp, ")");
1736 fprintf(fp, ", ");
1737 if (ADD.op & 0x20)
1738 fprintf(fp, "-");
1739 if (abs1 && abs2)
1740 fprintf(fp, "abs(");
1741 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1742 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1743 if (abs1 && abs2)
1744 fprintf(fp, ")");
1745 break;
1746 }
1747 case ADD_FADDMscale: {
1748 if (ADD.op & 0x400)
1749 fprintf(fp, "-");
1750 if (ADD.op & 0x200)
1751 fprintf(fp, "abs(");
1752 dump_src(fp, ADD.src0, regs, consts, false);
1753 if (ADD.op & 0x200)
1754 fprintf(fp, ")");
1755
1756 fprintf(fp, ", ");
1757
1758 if (ADD.op & 0x800)
1759 fprintf(fp, "-");
1760 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1761
1762 fprintf(fp, ", ");
1763
1764 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1765 break;
1766 }
1767 case ADD_FCMP:
1768 if (ADD.op & 0x400) {
1769 fprintf(fp, "-");
1770 }
1771 if (ADD.op & 0x100) {
1772 fprintf(fp, "abs(");
1773 }
1774 dump_src(fp, ADD.src0, regs, consts, false);
1775 switch ((ADD.op >> 6) & 0x3) {
1776 case 3:
1777 fprintf(fp, ".x");
1778 break;
1779 default:
1780 break;
1781 }
1782 if (ADD.op & 0x100) {
1783 fprintf(fp, ")");
1784 }
1785 fprintf(fp, ", ");
1786 if (ADD.op & 0x200) {
1787 fprintf(fp, "abs(");
1788 }
1789 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1790 switch ((ADD.op >> 6) & 0x3) {
1791 case 1:
1792 case 3:
1793 fprintf(fp, ".x");
1794 break;
1795 case 2:
1796 fprintf(fp, ".y");
1797 break;
1798 case 0:
1799 break;
1800 default:
1801 fprintf(fp, ".unk");
1802 break;
1803 }
1804 if (ADD.op & 0x200) {
1805 fprintf(fp, ")");
1806 }
1807 break;
1808 case ADD_FCMP16:
1809 dump_src(fp, ADD.src0, regs, consts, false);
1810 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1811 fprintf(fp, ", ");
1812 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1813 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1814 break;
1815 case ADD_BRANCH: {
1816 enum bifrost_branch_code code = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1817 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1818 if (code != BR_ALWAYS) {
1819 dump_src(fp, ADD.src0, regs, consts, false);
1820 switch (size) {
1821 case BR_SIZE_16XX:
1822 fprintf(fp, ".x");
1823 break;
1824 case BR_SIZE_16YY:
1825 case BR_SIZE_16YX0:
1826 case BR_SIZE_16YX1:
1827 fprintf(fp, ".y");
1828 break;
1829 case BR_SIZE_ZERO: {
1830 unsigned ctrl = (ADD.op >> 1) & 0x3;
1831 switch (ctrl) {
1832 case 1:
1833 fprintf(fp, ".y");
1834 break;
1835 case 2:
1836 fprintf(fp, ".x");
1837 break;
1838 default:
1839 break;
1840 }
1841 }
1842 default:
1843 break;
1844 }
1845 fprintf(fp, ", ");
1846 }
1847 if (code != BR_ALWAYS && size != BR_SIZE_ZERO) {
1848 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1849 switch (size) {
1850 case BR_SIZE_16XX:
1851 case BR_SIZE_16YX0:
1852 case BR_SIZE_16YX1:
1853 case BR_SIZE_32_AND_16X:
1854 fprintf(fp, ".x");
1855 break;
1856 case BR_SIZE_16YY:
1857 case BR_SIZE_32_AND_16Y:
1858 fprintf(fp, ".y");
1859 break;
1860 default:
1861 break;
1862 }
1863 fprintf(fp, ", ");
1864 }
1865 // I haven't had the chance to test if this actually specifies the
1866 // branch offset, since I couldn't get it to produce values other
1867 // than 5 (uniform/const high), but these three bits are always
1868 // consistent across branch instructions, so it makes sense...
1869 int offsetSrc = (ADD.op >> 3) & 0x7;
1870 if (offsetSrc == 4 || offsetSrc == 5) {
1871 // If the offset is known/constant, we can decode it
1872 uint32_t raw_offset;
1873 if (offsetSrc == 4)
1874 raw_offset = get_const(consts, regs);
1875 else
1876 raw_offset = get_const(consts, regs) >> 32;
1877 // The high 4 bits are flags, while the rest is the
1878 // twos-complement offset in bytes (here we convert to
1879 // clauses).
1880 int32_t branch_offset = ((int32_t) raw_offset << 4) >> 8;
1881
1882 // If high4 is the high 4 bits of the last 64-bit constant,
1883 // this is calculated as (high4 + 4) & 0xf, or 0 if the branch
1884 // offset itself is the last constant. Not sure if this is
1885 // actually used, or just garbage in unused bits, but in any
1886 // case, we can just ignore it here since it's redundant. Note
1887 // that if there is any padding, this will be 4 since the
1888 // padding counts as the last constant.
1889 unsigned flags = raw_offset >> 28;
1890 (void) flags;
1891
1892 // Note: the offset is in bytes, relative to the beginning of the
1893 // current clause, so a zero offset would be a loop back to the
1894 // same clause (annoyingly different from Midgard).
1895 fprintf(fp, "clause_%d", offset + branch_offset);
1896 } else {
1897 dump_src(fp, offsetSrc, regs, consts, false);
1898 }
1899 }
1900 }
1901 if (info.has_data_reg) {
1902 fprintf(fp, ", R%d", data_reg);
1903 }
1904 fprintf(fp, "\n");
1905 }
1906
1907 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
1908 struct bifrost_regs next_regs, uint64_t *consts,
1909 unsigned data_reg, unsigned offset, bool verbose)
1910 {
1911 struct bifrost_regs regs;
1912 memcpy((char *) &regs, (char *) &instr->reg_bits, sizeof(regs));
1913
1914 if (verbose) {
1915 fprintf(fp, "# regs: %016" PRIx64 "\n", instr->reg_bits);
1916 dump_regs(fp, regs);
1917 }
1918 dump_fma(fp, instr->fma_bits, regs, next_regs, consts, verbose);
1919 dump_add(fp, instr->add_bits, regs, next_regs, consts, data_reg, offset, verbose);
1920 }
1921
1922 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose)
1923 {
1924 // State for a decoded clause
1925 struct bifrost_alu_inst instrs[8] = {};
1926 uint64_t consts[6] = {};
1927 unsigned num_instrs = 0;
1928 unsigned num_consts = 0;
1929 uint64_t header_bits = 0;
1930 bool stopbit = false;
1931
1932 unsigned i;
1933 for (i = 0; ; i++, words += 4) {
1934 if (verbose) {
1935 fprintf(fp, "# ");
1936 for (int j = 0; j < 4; j++)
1937 fprintf(fp, "%08x ", words[3 - j]); // low bit on the right
1938 fprintf(fp, "\n");
1939 }
1940 unsigned tag = bits(words[0], 0, 8);
1941
1942 // speculatively decode some things that are common between many formats, so we can share some code
1943 struct bifrost_alu_inst main_instr = {};
1944 // 20 bits
1945 main_instr.add_bits = bits(words[2], 2, 32 - 13);
1946 // 23 bits
1947 main_instr.fma_bits = bits(words[1], 11, 32) | bits(words[2], 0, 2) << (32 - 11);
1948 // 35 bits
1949 main_instr.reg_bits = ((uint64_t) bits(words[1], 0, 11)) << 24 | (uint64_t) bits(words[0], 8, 32);
1950
1951 uint64_t const0 = bits(words[0], 8, 32) << 4 | (uint64_t) words[1] << 28 | bits(words[2], 0, 4) << 60;
1952 uint64_t const1 = bits(words[2], 4, 32) << 4 | (uint64_t) words[3] << 32;
1953
1954 bool stop = tag & 0x40;
1955
1956 if (verbose) {
1957 fprintf(fp, "# tag: 0x%02x\n", tag);
1958 }
1959 if (tag & 0x80) {
1960 unsigned idx = stop ? 5 : 2;
1961 main_instr.add_bits |= ((tag >> 3) & 0x7) << 17;
1962 instrs[idx + 1] = main_instr;
1963 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17);
1964 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10;
1965 consts[0] = bits(words[3], 17, 32) << 4;
1966 } else {
1967 bool done = false;
1968 switch ((tag >> 3) & 0x7) {
1969 case 0x0:
1970 switch (tag & 0x7) {
1971 case 0x3:
1972 main_instr.add_bits |= bits(words[3], 29, 32) << 17;
1973 instrs[1] = main_instr;
1974 num_instrs = 2;
1975 done = stop;
1976 break;
1977 case 0x4:
1978 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1979 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1980 consts[0] = const0;
1981 num_instrs = 3;
1982 num_consts = 1;
1983 done = stop;
1984 break;
1985 case 0x1:
1986 case 0x5:
1987 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1988 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1989 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1990 instrs[3] = main_instr;
1991 if ((tag & 0x7) == 0x5) {
1992 num_instrs = 4;
1993 done = stop;
1994 }
1995 break;
1996 case 0x6:
1997 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1998 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1999 consts[0] = const0;
2000 num_instrs = 6;
2001 num_consts = 1;
2002 done = stop;
2003 break;
2004 case 0x7:
2005 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2006 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
2007 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
2008 instrs[6] = main_instr;
2009 num_instrs = 7;
2010 done = stop;
2011 break;
2012 default:
2013 fprintf(fp, "unknown tag bits 0x%02x\n", tag);
2014 }
2015 break;
2016 case 0x2:
2017 case 0x3: {
2018 unsigned idx = ((tag >> 3) & 0x7) == 2 ? 4 : 7;
2019 main_instr.add_bits |= (tag & 0x7) << 17;
2020 instrs[idx] = main_instr;
2021 consts[0] |= (bits(words[2], 19, 32) | ((uint64_t) words[3] << 13)) << 19;
2022 num_consts = 1;
2023 num_instrs = idx + 1;
2024 done = stop;
2025 break;
2026 }
2027 case 0x4: {
2028 unsigned idx = stop ? 4 : 1;
2029 main_instr.add_bits |= (tag & 0x7) << 17;
2030 instrs[idx] = main_instr;
2031 instrs[idx + 1].fma_bits |= bits(words[3], 22, 32);
2032 instrs[idx + 1].reg_bits = bits(words[2], 19, 32) | (bits(words[3], 0, 22) << (32 - 19));
2033 break;
2034 }
2035 case 0x1:
2036 // only constants can come after this
2037 num_instrs = 1;
2038 done = stop;
2039 case 0x5:
2040 header_bits = bits(words[2], 19, 32) | ((uint64_t) words[3] << (32 - 19));
2041 main_instr.add_bits |= (tag & 0x7) << 17;
2042 instrs[0] = main_instr;
2043 break;
2044 case 0x6:
2045 case 0x7: {
2046 unsigned pos = tag & 0xf;
2047 // note that `pos' encodes both the total number of
2048 // instructions and the position in the constant stream,
2049 // presumably because decoded constants and instructions
2050 // share a buffer in the decoder, but we only care about
2051 // the position in the constant stream; the total number of
2052 // instructions is redundant.
2053 unsigned const_idx = 0;
2054 switch (pos) {
2055 case 0:
2056 case 1:
2057 case 2:
2058 case 6:
2059 const_idx = 0;
2060 break;
2061 case 3:
2062 case 4:
2063 case 7:
2064 case 9:
2065 const_idx = 1;
2066 break;
2067 case 5:
2068 case 0xa:
2069 const_idx = 2;
2070 break;
2071 case 8:
2072 case 0xb:
2073 case 0xc:
2074 const_idx = 3;
2075 break;
2076 case 0xd:
2077 const_idx = 4;
2078 break;
2079 default:
2080 fprintf(fp, "# unknown pos 0x%x\n", pos);
2081 break;
2082 }
2083
2084 if (num_consts < const_idx + 2)
2085 num_consts = const_idx + 2;
2086
2087 consts[const_idx] = const0;
2088 consts[const_idx + 1] = const1;
2089 done = stop;
2090 break;
2091 }
2092 default:
2093 break;
2094 }
2095
2096 if (done)
2097 break;
2098 }
2099 }
2100
2101 *size = i + 1;
2102
2103 if (verbose) {
2104 fprintf(fp, "# header: %012" PRIx64 "\n", header_bits);
2105 }
2106
2107 struct bifrost_header header;
2108 memcpy((char *) &header, (char *) &header_bits, sizeof(struct bifrost_header));
2109 dump_header(fp, header, verbose);
2110 if (!header.no_end_of_shader)
2111 stopbit = true;
2112
2113 fprintf(fp, "{\n");
2114 for (i = 0; i < num_instrs; i++) {
2115 struct bifrost_regs next_regs;
2116 if (i + 1 == num_instrs) {
2117 memcpy((char *) &next_regs, (char *) &instrs[0].reg_bits,
2118 sizeof(next_regs));
2119 } else {
2120 memcpy((char *) &next_regs, (char *) &instrs[i + 1].reg_bits,
2121 sizeof(next_regs));
2122 }
2123
2124 dump_instr(fp, &instrs[i], next_regs, consts, header.datareg, offset, verbose);
2125 }
2126 fprintf(fp, "}\n");
2127
2128 if (verbose) {
2129 for (unsigned i = 0; i < num_consts; i++) {
2130 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i, consts[i] & 0xffffffff);
2131 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i + 1, consts[i] >> 32);
2132 }
2133 }
2134 return stopbit;
2135 }
2136
2137 void disassemble_bifrost(FILE *fp, uint8_t *code, size_t size, bool verbose)
2138 {
2139 uint32_t *words = (uint32_t *) code;
2140 uint32_t *words_end = words + (size / 4);
2141 // used for displaying branch targets
2142 unsigned offset = 0;
2143 while (words != words_end) {
2144 // we don't know what the program-end bit is quite yet, so for now just
2145 // assume that an all-0 quadword is padding
2146 uint32_t zero[4] = {};
2147 if (memcmp(words, zero, 4 * sizeof(uint32_t)) == 0)
2148 break;
2149 fprintf(fp, "clause_%d:\n", offset);
2150 unsigned size;
2151 if (dump_clause(fp, words, &size, offset, verbose) == true) {
2152 break;
2153 }
2154 words += size * 4;
2155 offset += size;
2156 }
2157 }
2158