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pan/bi: Move some print routines out of the disasm
[mesa.git] / src / panfrost / bifrost / disassemble.c
1 /*
2 * Copyright (C) 2019 Connor Abbott <cwabbott0@gmail.com>
3 * Copyright (C) 2019 Lyude Paul <thatslyude@gmail.com>
4 * Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #include <stdbool.h>
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <assert.h>
30 #include <inttypes.h>
31 #include <string.h>
32
33 #include "bifrost.h"
34 #include "disassemble.h"
35 #include "bi_print.h"
36 #include "util/macros.h"
37
38 // return bits (high, lo]
39 static uint64_t bits(uint32_t word, unsigned lo, unsigned high)
40 {
41 if (high == 32)
42 return word >> lo;
43 return (word & ((1 << high) - 1)) >> lo;
44 }
45
46 // each of these structs represents an instruction that's dispatched in one
47 // cycle. Note that these instructions are packed in funny ways within the
48 // clause, hence the need for a separate struct.
49 struct bifrost_alu_inst {
50 uint32_t fma_bits;
51 uint32_t add_bits;
52 uint64_t reg_bits;
53 };
54
55 static unsigned get_reg0(struct bifrost_regs regs)
56 {
57 if (regs.ctrl == 0)
58 return regs.reg0 | ((regs.reg1 & 0x1) << 5);
59
60 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0;
61 }
62
63 static unsigned get_reg1(struct bifrost_regs regs)
64 {
65 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1;
66 }
67
68 // this represents the decoded version of the ctrl register field.
69 struct bifrost_reg_ctrl {
70 bool read_reg0;
71 bool read_reg1;
72 bool read_reg3;
73 enum bifrost_reg_write_unit fma_write_unit;
74 enum bifrost_reg_write_unit add_write_unit;
75 bool clause_start;
76 };
77
78 enum fma_src_type {
79 FMA_ONE_SRC,
80 FMA_TWO_SRC,
81 FMA_FADD,
82 FMA_FMINMAX,
83 FMA_FADD16,
84 FMA_FMINMAX16,
85 FMA_FCMP,
86 FMA_FCMP16,
87 FMA_THREE_SRC,
88 FMA_SHIFT,
89 FMA_FMA,
90 FMA_FMA16,
91 FMA_CSEL4,
92 FMA_FMA_MSCALE,
93 FMA_SHIFT_ADD64,
94 };
95
96 struct fma_op_info {
97 bool extended;
98 unsigned op;
99 char name[30];
100 enum fma_src_type src_type;
101 };
102
103 enum add_src_type {
104 ADD_ONE_SRC,
105 ADD_TWO_SRC,
106 ADD_FADD,
107 ADD_FMINMAX,
108 ADD_FADD16,
109 ADD_FMINMAX16,
110 ADD_THREE_SRC,
111 ADD_SHIFT,
112 ADD_FADDMscale,
113 ADD_FCMP,
114 ADD_FCMP16,
115 ADD_TEX_COMPACT, // texture instruction with embedded sampler
116 ADD_TEX, // texture instruction with sampler/etc. in uniform port
117 ADD_VARYING_INTERP,
118 ADD_BLENDING,
119 ADD_LOAD_ATTR,
120 ADD_VARYING_ADDRESS,
121 ADD_BRANCH,
122 };
123
124 struct add_op_info {
125 unsigned op;
126 char name[30];
127 enum add_src_type src_type;
128 bool has_data_reg;
129 };
130
131 void dump_header(FILE *fp, struct bifrost_header header, bool verbose);
132 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
133 struct bifrost_regs next_regs, uint64_t *consts,
134 unsigned data_reg, unsigned offset, bool verbose);
135 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose);
136
137 void dump_header(FILE *fp, struct bifrost_header header, bool verbose)
138 {
139 if (header.clause_type != 0) {
140 fprintf(fp, "id(%du) ", header.scoreboard_index);
141 }
142
143 if (header.scoreboard_deps != 0) {
144 fprintf(fp, "next-wait(");
145 bool first = true;
146 for (unsigned i = 0; i < 8; i++) {
147 if (header.scoreboard_deps & (1 << i)) {
148 if (!first) {
149 fprintf(fp, ", ");
150 }
151 fprintf(fp, "%d", i);
152 first = false;
153 }
154 }
155 fprintf(fp, ") ");
156 }
157
158 if (header.datareg_writebarrier)
159 fprintf(fp, "data-reg-barrier ");
160
161 if (!header.no_end_of_shader)
162 fprintf(fp, "eos ");
163
164 if (!header.back_to_back) {
165 fprintf(fp, "nbb ");
166 if (header.branch_cond)
167 fprintf(fp, "branch-cond ");
168 else
169 fprintf(fp, "branch-uncond ");
170 }
171
172 if (header.elide_writes)
173 fprintf(fp, "we ");
174
175 if (header.suppress_inf)
176 fprintf(fp, "suppress-inf ");
177 if (header.suppress_nan)
178 fprintf(fp, "suppress-nan ");
179
180 if (header.unk0)
181 fprintf(fp, "unk0 ");
182 if (header.unk1)
183 fprintf(fp, "unk1 ");
184 if (header.unk2)
185 fprintf(fp, "unk2 ");
186 if (header.unk3)
187 fprintf(fp, "unk3 ");
188 if (header.unk4)
189 fprintf(fp, "unk4 ");
190
191 fprintf(fp, "\n");
192
193 if (verbose) {
194 fprintf(fp, "# clause type %d, next clause type %d\n",
195 header.clause_type, header.next_clause_type);
196 }
197 }
198
199 static struct bifrost_reg_ctrl DecodeRegCtrl(FILE *fp, struct bifrost_regs regs)
200 {
201 struct bifrost_reg_ctrl decoded = {};
202 unsigned ctrl;
203 if (regs.ctrl == 0) {
204 ctrl = regs.reg1 >> 2;
205 decoded.read_reg0 = !(regs.reg1 & 0x2);
206 decoded.read_reg1 = false;
207 } else {
208 ctrl = regs.ctrl;
209 decoded.read_reg0 = decoded.read_reg1 = true;
210 }
211 switch (ctrl) {
212 case 1:
213 decoded.fma_write_unit = REG_WRITE_TWO;
214 break;
215 case 2:
216 case 3:
217 decoded.fma_write_unit = REG_WRITE_TWO;
218 decoded.read_reg3 = true;
219 break;
220 case 4:
221 decoded.read_reg3 = true;
222 break;
223 case 5:
224 decoded.add_write_unit = REG_WRITE_TWO;
225 break;
226 case 6:
227 decoded.add_write_unit = REG_WRITE_TWO;
228 decoded.read_reg3 = true;
229 break;
230 case 8:
231 decoded.clause_start = true;
232 break;
233 case 9:
234 decoded.fma_write_unit = REG_WRITE_TWO;
235 decoded.clause_start = true;
236 break;
237 case 11:
238 break;
239 case 12:
240 decoded.read_reg3 = true;
241 decoded.clause_start = true;
242 break;
243 case 13:
244 decoded.add_write_unit = REG_WRITE_TWO;
245 decoded.clause_start = true;
246 break;
247
248 case 7:
249 case 15:
250 decoded.fma_write_unit = REG_WRITE_THREE;
251 decoded.add_write_unit = REG_WRITE_TWO;
252 break;
253 default:
254 fprintf(fp, "# unknown reg ctrl %d\n", ctrl);
255 }
256
257 return decoded;
258 }
259
260 // Pass in the add_write_unit or fma_write_unit, and this returns which register
261 // the ADD/FMA units are writing to
262 static unsigned GetRegToWrite(enum bifrost_reg_write_unit unit, struct bifrost_regs regs)
263 {
264 switch (unit) {
265 case REG_WRITE_TWO:
266 return regs.reg2;
267 case REG_WRITE_THREE:
268 return regs.reg3;
269 default: /* REG_WRITE_NONE */
270 assert(0);
271 return 0;
272 }
273 }
274
275 static void dump_regs(FILE *fp, struct bifrost_regs srcs)
276 {
277 struct bifrost_reg_ctrl ctrl = DecodeRegCtrl(fp, srcs);
278 fprintf(fp, "# ");
279 if (ctrl.read_reg0)
280 fprintf(fp, "port 0: R%d ", get_reg0(srcs));
281 if (ctrl.read_reg1)
282 fprintf(fp, "port 1: R%d ", get_reg1(srcs));
283
284 if (ctrl.fma_write_unit == REG_WRITE_TWO)
285 fprintf(fp, "port 2: R%d (write FMA) ", srcs.reg2);
286 else if (ctrl.add_write_unit == REG_WRITE_TWO)
287 fprintf(fp, "port 2: R%d (write ADD) ", srcs.reg2);
288
289 if (ctrl.fma_write_unit == REG_WRITE_THREE)
290 fprintf(fp, "port 3: R%d (write FMA) ", srcs.reg3);
291 else if (ctrl.add_write_unit == REG_WRITE_THREE)
292 fprintf(fp, "port 3: R%d (write ADD) ", srcs.reg3);
293 else if (ctrl.read_reg3)
294 fprintf(fp, "port 3: R%d (read) ", srcs.reg3);
295
296 if (srcs.uniform_const) {
297 if (srcs.uniform_const & 0x80) {
298 fprintf(fp, "uniform: U%d", (srcs.uniform_const & 0x7f) * 2);
299 }
300 }
301
302 fprintf(fp, "\n");
303 }
304 static void dump_const_imm(FILE *fp, uint32_t imm)
305 {
306 union {
307 float f;
308 uint32_t i;
309 } fi;
310 fi.i = imm;
311 fprintf(fp, "0x%08x /* %f */", imm, fi.f);
312 }
313
314 static uint64_t get_const(uint64_t *consts, struct bifrost_regs srcs)
315 {
316 unsigned low_bits = srcs.uniform_const & 0xf;
317 uint64_t imm;
318 switch (srcs.uniform_const >> 4) {
319 case 4:
320 imm = consts[0];
321 break;
322 case 5:
323 imm = consts[1];
324 break;
325 case 6:
326 imm = consts[2];
327 break;
328 case 7:
329 imm = consts[3];
330 break;
331 case 2:
332 imm = consts[4];
333 break;
334 case 3:
335 imm = consts[5];
336 break;
337 default:
338 assert(0);
339 break;
340 }
341 return imm | low_bits;
342 }
343
344 static void dump_uniform_const_src(FILE *fp, struct bifrost_regs srcs, uint64_t *consts, bool high32)
345 {
346 if (srcs.uniform_const & 0x80) {
347 unsigned uniform = (srcs.uniform_const & 0x7f) * 2;
348 fprintf(fp, "U%d", uniform + (high32 ? 1 : 0));
349 } else if (srcs.uniform_const >= 0x20) {
350 uint64_t imm = get_const(consts, srcs);
351 if (high32)
352 dump_const_imm(fp, imm >> 32);
353 else
354 dump_const_imm(fp, imm);
355 } else {
356 switch (srcs.uniform_const) {
357 case 0:
358 fprintf(fp, "0");
359 break;
360 case 5:
361 fprintf(fp, "atest-data");
362 break;
363 case 6:
364 fprintf(fp, "sample-ptr");
365 break;
366 case 8:
367 case 9:
368 case 10:
369 case 11:
370 case 12:
371 case 13:
372 case 14:
373 case 15:
374 fprintf(fp, "blend-descriptor%u", (unsigned) srcs.uniform_const - 8);
375 break;
376 default:
377 fprintf(fp, "unkConst%u", (unsigned) srcs.uniform_const);
378 break;
379 }
380
381 if (high32)
382 fprintf(fp, ".y");
383 else
384 fprintf(fp, ".x");
385 }
386 }
387
388 static void dump_src(FILE *fp, unsigned src, struct bifrost_regs srcs, uint64_t *consts, bool isFMA)
389 {
390 switch (src) {
391 case 0:
392 fprintf(fp, "R%d", get_reg0(srcs));
393 break;
394 case 1:
395 fprintf(fp, "R%d", get_reg1(srcs));
396 break;
397 case 2:
398 fprintf(fp, "R%d", srcs.reg3);
399 break;
400 case 3:
401 if (isFMA)
402 fprintf(fp, "0");
403 else
404 fprintf(fp, "T"); // i.e. the output of FMA this cycle
405 break;
406 case 4:
407 dump_uniform_const_src(fp, srcs, consts, false);
408 break;
409 case 5:
410 dump_uniform_const_src(fp, srcs, consts, true);
411 break;
412 case 6:
413 fprintf(fp, "T0");
414 break;
415 case 7:
416 fprintf(fp, "T1");
417 break;
418 }
419 }
420
421 static const struct fma_op_info FMAOpInfos[] = {
422 { false, 0x00000, "FMA.f32", FMA_FMA },
423 { false, 0x40000, "MAX.f32", FMA_FMINMAX },
424 { false, 0x44000, "MIN.f32", FMA_FMINMAX },
425 { false, 0x48000, "FCMP.GL", FMA_FCMP },
426 { false, 0x4c000, "FCMP.D3D", FMA_FCMP },
427 { false, 0x4ff98, "ADD.i32", FMA_TWO_SRC },
428 { false, 0x4ffd8, "SUB.i32", FMA_TWO_SRC },
429 { false, 0x4fff0, "SUBB.i32", FMA_TWO_SRC },
430 { false, 0x50000, "FMA_MSCALE", FMA_FMA_MSCALE },
431 { false, 0x58000, "ADD.f32", FMA_FADD },
432 { false, 0x5c000, "CSEL4", FMA_CSEL4 },
433 { false, 0x5d8d0, "ICMP.D3D.GT.v2i16", FMA_TWO_SRC },
434 { false, 0x5d9d0, "UCMP.D3D.GT.v2i16", FMA_TWO_SRC },
435 { false, 0x5dad0, "ICMP.D3D.GE.v2i16", FMA_TWO_SRC },
436 { false, 0x5dbd0, "UCMP.D3D.GE.v2i16", FMA_TWO_SRC },
437 { false, 0x5dcd0, "ICMP.D3D.EQ.v2i16", FMA_TWO_SRC },
438 { false, 0x5de40, "ICMP.GL.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? 1 : 0
439 { false, 0x5de48, "ICMP.GL.GE.i32", FMA_TWO_SRC },
440 { false, 0x5de50, "UCMP.GL.GT.i32", FMA_TWO_SRC },
441 { false, 0x5de58, "UCMP.GL.GE.i32", FMA_TWO_SRC },
442 { false, 0x5de60, "ICMP.GL.EQ.i32", FMA_TWO_SRC },
443 { false, 0x5dec0, "ICMP.D3D.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? ~0 : 0
444 { false, 0x5dec8, "ICMP.D3D.GE.i32", FMA_TWO_SRC },
445 { false, 0x5ded0, "UCMP.D3D.GT.i32", FMA_TWO_SRC },
446 { false, 0x5ded8, "UCMP.D3D.GE.i32", FMA_TWO_SRC },
447 { false, 0x5dee0, "ICMP.D3D.EQ.i32", FMA_TWO_SRC },
448 { false, 0x60000, "RSHIFT_NAND", FMA_SHIFT },
449 { false, 0x61000, "RSHIFT_AND", FMA_SHIFT },
450 { false, 0x62000, "LSHIFT_NAND", FMA_SHIFT },
451 { false, 0x63000, "LSHIFT_AND", FMA_SHIFT }, // (src0 << src2) & src1
452 { false, 0x64000, "RSHIFT_XOR", FMA_SHIFT },
453 { false, 0x65200, "LSHIFT_ADD.i32", FMA_THREE_SRC },
454 { false, 0x65600, "LSHIFT_SUB.i32", FMA_THREE_SRC }, // (src0 << src2) - src1
455 { false, 0x65a00, "LSHIFT_RSUB.i32", FMA_THREE_SRC }, // src1 - (src0 << src2)
456 { false, 0x65e00, "RSHIFT_ADD.i32", FMA_THREE_SRC },
457 { false, 0x66200, "RSHIFT_SUB.i32", FMA_THREE_SRC },
458 { false, 0x66600, "RSHIFT_RSUB.i32", FMA_THREE_SRC },
459 { false, 0x66a00, "ARSHIFT_ADD.i32", FMA_THREE_SRC },
460 { false, 0x66e00, "ARSHIFT_SUB.i32", FMA_THREE_SRC },
461 { false, 0x67200, "ARSHIFT_RSUB.i32", FMA_THREE_SRC },
462 { false, 0x80000, "FMA.v2f16", FMA_FMA16 },
463 { false, 0xc0000, "MAX.v2f16", FMA_FMINMAX16 },
464 { false, 0xc4000, "MIN.v2f16", FMA_FMINMAX16 },
465 { false, 0xc8000, "FCMP.GL", FMA_FCMP16 },
466 { false, 0xcc000, "FCMP.D3D", FMA_FCMP16 },
467 { false, 0xcf900, "ADD.v2i16", FMA_TWO_SRC },
468 { false, 0xcfc10, "ADDC.i32", FMA_TWO_SRC },
469 { false, 0xcfd80, "ADD.i32.i16.X", FMA_TWO_SRC },
470 { false, 0xcfd90, "ADD.i32.u16.X", FMA_TWO_SRC },
471 { false, 0xcfdc0, "ADD.i32.i16.Y", FMA_TWO_SRC },
472 { false, 0xcfdd0, "ADD.i32.u16.Y", FMA_TWO_SRC },
473 { false, 0xd8000, "ADD.v2f16", FMA_FADD16 },
474 { false, 0xdc000, "CSEL4.v16", FMA_CSEL4 },
475 { false, 0xdd000, "F32_TO_F16", FMA_TWO_SRC },
476 { true, 0x00046, "F16_TO_I16.XX", FMA_ONE_SRC },
477 { true, 0x00047, "F16_TO_U16.XX", FMA_ONE_SRC },
478 { true, 0x0004e, "F16_TO_I16.YX", FMA_ONE_SRC },
479 { true, 0x0004f, "F16_TO_U16.YX", FMA_ONE_SRC },
480 { true, 0x00056, "F16_TO_I16.XY", FMA_ONE_SRC },
481 { true, 0x00057, "F16_TO_U16.XY", FMA_ONE_SRC },
482 { true, 0x0005e, "F16_TO_I16.YY", FMA_ONE_SRC },
483 { true, 0x0005f, "F16_TO_U16.YY", FMA_ONE_SRC },
484 { true, 0x000c0, "I16_TO_F16.XX", FMA_ONE_SRC },
485 { true, 0x000c1, "U16_TO_F16.XX", FMA_ONE_SRC },
486 { true, 0x000c8, "I16_TO_F16.YX", FMA_ONE_SRC },
487 { true, 0x000c9, "U16_TO_F16.YX", FMA_ONE_SRC },
488 { true, 0x000d0, "I16_TO_F16.XY", FMA_ONE_SRC },
489 { true, 0x000d1, "U16_TO_F16.XY", FMA_ONE_SRC },
490 { true, 0x000d8, "I16_TO_F16.YY", FMA_ONE_SRC },
491 { true, 0x000d9, "U16_TO_F16.YY", FMA_ONE_SRC },
492 { true, 0x00136, "F32_TO_I32", FMA_ONE_SRC },
493 { true, 0x00137, "F32_TO_U32", FMA_ONE_SRC },
494 { true, 0x00178, "I32_TO_F32", FMA_ONE_SRC },
495 { true, 0x00179, "U32_TO_F32", FMA_ONE_SRC },
496 { true, 0x00198, "I16_TO_I32.X", FMA_ONE_SRC },
497 { true, 0x00199, "U16_TO_U32.X", FMA_ONE_SRC },
498 { true, 0x0019a, "I16_TO_I32.Y", FMA_ONE_SRC },
499 { true, 0x0019b, "U16_TO_U32.Y", FMA_ONE_SRC },
500 { true, 0x0019c, "I16_TO_F32.X", FMA_ONE_SRC },
501 { true, 0x0019d, "U16_TO_F32.X", FMA_ONE_SRC },
502 { true, 0x0019e, "I16_TO_F32.Y", FMA_ONE_SRC },
503 { true, 0x0019f, "U16_TO_F32.Y", FMA_ONE_SRC },
504 { true, 0x001a2, "F16_TO_F32.X", FMA_ONE_SRC },
505 { true, 0x001a3, "F16_TO_F32.Y", FMA_ONE_SRC },
506 { true, 0x0032c, "NOP", FMA_ONE_SRC },
507 { true, 0x0032d, "MOV", FMA_ONE_SRC },
508 { true, 0x0032f, "SWZ.YY.v2i16", FMA_ONE_SRC },
509 { true, 0x00345, "LOG_FREXPM", FMA_ONE_SRC },
510 { true, 0x00365, "FRCP_FREXPM", FMA_ONE_SRC },
511 { true, 0x00375, "FSQRT_FREXPM", FMA_ONE_SRC },
512 { true, 0x0038d, "FRCP_FREXPE", FMA_ONE_SRC },
513 { true, 0x003a5, "FSQRT_FREXPE", FMA_ONE_SRC },
514 { true, 0x003ad, "FRSQ_FREXPE", FMA_ONE_SRC },
515 { true, 0x003c5, "LOG_FREXPE", FMA_ONE_SRC },
516 { true, 0x003fa, "CLZ", FMA_ONE_SRC },
517 { true, 0x00b80, "IMAX3", FMA_THREE_SRC },
518 { true, 0x00bc0, "UMAX3", FMA_THREE_SRC },
519 { true, 0x00c00, "IMIN3", FMA_THREE_SRC },
520 { true, 0x00c40, "UMIN3", FMA_THREE_SRC },
521 { true, 0x00ec5, "ROUND", FMA_ONE_SRC },
522 { true, 0x00f40, "CSEL", FMA_THREE_SRC }, // src2 != 0 ? src1 : src0
523 { true, 0x00fc0, "MUX.i32", FMA_THREE_SRC }, // see ADD comment
524 { true, 0x01805, "ROUNDEVEN", FMA_ONE_SRC },
525 { true, 0x01845, "CEIL", FMA_ONE_SRC },
526 { true, 0x01885, "FLOOR", FMA_ONE_SRC },
527 { true, 0x018c5, "TRUNC", FMA_ONE_SRC },
528 { true, 0x019b0, "ATAN_LDEXP.Y.f32", FMA_TWO_SRC },
529 { true, 0x019b8, "ATAN_LDEXP.X.f32", FMA_TWO_SRC },
530 { true, 0x01c80, "LSHIFT_ADD_LOW32.u32", FMA_SHIFT_ADD64 },
531 { true, 0x01cc0, "LSHIFT_ADD_LOW32.i64", FMA_SHIFT_ADD64 },
532 { true, 0x01d80, "LSHIFT_ADD_LOW32.i32", FMA_SHIFT_ADD64 },
533 { true, 0x01e00, "SEL.XX.i16", FMA_TWO_SRC },
534 { true, 0x01e08, "SEL.YX.i16", FMA_TWO_SRC },
535 { true, 0x01e10, "SEL.XY.i16", FMA_TWO_SRC },
536 { true, 0x01e18, "SEL.YY.i16", FMA_TWO_SRC },
537 { true, 0x00800, "IMAD", FMA_THREE_SRC },
538 { true, 0x078db, "POPCNT", FMA_ONE_SRC },
539 };
540
541 static struct fma_op_info find_fma_op_info(unsigned op, bool extended)
542 {
543 for (unsigned i = 0; i < ARRAY_SIZE(FMAOpInfos); i++) {
544 unsigned opCmp = ~0;
545
546 if (FMAOpInfos[i].extended != extended)
547 continue;
548
549 if (extended)
550 op &= ~0xe0000;
551
552 switch (FMAOpInfos[i].src_type) {
553 case FMA_ONE_SRC:
554 opCmp = op;
555 break;
556 case FMA_TWO_SRC:
557 opCmp = op & ~0x7;
558 break;
559 case FMA_FCMP:
560 case FMA_FCMP16:
561 opCmp = op & ~0x1fff;
562 break;
563 case FMA_THREE_SRC:
564 case FMA_SHIFT_ADD64:
565 opCmp = op & ~0x3f;
566 break;
567 case FMA_FADD:
568 case FMA_FMINMAX:
569 case FMA_FADD16:
570 case FMA_FMINMAX16:
571 opCmp = op & ~0x3fff;
572 break;
573 case FMA_FMA:
574 case FMA_FMA16:
575 opCmp = op & ~0x3ffff;
576 break;
577 case FMA_CSEL4:
578 case FMA_SHIFT:
579 opCmp = op & ~0xfff;
580 break;
581 case FMA_FMA_MSCALE:
582 opCmp = op & ~0x7fff;
583 break;
584 default:
585 opCmp = ~0;
586 break;
587 }
588 if (FMAOpInfos[i].op == opCmp)
589 return FMAOpInfos[i];
590 }
591
592 struct fma_op_info info;
593 snprintf(info.name, sizeof(info.name), "op%04x", op);
594 info.op = op;
595 info.src_type = FMA_THREE_SRC;
596 return info;
597 }
598
599 static void dump_fcmp(FILE *fp, unsigned op)
600 {
601 switch (op) {
602 case 0:
603 fprintf(fp, ".OEQ");
604 break;
605 case 1:
606 fprintf(fp, ".OGT");
607 break;
608 case 2:
609 fprintf(fp, ".OGE");
610 break;
611 case 3:
612 fprintf(fp, ".UNE");
613 break;
614 case 4:
615 fprintf(fp, ".OLT");
616 break;
617 case 5:
618 fprintf(fp, ".OLE");
619 break;
620 default:
621 fprintf(fp, ".unk%d", op);
622 break;
623 }
624 }
625
626 static void dump_16swizzle(FILE *fp, unsigned swiz)
627 {
628 if (swiz == 2)
629 return;
630 fprintf(fp, ".%c%c", "xy"[swiz & 1], "xy"[(swiz >> 1) & 1]);
631 }
632
633 static void dump_fma_expand_src0(FILE *fp, unsigned ctrl)
634 {
635 switch (ctrl) {
636 case 3:
637 case 4:
638 case 6:
639 fprintf(fp, ".x");
640 break;
641 case 5:
642 case 7:
643 fprintf(fp, ".y");
644 break;
645 case 0:
646 case 1:
647 case 2:
648 break;
649 default:
650 fprintf(fp, ".unk");
651 break;
652 }
653 }
654
655 static void dump_fma_expand_src1(FILE *fp, unsigned ctrl)
656 {
657 switch (ctrl) {
658 case 1:
659 case 3:
660 fprintf(fp, ".x");
661 break;
662 case 2:
663 case 4:
664 case 5:
665 fprintf(fp, ".y");
666 break;
667 case 0:
668 case 6:
669 case 7:
670 break;
671 default:
672 fprintf(fp, ".unk");
673 break;
674 }
675 }
676
677 static void dump_fma(FILE *fp, uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts, bool verbose)
678 {
679 if (verbose) {
680 fprintf(fp, "# FMA: %016" PRIx64 "\n", word);
681 }
682 struct bifrost_fma_inst FMA;
683 memcpy((char *) &FMA, (char *) &word, sizeof(struct bifrost_fma_inst));
684 struct fma_op_info info = find_fma_op_info(FMA.op, (FMA.op & 0xe0000) == 0xe0000);
685
686 fprintf(fp, "%s", info.name);
687 if (info.src_type == FMA_FADD ||
688 info.src_type == FMA_FMINMAX ||
689 info.src_type == FMA_FMA ||
690 info.src_type == FMA_FADD16 ||
691 info.src_type == FMA_FMINMAX16 ||
692 info.src_type == FMA_FMA16) {
693 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 12, 14)));
694 switch (info.src_type) {
695 case FMA_FADD:
696 case FMA_FMA:
697 case FMA_FADD16:
698 case FMA_FMA16:
699 fprintf(fp, "%s", bi_round_mode_name(bits(FMA.op, 10, 12)));
700 break;
701 case FMA_FMINMAX:
702 case FMA_FMINMAX16:
703 fprintf(fp, "%s", bi_minmax_mode_name(bits(FMA.op, 10, 12)));
704 break;
705 default:
706 assert(0);
707 }
708 } else if (info.src_type == FMA_FCMP || info.src_type == FMA_FCMP16) {
709 dump_fcmp(fp, bits(FMA.op, 10, 13));
710 if (info.src_type == FMA_FCMP)
711 fprintf(fp, ".f32");
712 else
713 fprintf(fp, ".v2f16");
714 } else if (info.src_type == FMA_FMA_MSCALE) {
715 if (FMA.op & (1 << 11)) {
716 switch ((FMA.op >> 9) & 0x3) {
717 case 0:
718 /* This mode seems to do a few things:
719 * - Makes 0 * infinity (and incidentally 0 * nan) return 0,
720 * since generating a nan would poison the result of
721 * 1/infinity and 1/0.
722 * - Fiddles with which nan is returned in nan * nan,
723 * presumably to make sure that the same exact nan is
724 * returned for 1/nan.
725 */
726 fprintf(fp, ".rcp_mode");
727 break;
728 case 3:
729 /* Similar to the above, but src0 always wins when multiplying
730 * 0 by infinity.
731 */
732 fprintf(fp, ".sqrt_mode");
733 break;
734 default:
735 fprintf(fp, ".unk%d_mode", (int) (FMA.op >> 9) & 0x3);
736 }
737 } else {
738 fprintf(fp, "%s", bi_output_mod_name(bits(FMA.op, 9, 11)));
739 }
740 } else if (info.src_type == FMA_SHIFT) {
741 struct bifrost_shift_fma shift;
742 memcpy(&shift, &FMA, sizeof(shift));
743
744 if (shift.half == 0x7)
745 fprintf(fp, ".v2i16");
746 else if (shift.half == 0)
747 fprintf(fp, ".i32");
748 else if (shift.half == 0x4)
749 fprintf(fp, ".v4i8");
750 else
751 fprintf(fp, ".unk%u", shift.half);
752
753 if (!shift.unk)
754 fprintf(fp, ".no_unk");
755
756 if (shift.invert_1)
757 fprintf(fp, ".invert_1");
758
759 if (shift.invert_2)
760 fprintf(fp, ".invert_2");
761 }
762
763 fprintf(fp, " ");
764
765 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
766 if (next_ctrl.fma_write_unit != REG_WRITE_NONE) {
767 fprintf(fp, "{R%d, T0}, ", GetRegToWrite(next_ctrl.fma_write_unit, next_regs));
768 } else {
769 fprintf(fp, "T0, ");
770 }
771
772 switch (info.src_type) {
773 case FMA_ONE_SRC:
774 dump_src(fp, FMA.src0, regs, consts, true);
775 break;
776 case FMA_TWO_SRC:
777 dump_src(fp, FMA.src0, regs, consts, true);
778 fprintf(fp, ", ");
779 dump_src(fp, FMA.op & 0x7, regs, consts, true);
780 break;
781 case FMA_FADD:
782 case FMA_FMINMAX:
783 if (FMA.op & 0x10)
784 fprintf(fp, "-");
785 if (FMA.op & 0x200)
786 fprintf(fp, "abs(");
787 dump_src(fp, FMA.src0, regs, consts, true);
788 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
789 if (FMA.op & 0x200)
790 fprintf(fp, ")");
791 fprintf(fp, ", ");
792 if (FMA.op & 0x20)
793 fprintf(fp, "-");
794 if (FMA.op & 0x8)
795 fprintf(fp, "abs(");
796 dump_src(fp, FMA.op & 0x7, regs, consts, true);
797 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
798 if (FMA.op & 0x8)
799 fprintf(fp, ")");
800 break;
801 case FMA_FADD16:
802 case FMA_FMINMAX16: {
803 bool abs1 = FMA.op & 0x8;
804 bool abs2 = (FMA.op & 0x7) < FMA.src0;
805 if (FMA.op & 0x10)
806 fprintf(fp, "-");
807 if (abs1 || abs2)
808 fprintf(fp, "abs(");
809 dump_src(fp, FMA.src0, regs, consts, true);
810 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
811 if (abs1 || abs2)
812 fprintf(fp, ")");
813 fprintf(fp, ", ");
814 if (FMA.op & 0x20)
815 fprintf(fp, "-");
816 if (abs1 && abs2)
817 fprintf(fp, "abs(");
818 dump_src(fp, FMA.op & 0x7, regs, consts, true);
819 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
820 if (abs1 && abs2)
821 fprintf(fp, ")");
822 break;
823 }
824 case FMA_FCMP:
825 if (FMA.op & 0x200)
826 fprintf(fp, "abs(");
827 dump_src(fp, FMA.src0, regs, consts, true);
828 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
829 if (FMA.op & 0x200)
830 fprintf(fp, ")");
831 fprintf(fp, ", ");
832 if (FMA.op & 0x20)
833 fprintf(fp, "-");
834 if (FMA.op & 0x8)
835 fprintf(fp, "abs(");
836 dump_src(fp, FMA.op & 0x7, regs, consts, true);
837 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
838 if (FMA.op & 0x8)
839 fprintf(fp, ")");
840 break;
841 case FMA_FCMP16:
842 dump_src(fp, FMA.src0, regs, consts, true);
843 // Note: this is kinda a guess, I haven't seen the blob set this to
844 // anything other than the identity, but it matches FMA_TWO_SRCFmod16
845 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
846 fprintf(fp, ", ");
847 dump_src(fp, FMA.op & 0x7, regs, consts, true);
848 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
849 break;
850 case FMA_SHIFT_ADD64:
851 dump_src(fp, FMA.src0, regs, consts, true);
852 fprintf(fp, ", ");
853 dump_src(fp, FMA.op & 0x7, regs, consts, true);
854 fprintf(fp, ", ");
855 fprintf(fp, "shift:%u", (FMA.op >> 3) & 0x7);
856 break;
857 case FMA_THREE_SRC:
858 dump_src(fp, FMA.src0, regs, consts, true);
859 fprintf(fp, ", ");
860 dump_src(fp, FMA.op & 0x7, regs, consts, true);
861 fprintf(fp, ", ");
862 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
863 break;
864 case FMA_SHIFT: {
865 struct bifrost_shift_fma shift;
866 memcpy(&shift, &FMA, sizeof(shift));
867
868 dump_src(fp, shift.src0, regs, consts, true);
869 fprintf(fp, ", ");
870 dump_src(fp, shift.src1, regs, consts, true);
871 fprintf(fp, ", ");
872 dump_src(fp, shift.src2, regs, consts, true);
873 break;
874 }
875 case FMA_FMA:
876 if (FMA.op & (1 << 14))
877 fprintf(fp, "-");
878 if (FMA.op & (1 << 9))
879 fprintf(fp, "abs(");
880 dump_src(fp, FMA.src0, regs, consts, true);
881 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
882 if (FMA.op & (1 << 9))
883 fprintf(fp, ")");
884 fprintf(fp, ", ");
885 if (FMA.op & (1 << 16))
886 fprintf(fp, "abs(");
887 dump_src(fp, FMA.op & 0x7, regs, consts, true);
888 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
889 if (FMA.op & (1 << 16))
890 fprintf(fp, ")");
891 fprintf(fp, ", ");
892 if (FMA.op & (1 << 15))
893 fprintf(fp, "-");
894 if (FMA.op & (1 << 17))
895 fprintf(fp, "abs(");
896 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
897 if (FMA.op & (1 << 17))
898 fprintf(fp, ")");
899 break;
900 case FMA_FMA16:
901 if (FMA.op & (1 << 14))
902 fprintf(fp, "-");
903 dump_src(fp, FMA.src0, regs, consts, true);
904 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
905 fprintf(fp, ", ");
906 dump_src(fp, FMA.op & 0x7, regs, consts, true);
907 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
908 fprintf(fp, ", ");
909 if (FMA.op & (1 << 15))
910 fprintf(fp, "-");
911 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
912 dump_16swizzle(fp, (FMA.op >> 16) & 0x3);
913 break;
914 case FMA_CSEL4: {
915 struct bifrost_csel4 csel;
916 memcpy(&csel, &FMA, sizeof(csel));
917 fprintf(fp, ".%s ", bi_csel_cond_name(csel.cond));
918
919 dump_src(fp, csel.src0, regs, consts, true);
920 fprintf(fp, ", ");
921 dump_src(fp, csel.src1, regs, consts, true);
922 fprintf(fp, ", ");
923 dump_src(fp, csel.src2, regs, consts, true);
924 fprintf(fp, ", ");
925 dump_src(fp, csel.src3, regs, consts, true);
926 break;
927 }
928 case FMA_FMA_MSCALE:
929 if (FMA.op & (1 << 12))
930 fprintf(fp, "abs(");
931 dump_src(fp, FMA.src0, regs, consts, true);
932 if (FMA.op & (1 << 12))
933 fprintf(fp, ")");
934 fprintf(fp, ", ");
935 if (FMA.op & (1 << 13))
936 fprintf(fp, "-");
937 dump_src(fp, FMA.op & 0x7, regs, consts, true);
938 fprintf(fp, ", ");
939 if (FMA.op & (1 << 14))
940 fprintf(fp, "-");
941 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
942 fprintf(fp, ", ");
943 dump_src(fp, (FMA.op >> 6) & 0x7, regs, consts, true);
944 break;
945 }
946 fprintf(fp, "\n");
947 }
948
949 static const struct add_op_info add_op_infos[] = {
950 { 0x00000, "MAX.f32", ADD_FMINMAX },
951 { 0x02000, "MIN.f32", ADD_FMINMAX },
952 { 0x04000, "ADD.f32", ADD_FADD },
953 { 0x06000, "FCMP.GL", ADD_FCMP },
954 { 0x07000, "FCMP.D3D", ADD_FCMP },
955 { 0x07856, "F16_TO_I16", ADD_ONE_SRC },
956 { 0x07857, "F16_TO_U16", ADD_ONE_SRC },
957 { 0x078c0, "I16_TO_F16.XX", ADD_ONE_SRC },
958 { 0x078c1, "U16_TO_F16.XX", ADD_ONE_SRC },
959 { 0x078c8, "I16_TO_F16.YX", ADD_ONE_SRC },
960 { 0x078c9, "U16_TO_F16.YX", ADD_ONE_SRC },
961 { 0x078d0, "I16_TO_F16.XY", ADD_ONE_SRC },
962 { 0x078d1, "U16_TO_F16.XY", ADD_ONE_SRC },
963 { 0x078d8, "I16_TO_F16.YY", ADD_ONE_SRC },
964 { 0x078d9, "U16_TO_F16.YY", ADD_ONE_SRC },
965 { 0x07936, "F32_TO_I32", ADD_ONE_SRC },
966 { 0x07937, "F32_TO_U32", ADD_ONE_SRC },
967 { 0x07978, "I32_TO_F32", ADD_ONE_SRC },
968 { 0x07979, "U32_TO_F32", ADD_ONE_SRC },
969 { 0x07998, "I16_TO_I32.X", ADD_ONE_SRC },
970 { 0x07999, "U16_TO_U32.X", ADD_ONE_SRC },
971 { 0x0799a, "I16_TO_I32.Y", ADD_ONE_SRC },
972 { 0x0799b, "U16_TO_U32.Y", ADD_ONE_SRC },
973 { 0x0799c, "I16_TO_F32.X", ADD_ONE_SRC },
974 { 0x0799d, "U16_TO_F32.X", ADD_ONE_SRC },
975 { 0x0799e, "I16_TO_F32.Y", ADD_ONE_SRC },
976 { 0x0799f, "U16_TO_F32.Y", ADD_ONE_SRC },
977 { 0x079a2, "F16_TO_F32.X", ADD_ONE_SRC },
978 { 0x079a3, "F16_TO_F32.Y", ADD_ONE_SRC },
979 { 0x07b2b, "SWZ.YX.v2i16", ADD_ONE_SRC },
980 { 0x07b2c, "NOP", ADD_ONE_SRC },
981 { 0x07b29, "SWZ.XX.v2i16", ADD_ONE_SRC },
982 { 0x07b2d, "MOV", ADD_ONE_SRC },
983 { 0x07b2f, "SWZ.YY.v2i16", ADD_ONE_SRC },
984 { 0x07b65, "FRCP_FREXPM", ADD_ONE_SRC },
985 { 0x07b75, "FSQRT_FREXPM", ADD_ONE_SRC },
986 { 0x07b8d, "FRCP_FREXPE", ADD_ONE_SRC },
987 { 0x07ba5, "FSQRT_FREXPE", ADD_ONE_SRC },
988 { 0x07bad, "FRSQ_FREXPE", ADD_ONE_SRC },
989 { 0x07bc5, "FLOG_FREXPE", ADD_ONE_SRC },
990 { 0x07d45, "CEIL", ADD_ONE_SRC },
991 { 0x07d85, "FLOOR", ADD_ONE_SRC },
992 { 0x07dc5, "TRUNC", ADD_ONE_SRC },
993 { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC },
994 { 0x08000, "LD_ATTR", ADD_LOAD_ATTR, true },
995 { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP, true },
996 { 0x0b000, "TEX", ADD_TEX_COMPACT, true },
997 { 0x0c188, "LOAD.i32", ADD_TWO_SRC, true },
998 { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC, true },
999 { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1000 { 0x0c1c8, "LOAD.v2i32", ADD_TWO_SRC, true },
1001 { 0x0c1e0, "LD_UBO.v2i32", ADD_TWO_SRC, true },
1002 { 0x0c1f8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1003 { 0x0c208, "LOAD.v4i32", ADD_TWO_SRC, true },
1004 { 0x0c220, "LD_UBO.v4i32", ADD_TWO_SRC, true },
1005 { 0x0c238, "LD_SCRATCH.v4i32", ADD_TWO_SRC, true },
1006 { 0x0c248, "STORE.v4i32", ADD_TWO_SRC, true },
1007 { 0x0c278, "ST_SCRATCH.v4i32", ADD_TWO_SRC, true },
1008 { 0x0c588, "STORE.i32", ADD_TWO_SRC, true },
1009 { 0x0c5b8, "ST_SCRATCH.i32", ADD_TWO_SRC, true },
1010 { 0x0c5c8, "STORE.v2i32", ADD_TWO_SRC, true },
1011 { 0x0c5f8, "ST_SCRATCH.v2i32", ADD_TWO_SRC, true },
1012 { 0x0c648, "LOAD.u16", ADD_TWO_SRC, true }, // zero-extends
1013 { 0x0ca88, "LOAD.v3i32", ADD_TWO_SRC, true },
1014 { 0x0caa0, "LD_UBO.v3i32", ADD_TWO_SRC, true },
1015 { 0x0cab8, "LD_SCRATCH.v3i32", ADD_TWO_SRC, true },
1016 { 0x0cb88, "STORE.v3i32", ADD_TWO_SRC, true },
1017 { 0x0cbb8, "ST_SCRATCH.v3i32", ADD_TWO_SRC, true },
1018 { 0x0cc00, "FRCP_FAST.f32", ADD_ONE_SRC },
1019 { 0x0cc20, "FRSQ_FAST.f32", ADD_ONE_SRC },
1020 { 0x0ce00, "FRCP_TABLE", ADD_ONE_SRC },
1021 { 0x0ce10, "FRCP_FAST.f16.X", ADD_ONE_SRC },
1022 { 0x0ce20, "FRSQ_TABLE", ADD_ONE_SRC },
1023 { 0x0ce30, "FRCP_FAST.f16.Y", ADD_ONE_SRC },
1024 { 0x0ce50, "FRSQ_FAST.f16.X", ADD_ONE_SRC },
1025 { 0x0ce60, "FRCP_APPROX", ADD_ONE_SRC },
1026 { 0x0ce70, "FRSQ_FAST.f16.Y", ADD_ONE_SRC },
1027 { 0x0cf40, "ATAN_ASSIST", ADD_TWO_SRC },
1028 { 0x0cf48, "ATAN_TABLE", ADD_TWO_SRC },
1029 { 0x0cf50, "SIN_TABLE", ADD_ONE_SRC },
1030 { 0x0cf51, "COS_TABLE", ADD_ONE_SRC },
1031 { 0x0cf58, "EXP_TABLE", ADD_ONE_SRC },
1032 { 0x0cf60, "FLOG2_TABLE", ADD_ONE_SRC },
1033 { 0x0cf64, "FLOGE_TABLE", ADD_ONE_SRC },
1034 { 0x0d000, "BRANCH", ADD_BRANCH },
1035 { 0x0e8c0, "MUX", ADD_THREE_SRC },
1036 { 0x0e9b0, "ATAN_LDEXP.Y.f32", ADD_TWO_SRC },
1037 { 0x0e9b8, "ATAN_LDEXP.X.f32", ADD_TWO_SRC },
1038 { 0x0ea60, "SEL.XX.i16", ADD_TWO_SRC },
1039 { 0x0ea70, "SEL.XY.i16", ADD_TWO_SRC },
1040 { 0x0ea68, "SEL.YX.i16", ADD_TWO_SRC },
1041 { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC },
1042 { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC },
1043 { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC }, // src0 > src1 ? 1 : 0
1044 { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC },
1045 { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC },
1046 { 0x0f658, "UCMP.GL.GE", ADD_TWO_SRC },
1047 { 0x0f660, "ICMP.GL.EQ", ADD_TWO_SRC },
1048 { 0x0f669, "ICMP.GL.NEQ", ADD_TWO_SRC },
1049 { 0x0f6c0, "ICMP.D3D.GT", ADD_TWO_SRC }, // src0 > src1 ? ~0 : 0
1050 { 0x0f6c8, "ICMP.D3D.GE", ADD_TWO_SRC },
1051 { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC },
1052 { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC },
1053 { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC },
1054 { 0x10000, "MAX.v2f16", ADD_FMINMAX16 },
1055 { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale },
1056 { 0x12000, "MIN.v2f16", ADD_FMINMAX16 },
1057 { 0x14000, "ADD.v2f16", ADD_FADD16 },
1058 { 0x17000, "FCMP.D3D", ADD_FCMP16 },
1059 { 0x178c0, "ADD.i32", ADD_TWO_SRC },
1060 { 0x17900, "ADD.v2i16", ADD_TWO_SRC },
1061 { 0x17ac0, "SUB.i32", ADD_TWO_SRC },
1062 { 0x17c10, "ADDC.i32", ADD_TWO_SRC }, // adds src0 to the bottom bit of src1
1063 { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC },
1064 { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC },
1065 { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC },
1066 { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC },
1067 { 0x18000, "LD_VAR_ADDR", ADD_VARYING_ADDRESS, true },
1068 { 0x19181, "DISCARD.FEQ.f32", ADD_TWO_SRC, true },
1069 { 0x19189, "DISCARD.FNE.f32", ADD_TWO_SRC, true },
1070 { 0x1918C, "DISCARD.GL.f32", ADD_TWO_SRC, true }, /* Consumes ICMP.GL/etc with fixed 0 argument */
1071 { 0x19190, "DISCARD.FLE.f32", ADD_TWO_SRC, true },
1072 { 0x19198, "DISCARD.FLT.f32", ADD_TWO_SRC, true },
1073 { 0x191e8, "ATEST.f32", ADD_TWO_SRC, true },
1074 { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC, true },
1075 { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC, true },
1076 { 0x19300, "ST_VAR.v1", ADD_THREE_SRC, true },
1077 { 0x19340, "ST_VAR.v2", ADD_THREE_SRC, true },
1078 { 0x19380, "ST_VAR.v3", ADD_THREE_SRC, true },
1079 { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC, true },
1080 { 0x1952c, "BLEND", ADD_BLENDING, true },
1081 { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP, true },
1082 { 0x1ae60, "TEX", ADD_TEX, true },
1083 { 0x1c000, "RSHIFT_NAND.i32", ADD_SHIFT },
1084 { 0x1c400, "RSHIFT_AND.i32", ADD_SHIFT },
1085 { 0x1c800, "LSHIFT_NAND.i32", ADD_SHIFT },
1086 { 0x1cc00, "LSHIFT_AND.i32", ADD_SHIFT },
1087 { 0x1d000, "RSHIFT_XOR.i32", ADD_SHIFT },
1088 { 0x1d400, "LSHIFT_ADD.i32", ADD_SHIFT },
1089 { 0x1d800, "RSHIFT_SUB.i32", ADD_SHIFT },
1090 { 0x1dd18, "OR.i32", ADD_TWO_SRC },
1091 { 0x1dd20, "AND.i32", ADD_TWO_SRC },
1092 { 0x1dd60, "LSHIFT.i32", ADD_TWO_SRC },
1093 { 0x1dd50, "XOR.i32", ADD_TWO_SRC },
1094 { 0x1dd80, "RSHIFT.i32", ADD_TWO_SRC },
1095 { 0x1dda0, "ARSHIFT.i32", ADD_TWO_SRC },
1096 };
1097
1098 static struct add_op_info find_add_op_info(unsigned op)
1099 {
1100 for (unsigned i = 0; i < ARRAY_SIZE(add_op_infos); i++) {
1101 unsigned opCmp = ~0;
1102 switch (add_op_infos[i].src_type) {
1103 case ADD_ONE_SRC:
1104 case ADD_BLENDING:
1105 opCmp = op;
1106 break;
1107 case ADD_TWO_SRC:
1108 opCmp = op & ~0x7;
1109 break;
1110 case ADD_THREE_SRC:
1111 opCmp = op & ~0x3f;
1112 break;
1113 case ADD_SHIFT:
1114 opCmp = op & ~0x3ff;
1115 break;
1116 case ADD_TEX:
1117 opCmp = op & ~0xf;
1118 break;
1119 case ADD_FADD:
1120 case ADD_FMINMAX:
1121 case ADD_FADD16:
1122 opCmp = op & ~0x1fff;
1123 break;
1124 case ADD_FMINMAX16:
1125 case ADD_FADDMscale:
1126 opCmp = op & ~0xfff;
1127 break;
1128 case ADD_FCMP:
1129 case ADD_FCMP16:
1130 opCmp = op & ~0x7ff;
1131 break;
1132 case ADD_TEX_COMPACT:
1133 opCmp = op & ~0x3ff;
1134 break;
1135 case ADD_VARYING_INTERP:
1136 opCmp = op & ~0x7ff;
1137 break;
1138 case ADD_VARYING_ADDRESS:
1139 opCmp = op & ~0xfff;
1140 break;
1141 case ADD_LOAD_ATTR:
1142 case ADD_BRANCH:
1143 opCmp = op & ~0xfff;
1144 break;
1145 default:
1146 opCmp = ~0;
1147 break;
1148 }
1149 if (add_op_infos[i].op == opCmp)
1150 return add_op_infos[i];
1151 }
1152
1153 struct add_op_info info;
1154 snprintf(info.name, sizeof(info.name), "op%04x", op);
1155 info.op = op;
1156 info.src_type = ADD_TWO_SRC;
1157 info.has_data_reg = true;
1158 return info;
1159 }
1160
1161 static void dump_add(FILE *fp, uint64_t word, struct bifrost_regs regs,
1162 struct bifrost_regs next_regs, uint64_t *consts,
1163 unsigned data_reg, unsigned offset, bool verbose)
1164 {
1165 if (verbose) {
1166 fprintf(fp, "# ADD: %016" PRIx64 "\n", word);
1167 }
1168 struct bifrost_add_inst ADD;
1169 memcpy((char *) &ADD, (char *) &word, sizeof(ADD));
1170 struct add_op_info info = find_add_op_info(ADD.op);
1171
1172 fprintf(fp, "%s", info.name);
1173
1174 // float16 seems like it doesn't support output modifiers
1175 if (info.src_type == ADD_FADD || info.src_type == ADD_FMINMAX) {
1176 // output modifiers
1177 fprintf(fp, "%s", bi_output_mod_name(bits(ADD.op, 8, 10)));
1178 if (info.src_type == ADD_FADD)
1179 fprintf(fp, "%s", bi_round_mode_name(bits(ADD.op, 10, 12)));
1180 else
1181 fprintf(fp, "%s", bi_minmax_mode_name(bits(ADD.op, 10, 12)));
1182 } else if (info.src_type == ADD_FCMP || info.src_type == ADD_FCMP16) {
1183 dump_fcmp(fp, bits(ADD.op, 3, 6));
1184 if (info.src_type == ADD_FCMP)
1185 fprintf(fp, ".f32");
1186 else
1187 fprintf(fp, ".v2f16");
1188 } else if (info.src_type == ADD_FADDMscale) {
1189 switch ((ADD.op >> 6) & 0x7) {
1190 case 0:
1191 break;
1192 // causes GPU hangs on G71
1193 case 1:
1194 fprintf(fp, ".invalid");
1195 break;
1196 // Same as usual outmod value.
1197 case 2:
1198 fprintf(fp, ".clamp_0_1");
1199 break;
1200 // If src0 is infinite or NaN, flush it to zero so that the other
1201 // source is passed through unmodified.
1202 case 3:
1203 fprintf(fp, ".flush_src0_inf_nan");
1204 break;
1205 // Vice versa.
1206 case 4:
1207 fprintf(fp, ".flush_src1_inf_nan");
1208 break;
1209 // Every other case seems to behave the same as the above?
1210 default:
1211 fprintf(fp, ".unk%d", (ADD.op >> 6) & 0x7);
1212 break;
1213 }
1214 } else if (info.src_type == ADD_VARYING_INTERP) {
1215 if (ADD.op & 0x200)
1216 fprintf(fp, ".reuse");
1217 if (ADD.op & 0x400)
1218 fprintf(fp, ".flat");
1219 switch ((ADD.op >> 7) & 0x3) {
1220 case BIFROST_INTERP_PER_FRAG:
1221 fprintf(fp, ".per_frag");
1222 break;
1223 case BIFROST_INTERP_CENTROID:
1224 fprintf(fp, ".centroid");
1225 break;
1226 case BIFROST_INTERP_DEFAULT:
1227 break;
1228 case BIFROST_INTERP_EXPLICIT:
1229 fprintf(fp, ".explicit");
1230 break;
1231 }
1232 fprintf(fp, ".v%d", ((ADD.op >> 5) & 0x3) + 1);
1233 } else if (info.src_type == ADD_BRANCH) {
1234 enum bifrost_branch_code branchCode = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1235 if (branchCode == BR_ALWAYS) {
1236 // unconditional branch
1237 } else {
1238 enum bifrost_branch_cond cond = (enum bifrost_branch_cond) ((ADD.op >> 6) & 0x7);
1239 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1240 bool portSwapped = (ADD.op & 0x7) < ADD.src0;
1241 // See the comment in branch_bit_size
1242 if (size == BR_SIZE_16YX0)
1243 portSwapped = true;
1244 if (size == BR_SIZE_16YX1)
1245 portSwapped = false;
1246 // These sizes are only for floating point comparisons, so the
1247 // non-floating-point comparisons are reused to encode the flipped
1248 // versions.
1249 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y)
1250 portSwapped = false;
1251 // There's only one argument, so we reuse the extra argument to
1252 // encode this.
1253 if (size == BR_SIZE_ZERO)
1254 portSwapped = !(ADD.op & 1);
1255
1256 switch (cond) {
1257 case BR_COND_LT:
1258 if (portSwapped)
1259 fprintf(fp, ".LT.u");
1260 else
1261 fprintf(fp, ".LT.i");
1262 break;
1263 case BR_COND_LE:
1264 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y) {
1265 fprintf(fp, ".UNE.f");
1266 } else {
1267 if (portSwapped)
1268 fprintf(fp, ".LE.u");
1269 else
1270 fprintf(fp, ".LE.i");
1271 }
1272 break;
1273 case BR_COND_GT:
1274 if (portSwapped)
1275 fprintf(fp, ".GT.u");
1276 else
1277 fprintf(fp, ".GT.i");
1278 break;
1279 case BR_COND_GE:
1280 if (portSwapped)
1281 fprintf(fp, ".GE.u");
1282 else
1283 fprintf(fp, ".GE.i");
1284 break;
1285 case BR_COND_EQ:
1286 if (portSwapped)
1287 fprintf(fp, ".NE.i");
1288 else
1289 fprintf(fp, ".EQ.i");
1290 break;
1291 case BR_COND_OEQ:
1292 if (portSwapped)
1293 fprintf(fp, ".UNE.f");
1294 else
1295 fprintf(fp, ".OEQ.f");
1296 break;
1297 case BR_COND_OGT:
1298 if (portSwapped)
1299 fprintf(fp, ".OGT.unk.f");
1300 else
1301 fprintf(fp, ".OGT.f");
1302 break;
1303 case BR_COND_OLT:
1304 if (portSwapped)
1305 fprintf(fp, ".OLT.unk.f");
1306 else
1307 fprintf(fp, ".OLT.f");
1308 break;
1309 }
1310 switch (size) {
1311 case BR_SIZE_32:
1312 case BR_SIZE_32_AND_16X:
1313 case BR_SIZE_32_AND_16Y:
1314 fprintf(fp, "32");
1315 break;
1316 case BR_SIZE_16XX:
1317 case BR_SIZE_16YY:
1318 case BR_SIZE_16YX0:
1319 case BR_SIZE_16YX1:
1320 fprintf(fp, "16");
1321 break;
1322 case BR_SIZE_ZERO: {
1323 unsigned ctrl = (ADD.op >> 1) & 0x3;
1324 if (ctrl == 0)
1325 fprintf(fp, "32.Z");
1326 else
1327 fprintf(fp, "16.Z");
1328 break;
1329 }
1330 }
1331 }
1332 } else if (info.src_type == ADD_SHIFT) {
1333 struct bifrost_shift_add shift;
1334 memcpy(&shift, &ADD, sizeof(ADD));
1335
1336 if (shift.invert_1)
1337 fprintf(fp, ".invert_1");
1338
1339 if (shift.invert_2)
1340 fprintf(fp, ".invert_2");
1341
1342 if (shift.zero)
1343 fprintf(fp, ".unk%u", shift.zero);
1344 } else if (info.src_type == ADD_VARYING_ADDRESS) {
1345 struct bifrost_ld_var_addr ld;
1346 memcpy(&ld, &ADD, sizeof(ADD));
1347 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1348 } else if (info.src_type == ADD_LOAD_ATTR) {
1349 struct bifrost_ld_attr ld;
1350 memcpy(&ld, &ADD, sizeof(ADD));
1351
1352 if (ld.channels)
1353 fprintf(fp, ".v%d%s", ld.channels + 1, bi_ldst_type_name(ld.type));
1354 else
1355 fprintf(fp, ".%s", bi_ldst_type_name(ld.type));
1356 }
1357
1358 fprintf(fp, " ");
1359
1360 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
1361 if (next_ctrl.add_write_unit != REG_WRITE_NONE) {
1362 fprintf(fp, "{R%d, T1}, ", GetRegToWrite(next_ctrl.add_write_unit, next_regs));
1363 } else {
1364 fprintf(fp, "T1, ");
1365 }
1366
1367 switch (info.src_type) {
1368 case ADD_BLENDING:
1369 // Note: in this case, regs.uniform_const == location | 0x8
1370 // This probably means we can't load uniforms or immediates in the
1371 // same instruction. This re-uses the encoding that normally means
1372 // "disabled", where the low 4 bits are ignored. Perhaps the extra
1373 // 0x8 or'd in indicates this is happening.
1374 fprintf(fp, "location:%d, ", regs.uniform_const & 0x7);
1375 // fallthrough
1376 case ADD_ONE_SRC:
1377 dump_src(fp, ADD.src0, regs, consts, false);
1378 break;
1379 case ADD_TEX:
1380 case ADD_TEX_COMPACT: {
1381 int tex_index;
1382 int sampler_index;
1383 bool dualTex = false;
1384 if (info.src_type == ADD_TEX_COMPACT) {
1385 tex_index = (ADD.op >> 3) & 0x7;
1386 sampler_index = (ADD.op >> 7) & 0x7;
1387 bool unknown = (ADD.op & 0x40);
1388 // TODO: figure out if the unknown bit is ever 0
1389 if (!unknown)
1390 fprintf(fp, "unknown ");
1391 } else {
1392 uint64_t constVal = get_const(consts, regs);
1393 uint32_t controlBits = (ADD.op & 0x8) ? (constVal >> 32) : constVal;
1394 struct bifrost_tex_ctrl ctrl;
1395 memcpy((char *) &ctrl, (char *) &controlBits, sizeof(ctrl));
1396
1397 // TODO: figure out what actually triggers dual-tex
1398 if (ctrl.result_type == 9) {
1399 struct bifrost_dual_tex_ctrl dualCtrl;
1400 memcpy((char *) &dualCtrl, (char *) &controlBits, sizeof(ctrl));
1401 fprintf(fp, "(dualtex) tex0:%d samp0:%d tex1:%d samp1:%d ",
1402 dualCtrl.tex_index0, dualCtrl.sampler_index0,
1403 dualCtrl.tex_index1, dualCtrl.sampler_index1);
1404 if (dualCtrl.unk0 != 3)
1405 fprintf(fp, "unk:%d ", dualCtrl.unk0);
1406 dualTex = true;
1407 } else {
1408 if (ctrl.no_merge_index) {
1409 tex_index = ctrl.tex_index;
1410 sampler_index = ctrl.sampler_index;
1411 } else {
1412 tex_index = sampler_index = ctrl.tex_index;
1413 unsigned unk = ctrl.sampler_index >> 2;
1414 if (unk != 3)
1415 fprintf(fp, "unk:%d ", unk);
1416 if (ctrl.sampler_index & 1)
1417 tex_index = -1;
1418 if (ctrl.sampler_index & 2)
1419 sampler_index = -1;
1420 }
1421
1422 if (ctrl.unk0 != 3)
1423 fprintf(fp, "unk0:%d ", ctrl.unk0);
1424 if (ctrl.unk1)
1425 fprintf(fp, "unk1 ");
1426 if (ctrl.unk2 != 0xf)
1427 fprintf(fp, "unk2:%x ", ctrl.unk2);
1428
1429 switch (ctrl.result_type) {
1430 case 0x4:
1431 fprintf(fp, "f32 ");
1432 break;
1433 case 0xe:
1434 fprintf(fp, "i32 ");
1435 break;
1436 case 0xf:
1437 fprintf(fp, "u32 ");
1438 break;
1439 default:
1440 fprintf(fp, "unktype(%x) ", ctrl.result_type);
1441 }
1442
1443 switch (ctrl.tex_type) {
1444 case 0:
1445 fprintf(fp, "cube ");
1446 break;
1447 case 1:
1448 fprintf(fp, "buffer ");
1449 break;
1450 case 2:
1451 fprintf(fp, "2D ");
1452 break;
1453 case 3:
1454 fprintf(fp, "3D ");
1455 break;
1456 }
1457
1458 if (ctrl.is_shadow)
1459 fprintf(fp, "shadow ");
1460 if (ctrl.is_array)
1461 fprintf(fp, "array ");
1462
1463 if (!ctrl.filter) {
1464 if (ctrl.calc_gradients) {
1465 int comp = (controlBits >> 20) & 0x3;
1466 fprintf(fp, "txg comp:%d ", comp);
1467 } else {
1468 fprintf(fp, "txf ");
1469 }
1470 } else {
1471 if (!ctrl.not_supply_lod) {
1472 if (ctrl.compute_lod)
1473 fprintf(fp, "lod_bias ");
1474 else
1475 fprintf(fp, "lod ");
1476 }
1477
1478 if (!ctrl.calc_gradients)
1479 fprintf(fp, "grad ");
1480 }
1481
1482 if (ctrl.texel_offset)
1483 fprintf(fp, "offset ");
1484 }
1485 }
1486
1487 if (!dualTex) {
1488 if (tex_index == -1)
1489 fprintf(fp, "tex:indirect ");
1490 else
1491 fprintf(fp, "tex:%d ", tex_index);
1492
1493 if (sampler_index == -1)
1494 fprintf(fp, "samp:indirect ");
1495 else
1496 fprintf(fp, "samp:%d ", sampler_index);
1497 }
1498 break;
1499 }
1500 case ADD_VARYING_INTERP: {
1501 unsigned addr = ADD.op & 0x1f;
1502 if (addr < 0b10100) {
1503 // direct addr
1504 fprintf(fp, "%d", addr);
1505 } else if (addr < 0b11000) {
1506 if (addr == 22)
1507 fprintf(fp, "fragw");
1508 else if (addr == 23)
1509 fprintf(fp, "fragz");
1510 else
1511 fprintf(fp, "unk%d", addr);
1512 } else {
1513 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1514 }
1515 fprintf(fp, ", ");
1516 dump_src(fp, ADD.src0, regs, consts, false);
1517 break;
1518 }
1519 case ADD_VARYING_ADDRESS: {
1520 dump_src(fp, ADD.src0, regs, consts, false);
1521 fprintf(fp, ", ");
1522 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1523 fprintf(fp, ", ");
1524 unsigned location = (ADD.op >> 3) & 0x1f;
1525 if (location < 16) {
1526 fprintf(fp, "location:%d", location);
1527 } else if (location == 20) {
1528 fprintf(fp, "location:%u", (uint32_t) get_const(consts, regs));
1529 } else if (location == 21) {
1530 fprintf(fp, "location:%u", (uint32_t) (get_const(consts, regs) >> 32));
1531 } else {
1532 fprintf(fp, "location:%d(unk)", location);
1533 }
1534 break;
1535 }
1536 case ADD_LOAD_ATTR:
1537 fprintf(fp, "location:%d, ", (ADD.op >> 3) & 0x1f);
1538 case ADD_TWO_SRC:
1539 dump_src(fp, ADD.src0, regs, consts, false);
1540 fprintf(fp, ", ");
1541 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1542 break;
1543 case ADD_THREE_SRC:
1544 dump_src(fp, ADD.src0, regs, consts, false);
1545 fprintf(fp, ", ");
1546 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1547 fprintf(fp, ", ");
1548 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1549 break;
1550 case ADD_SHIFT: {
1551 struct bifrost_shift_add shift;
1552 memcpy(&shift, &ADD, sizeof(ADD));
1553 dump_src(fp, shift.src0, regs, consts, false);
1554 fprintf(fp, ", ");
1555 dump_src(fp, shift.src1, regs, consts, false);
1556 fprintf(fp, ", ");
1557 dump_src(fp, shift.src2, regs, consts, false);
1558 break;
1559 }
1560 case ADD_FADD:
1561 case ADD_FMINMAX:
1562 if (ADD.op & 0x10)
1563 fprintf(fp, "-");
1564 if (ADD.op & 0x1000)
1565 fprintf(fp, "abs(");
1566 dump_src(fp, ADD.src0, regs, consts, false);
1567 switch ((ADD.op >> 6) & 0x3) {
1568 case 3:
1569 fprintf(fp, ".x");
1570 break;
1571 default:
1572 break;
1573 }
1574 if (ADD.op & 0x1000)
1575 fprintf(fp, ")");
1576 fprintf(fp, ", ");
1577 if (ADD.op & 0x20)
1578 fprintf(fp, "-");
1579 if (ADD.op & 0x8)
1580 fprintf(fp, "abs(");
1581 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1582 switch ((ADD.op >> 6) & 0x3) {
1583 case 1:
1584 case 3:
1585 fprintf(fp, ".x");
1586 break;
1587 case 2:
1588 fprintf(fp, ".y");
1589 break;
1590 case 0:
1591 break;
1592 default:
1593 fprintf(fp, ".unk");
1594 break;
1595 }
1596 if (ADD.op & 0x8)
1597 fprintf(fp, ")");
1598 break;
1599 case ADD_FADD16:
1600 if (ADD.op & 0x10)
1601 fprintf(fp, "-");
1602 if (ADD.op & 0x1000)
1603 fprintf(fp, "abs(");
1604 dump_src(fp, ADD.src0, regs, consts, false);
1605 if (ADD.op & 0x1000)
1606 fprintf(fp, ")");
1607 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1608 fprintf(fp, ", ");
1609 if (ADD.op & 0x20)
1610 fprintf(fp, "-");
1611 if (ADD.op & 0x8)
1612 fprintf(fp, "abs(");
1613 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1614 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1615 if (ADD.op & 0x8)
1616 fprintf(fp, ")");
1617 break;
1618 case ADD_FMINMAX16: {
1619 bool abs1 = ADD.op & 0x8;
1620 bool abs2 = (ADD.op & 0x7) < ADD.src0;
1621 if (ADD.op & 0x10)
1622 fprintf(fp, "-");
1623 if (abs1 || abs2)
1624 fprintf(fp, "abs(");
1625 dump_src(fp, ADD.src0, regs, consts, false);
1626 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1627 if (abs1 || abs2)
1628 fprintf(fp, ")");
1629 fprintf(fp, ", ");
1630 if (ADD.op & 0x20)
1631 fprintf(fp, "-");
1632 if (abs1 && abs2)
1633 fprintf(fp, "abs(");
1634 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1635 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1636 if (abs1 && abs2)
1637 fprintf(fp, ")");
1638 break;
1639 }
1640 case ADD_FADDMscale: {
1641 if (ADD.op & 0x400)
1642 fprintf(fp, "-");
1643 if (ADD.op & 0x200)
1644 fprintf(fp, "abs(");
1645 dump_src(fp, ADD.src0, regs, consts, false);
1646 if (ADD.op & 0x200)
1647 fprintf(fp, ")");
1648
1649 fprintf(fp, ", ");
1650
1651 if (ADD.op & 0x800)
1652 fprintf(fp, "-");
1653 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1654
1655 fprintf(fp, ", ");
1656
1657 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1658 break;
1659 }
1660 case ADD_FCMP:
1661 if (ADD.op & 0x400) {
1662 fprintf(fp, "-");
1663 }
1664 if (ADD.op & 0x100) {
1665 fprintf(fp, "abs(");
1666 }
1667 dump_src(fp, ADD.src0, regs, consts, false);
1668 switch ((ADD.op >> 6) & 0x3) {
1669 case 3:
1670 fprintf(fp, ".x");
1671 break;
1672 default:
1673 break;
1674 }
1675 if (ADD.op & 0x100) {
1676 fprintf(fp, ")");
1677 }
1678 fprintf(fp, ", ");
1679 if (ADD.op & 0x200) {
1680 fprintf(fp, "abs(");
1681 }
1682 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1683 switch ((ADD.op >> 6) & 0x3) {
1684 case 1:
1685 case 3:
1686 fprintf(fp, ".x");
1687 break;
1688 case 2:
1689 fprintf(fp, ".y");
1690 break;
1691 case 0:
1692 break;
1693 default:
1694 fprintf(fp, ".unk");
1695 break;
1696 }
1697 if (ADD.op & 0x200) {
1698 fprintf(fp, ")");
1699 }
1700 break;
1701 case ADD_FCMP16:
1702 dump_src(fp, ADD.src0, regs, consts, false);
1703 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1704 fprintf(fp, ", ");
1705 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1706 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1707 break;
1708 case ADD_BRANCH: {
1709 enum bifrost_branch_code code = (enum bifrost_branch_code) ((ADD.op >> 6) & 0x3f);
1710 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1711 if (code != BR_ALWAYS) {
1712 dump_src(fp, ADD.src0, regs, consts, false);
1713 switch (size) {
1714 case BR_SIZE_16XX:
1715 fprintf(fp, ".x");
1716 break;
1717 case BR_SIZE_16YY:
1718 case BR_SIZE_16YX0:
1719 case BR_SIZE_16YX1:
1720 fprintf(fp, ".y");
1721 break;
1722 case BR_SIZE_ZERO: {
1723 unsigned ctrl = (ADD.op >> 1) & 0x3;
1724 switch (ctrl) {
1725 case 1:
1726 fprintf(fp, ".y");
1727 break;
1728 case 2:
1729 fprintf(fp, ".x");
1730 break;
1731 default:
1732 break;
1733 }
1734 }
1735 default:
1736 break;
1737 }
1738 fprintf(fp, ", ");
1739 }
1740 if (code != BR_ALWAYS && size != BR_SIZE_ZERO) {
1741 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1742 switch (size) {
1743 case BR_SIZE_16XX:
1744 case BR_SIZE_16YX0:
1745 case BR_SIZE_16YX1:
1746 case BR_SIZE_32_AND_16X:
1747 fprintf(fp, ".x");
1748 break;
1749 case BR_SIZE_16YY:
1750 case BR_SIZE_32_AND_16Y:
1751 fprintf(fp, ".y");
1752 break;
1753 default:
1754 break;
1755 }
1756 fprintf(fp, ", ");
1757 }
1758 // I haven't had the chance to test if this actually specifies the
1759 // branch offset, since I couldn't get it to produce values other
1760 // than 5 (uniform/const high), but these three bits are always
1761 // consistent across branch instructions, so it makes sense...
1762 int offsetSrc = (ADD.op >> 3) & 0x7;
1763 if (offsetSrc == 4 || offsetSrc == 5) {
1764 // If the offset is known/constant, we can decode it
1765 uint32_t raw_offset;
1766 if (offsetSrc == 4)
1767 raw_offset = get_const(consts, regs);
1768 else
1769 raw_offset = get_const(consts, regs) >> 32;
1770 // The high 4 bits are flags, while the rest is the
1771 // twos-complement offset in bytes (here we convert to
1772 // clauses).
1773 int32_t branch_offset = ((int32_t) raw_offset << 4) >> 8;
1774
1775 // If high4 is the high 4 bits of the last 64-bit constant,
1776 // this is calculated as (high4 + 4) & 0xf, or 0 if the branch
1777 // offset itself is the last constant. Not sure if this is
1778 // actually used, or just garbage in unused bits, but in any
1779 // case, we can just ignore it here since it's redundant. Note
1780 // that if there is any padding, this will be 4 since the
1781 // padding counts as the last constant.
1782 unsigned flags = raw_offset >> 28;
1783 (void) flags;
1784
1785 // Note: the offset is in bytes, relative to the beginning of the
1786 // current clause, so a zero offset would be a loop back to the
1787 // same clause (annoyingly different from Midgard).
1788 fprintf(fp, "clause_%d", offset + branch_offset);
1789 } else {
1790 dump_src(fp, offsetSrc, regs, consts, false);
1791 }
1792 }
1793 }
1794 if (info.has_data_reg) {
1795 fprintf(fp, ", R%d", data_reg);
1796 }
1797 fprintf(fp, "\n");
1798 }
1799
1800 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
1801 struct bifrost_regs next_regs, uint64_t *consts,
1802 unsigned data_reg, unsigned offset, bool verbose)
1803 {
1804 struct bifrost_regs regs;
1805 memcpy((char *) &regs, (char *) &instr->reg_bits, sizeof(regs));
1806
1807 if (verbose) {
1808 fprintf(fp, "# regs: %016" PRIx64 "\n", instr->reg_bits);
1809 dump_regs(fp, regs);
1810 }
1811 dump_fma(fp, instr->fma_bits, regs, next_regs, consts, verbose);
1812 dump_add(fp, instr->add_bits, regs, next_regs, consts, data_reg, offset, verbose);
1813 }
1814
1815 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose)
1816 {
1817 // State for a decoded clause
1818 struct bifrost_alu_inst instrs[8] = {};
1819 uint64_t consts[6] = {};
1820 unsigned num_instrs = 0;
1821 unsigned num_consts = 0;
1822 uint64_t header_bits = 0;
1823 bool stopbit = false;
1824
1825 unsigned i;
1826 for (i = 0; ; i++, words += 4) {
1827 if (verbose) {
1828 fprintf(fp, "# ");
1829 for (int j = 0; j < 4; j++)
1830 fprintf(fp, "%08x ", words[3 - j]); // low bit on the right
1831 fprintf(fp, "\n");
1832 }
1833 unsigned tag = bits(words[0], 0, 8);
1834
1835 // speculatively decode some things that are common between many formats, so we can share some code
1836 struct bifrost_alu_inst main_instr = {};
1837 // 20 bits
1838 main_instr.add_bits = bits(words[2], 2, 32 - 13);
1839 // 23 bits
1840 main_instr.fma_bits = bits(words[1], 11, 32) | bits(words[2], 0, 2) << (32 - 11);
1841 // 35 bits
1842 main_instr.reg_bits = ((uint64_t) bits(words[1], 0, 11)) << 24 | (uint64_t) bits(words[0], 8, 32);
1843
1844 uint64_t const0 = bits(words[0], 8, 32) << 4 | (uint64_t) words[1] << 28 | bits(words[2], 0, 4) << 60;
1845 uint64_t const1 = bits(words[2], 4, 32) << 4 | (uint64_t) words[3] << 32;
1846
1847 bool stop = tag & 0x40;
1848
1849 if (verbose) {
1850 fprintf(fp, "# tag: 0x%02x\n", tag);
1851 }
1852 if (tag & 0x80) {
1853 unsigned idx = stop ? 5 : 2;
1854 main_instr.add_bits |= ((tag >> 3) & 0x7) << 17;
1855 instrs[idx + 1] = main_instr;
1856 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17);
1857 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10;
1858 consts[0] = bits(words[3], 17, 32) << 4;
1859 } else {
1860 bool done = false;
1861 switch ((tag >> 3) & 0x7) {
1862 case 0x0:
1863 switch (tag & 0x7) {
1864 case 0x3:
1865 main_instr.add_bits |= bits(words[3], 29, 32) << 17;
1866 instrs[1] = main_instr;
1867 num_instrs = 2;
1868 done = stop;
1869 break;
1870 case 0x4:
1871 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1872 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1873 consts[0] = const0;
1874 num_instrs = 3;
1875 num_consts = 1;
1876 done = stop;
1877 break;
1878 case 0x1:
1879 case 0x5:
1880 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1881 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
1882 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1883 instrs[3] = main_instr;
1884 if ((tag & 0x7) == 0x5) {
1885 num_instrs = 4;
1886 done = stop;
1887 }
1888 break;
1889 case 0x6:
1890 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1891 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1892 consts[0] = const0;
1893 num_instrs = 6;
1894 num_consts = 1;
1895 done = stop;
1896 break;
1897 case 0x7:
1898 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
1899 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
1900 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
1901 instrs[6] = main_instr;
1902 num_instrs = 7;
1903 done = stop;
1904 break;
1905 default:
1906 fprintf(fp, "unknown tag bits 0x%02x\n", tag);
1907 }
1908 break;
1909 case 0x2:
1910 case 0x3: {
1911 unsigned idx = ((tag >> 3) & 0x7) == 2 ? 4 : 7;
1912 main_instr.add_bits |= (tag & 0x7) << 17;
1913 instrs[idx] = main_instr;
1914 consts[0] |= (bits(words[2], 19, 32) | ((uint64_t) words[3] << 13)) << 19;
1915 num_consts = 1;
1916 num_instrs = idx + 1;
1917 done = stop;
1918 break;
1919 }
1920 case 0x4: {
1921 unsigned idx = stop ? 4 : 1;
1922 main_instr.add_bits |= (tag & 0x7) << 17;
1923 instrs[idx] = main_instr;
1924 instrs[idx + 1].fma_bits |= bits(words[3], 22, 32);
1925 instrs[idx + 1].reg_bits = bits(words[2], 19, 32) | (bits(words[3], 0, 22) << (32 - 19));
1926 break;
1927 }
1928 case 0x1:
1929 // only constants can come after this
1930 num_instrs = 1;
1931 done = stop;
1932 case 0x5:
1933 header_bits = bits(words[2], 19, 32) | ((uint64_t) words[3] << (32 - 19));
1934 main_instr.add_bits |= (tag & 0x7) << 17;
1935 instrs[0] = main_instr;
1936 break;
1937 case 0x6:
1938 case 0x7: {
1939 unsigned pos = tag & 0xf;
1940 // note that `pos' encodes both the total number of
1941 // instructions and the position in the constant stream,
1942 // presumably because decoded constants and instructions
1943 // share a buffer in the decoder, but we only care about
1944 // the position in the constant stream; the total number of
1945 // instructions is redundant.
1946 unsigned const_idx = 0;
1947 switch (pos) {
1948 case 0:
1949 case 1:
1950 case 2:
1951 case 6:
1952 const_idx = 0;
1953 break;
1954 case 3:
1955 case 4:
1956 case 7:
1957 case 9:
1958 const_idx = 1;
1959 break;
1960 case 5:
1961 case 0xa:
1962 const_idx = 2;
1963 break;
1964 case 8:
1965 case 0xb:
1966 case 0xc:
1967 const_idx = 3;
1968 break;
1969 case 0xd:
1970 const_idx = 4;
1971 break;
1972 default:
1973 fprintf(fp, "# unknown pos 0x%x\n", pos);
1974 break;
1975 }
1976
1977 if (num_consts < const_idx + 2)
1978 num_consts = const_idx + 2;
1979
1980 consts[const_idx] = const0;
1981 consts[const_idx + 1] = const1;
1982 done = stop;
1983 break;
1984 }
1985 default:
1986 break;
1987 }
1988
1989 if (done)
1990 break;
1991 }
1992 }
1993
1994 *size = i + 1;
1995
1996 if (verbose) {
1997 fprintf(fp, "# header: %012" PRIx64 "\n", header_bits);
1998 }
1999
2000 struct bifrost_header header;
2001 memcpy((char *) &header, (char *) &header_bits, sizeof(struct bifrost_header));
2002 dump_header(fp, header, verbose);
2003 if (!header.no_end_of_shader)
2004 stopbit = true;
2005
2006 fprintf(fp, "{\n");
2007 for (i = 0; i < num_instrs; i++) {
2008 struct bifrost_regs next_regs;
2009 if (i + 1 == num_instrs) {
2010 memcpy((char *) &next_regs, (char *) &instrs[0].reg_bits,
2011 sizeof(next_regs));
2012 } else {
2013 memcpy((char *) &next_regs, (char *) &instrs[i + 1].reg_bits,
2014 sizeof(next_regs));
2015 }
2016
2017 dump_instr(fp, &instrs[i], next_regs, consts, header.datareg, offset, verbose);
2018 }
2019 fprintf(fp, "}\n");
2020
2021 if (verbose) {
2022 for (unsigned i = 0; i < num_consts; i++) {
2023 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i, consts[i] & 0xffffffff);
2024 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i + 1, consts[i] >> 32);
2025 }
2026 }
2027 return stopbit;
2028 }
2029
2030 void disassemble_bifrost(FILE *fp, uint8_t *code, size_t size, bool verbose)
2031 {
2032 uint32_t *words = (uint32_t *) code;
2033 uint32_t *words_end = words + (size / 4);
2034 // used for displaying branch targets
2035 unsigned offset = 0;
2036 while (words != words_end) {
2037 // we don't know what the program-end bit is quite yet, so for now just
2038 // assume that an all-0 quadword is padding
2039 uint32_t zero[4] = {};
2040 if (memcmp(words, zero, 4 * sizeof(uint32_t)) == 0)
2041 break;
2042 fprintf(fp, "clause_%d:\n", offset);
2043 unsigned size;
2044 if (dump_clause(fp, words, &size, offset, verbose) == true) {
2045 break;
2046 }
2047 words += size * 4;
2048 offset += size;
2049 }
2050 }
2051