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pan/bifrost: Sync disassembler with Ryan's tree
[mesa.git] / src / panfrost / bifrost / disassemble.c
1 /*
2 * Copyright (C) 2019 Connor Abbott <cwabbott0@gmail.com>
3 * Copyright (C) 2019 Lyude Paul <thatslyude@gmail.com>
4 * Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #include <stdbool.h>
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <assert.h>
30 #include <inttypes.h>
31 #include <string.h>
32
33 #include "bifrost.h"
34 #include "bifrost_ops.h"
35 #include "disassemble.h"
36 #include "util/macros.h"
37
38 // return bits (high, lo]
39 static uint64_t bits(uint32_t word, unsigned lo, unsigned high)
40 {
41 if (high == 32)
42 return word >> lo;
43 return (word & ((1 << high) - 1)) >> lo;
44 }
45
46 // each of these structs represents an instruction that's dispatched in one
47 // cycle. Note that these instructions are packed in funny ways within the
48 // clause, hence the need for a separate struct.
49 struct bifrost_alu_inst {
50 uint32_t fma_bits;
51 uint32_t add_bits;
52 uint64_t reg_bits;
53 };
54
55 struct bifrost_regs {
56 unsigned uniform_const : 8;
57 unsigned reg2 : 6;
58 unsigned reg3 : 6;
59 unsigned reg0 : 5;
60 unsigned reg1 : 6;
61 unsigned ctrl : 4;
62 };
63
64 static unsigned get_reg0(struct bifrost_regs regs)
65 {
66 if (regs.ctrl == 0)
67 return regs.reg0 | ((regs.reg1 & 0x1) << 5);
68
69 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0;
70 }
71
72 static unsigned get_reg1(struct bifrost_regs regs)
73 {
74 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1;
75 }
76
77 enum bifrost_reg_write_unit {
78 REG_WRITE_NONE = 0, // don't write
79 REG_WRITE_TWO, // write using reg2
80 REG_WRITE_THREE, // write using reg3
81 };
82
83 // this represents the decoded version of the ctrl register field.
84 struct bifrost_reg_ctrl{
85 bool read_reg0;
86 bool read_reg1;
87 bool read_reg3;
88 enum bifrost_reg_write_unit fma_write_unit;
89 enum bifrost_reg_write_unit add_write_unit;
90 bool clause_start;
91 };
92
93 enum fma_src_type {
94 FMA_ONE_SRC,
95 FMA_TWO_SRC,
96 FMA_FADD,
97 FMA_FMINMAX,
98 FMA_FADD16,
99 FMA_FMINMAX16,
100 FMA_FCMP,
101 FMA_FCMP16,
102 FMA_THREE_SRC,
103 FMA_FMA,
104 FMA_FMA16,
105 FMA_FOUR_SRC,
106 FMA_FMA_MSCALE,
107 FMA_SHIFT_ADD64,
108 };
109
110 struct fma_op_info {
111 unsigned op;
112 char name[30];
113 enum fma_src_type src_type;
114 };
115
116 enum add_src_type {
117 ADD_ONE_SRC,
118 ADD_TWO_SRC,
119 ADD_FADD,
120 ADD_FMINMAX,
121 ADD_FADD16,
122 ADD_FMINMAX16,
123 ADD_THREE_SRC,
124 ADD_FADDMscale,
125 ADD_FCMP,
126 ADD_FCMP16,
127 ADD_TEX_COMPACT, // texture instruction with embedded sampler
128 ADD_TEX, // texture instruction with sampler/etc. in uniform port
129 ADD_VARYING_INTERP,
130 ADD_BLENDING,
131 ADD_LOAD_ATTR,
132 ADD_VARYING_ADDRESS,
133 ADD_BRANCH,
134 };
135
136 struct add_op_info {
137 unsigned op;
138 char name[30];
139 enum add_src_type src_type;
140 bool has_data_reg;
141 };
142
143 struct bifrost_tex_ctrl {
144 unsigned sampler_index : 4; // also used to signal indirects
145 unsigned tex_index : 7;
146 bool no_merge_index : 1; // whether to merge (direct) sampler & texture indices
147 bool filter : 1; // use the usual filtering pipeline (0 for texelFetch & textureGather)
148 unsigned unk0 : 2;
149 bool texel_offset : 1; // *Offset()
150 bool is_shadow : 1;
151 bool is_array : 1;
152 unsigned tex_type : 2; // 2D, 3D, Cube, Buffer
153 bool compute_lod : 1; // 0 for *Lod()
154 bool not_supply_lod : 1; // 0 for *Lod() or when a bias is applied
155 bool calc_gradients : 1; // 0 for *Grad()
156 unsigned unk1 : 1;
157 unsigned result_type : 4; // integer, unsigned, float TODO: why is this 4 bits?
158 unsigned unk2 : 4;
159 };
160
161 struct bifrost_dual_tex_ctrl {
162 unsigned sampler_index0 : 2;
163 unsigned unk0 : 2;
164 unsigned tex_index0 : 2;
165 unsigned sampler_index1 : 2;
166 unsigned tex_index1 : 2;
167 unsigned unk1 : 22;
168 };
169
170 enum branch_bit_size {
171 BR_SIZE_32 = 0,
172 BR_SIZE_16XX = 1,
173 BR_SIZE_16YY = 2,
174 // For the above combinations of bitsize and location, an extra bit is
175 // encoded via comparing the sources. The only possible source of ambiguity
176 // would be if the sources were the same, but then the branch condition
177 // would be always true or always false anyways, so we can ignore it. But
178 // this no longer works when comparing the y component to the x component,
179 // since it's valid to compare the y component of a source against its own
180 // x component. Instead, the extra bit is encoded via an extra bitsize.
181 BR_SIZE_16YX0 = 3,
182 BR_SIZE_16YX1 = 4,
183 BR_SIZE_32_AND_16X = 5,
184 BR_SIZE_32_AND_16Y = 6,
185 // Used for comparisons with zero and always-true, see below. I think this
186 // only works for integer comparisons.
187 BR_SIZE_ZERO = 7,
188 };
189
190 void dump_header(struct bifrost_header header, bool verbose);
191 void dump_instr(const struct bifrost_alu_inst *instr, struct bifrost_regs next_regs, uint64_t *consts,
192 unsigned data_reg, unsigned offset, bool verbose);
193 bool dump_clause(uint32_t *words, unsigned *size, unsigned offset, bool verbose);
194
195 void dump_header(struct bifrost_header header, bool verbose) {
196 if (header.clause_type != 0) {
197 printf("id(%du) ", header.scoreboard_index);
198 }
199
200 if (header.scoreboard_deps != 0) {
201 printf("next-wait(");
202 bool first = true;
203 for (unsigned i = 0; i < 8; i++) {
204 if (header.scoreboard_deps & (1 << i)) {
205 if (!first) {
206 printf(", ");
207 }
208 printf("%d", i);
209 first = false;
210 }
211 }
212 printf(") ");
213 }
214
215 if (header.datareg_writebarrier)
216 printf("data-reg-barrier ");
217
218 if (!header.no_end_of_shader)
219 printf("eos ");
220
221 if (!header.back_to_back) {
222 printf("nbb ");
223 if (header.branch_cond)
224 printf("branch-cond ");
225 else
226 printf("branch-uncond ");
227 }
228
229 if (header.elide_writes)
230 printf("we ");
231
232 if (header.suppress_inf)
233 printf("suppress-inf ");
234 if (header.suppress_nan)
235 printf("suppress-nan ");
236
237 if (header.unk0)
238 printf("unk0 ");
239 if (header.unk1)
240 printf("unk1 ");
241 if (header.unk2)
242 printf("unk2 ");
243 if (header.unk3)
244 printf("unk3 ");
245 if (header.unk4)
246 printf("unk4 ");
247
248 printf("\n");
249
250 if (verbose) {
251 printf("# clause type %d, next clause type %d\n",
252 header.clause_type, header.next_clause_type);
253 }
254 }
255
256 static struct bifrost_reg_ctrl DecodeRegCtrl(struct bifrost_regs regs)
257 {
258 struct bifrost_reg_ctrl decoded = {};
259 unsigned ctrl;
260 if (regs.ctrl == 0) {
261 ctrl = regs.reg1 >> 2;
262 decoded.read_reg0 = !(regs.reg1 & 0x2);
263 decoded.read_reg1 = false;
264 } else {
265 ctrl = regs.ctrl;
266 decoded.read_reg0 = decoded.read_reg1 = true;
267 }
268 switch (ctrl) {
269 case 1:
270 decoded.fma_write_unit = REG_WRITE_TWO;
271 break;
272 case 2:
273 case 3:
274 decoded.fma_write_unit = REG_WRITE_TWO;
275 decoded.read_reg3 = true;
276 break;
277 case 4:
278 decoded.read_reg3 = true;
279 break;
280 case 5:
281 decoded.add_write_unit = REG_WRITE_TWO;
282 break;
283 case 6:
284 decoded.add_write_unit = REG_WRITE_TWO;
285 decoded.read_reg3 = true;
286 break;
287 case 8:
288 decoded.clause_start = true;
289 break;
290 case 9:
291 decoded.fma_write_unit = REG_WRITE_TWO;
292 decoded.clause_start = true;
293 break;
294 case 11:
295 break;
296 case 12:
297 decoded.read_reg3 = true;
298 decoded.clause_start = true;
299 break;
300 case 13:
301 decoded.add_write_unit = REG_WRITE_TWO;
302 decoded.clause_start = true;
303 break;
304
305 case 7:
306 case 15:
307 decoded.fma_write_unit = REG_WRITE_THREE;
308 decoded.add_write_unit = REG_WRITE_TWO;
309 break;
310 default:
311 printf("# unknown reg ctrl %d\n", ctrl);
312 }
313
314 return decoded;
315 }
316
317 // Pass in the add_write_unit or fma_write_unit, and this returns which register
318 // the ADD/FMA units are writing to
319 static unsigned GetRegToWrite(enum bifrost_reg_write_unit unit, struct bifrost_regs regs)
320 {
321 switch (unit) {
322 case REG_WRITE_TWO:
323 return regs.reg2;
324 case REG_WRITE_THREE:
325 return regs.reg3;
326 default: /* REG_WRITE_NONE */
327 assert(0);
328 return 0;
329 }
330 }
331
332 static void dump_regs(struct bifrost_regs srcs)
333 {
334 struct bifrost_reg_ctrl ctrl = DecodeRegCtrl(srcs);
335 printf("# ");
336 if (ctrl.read_reg0)
337 printf("port 0: R%d ", get_reg0(srcs));
338 if (ctrl.read_reg1)
339 printf("port 1: R%d ", get_reg1(srcs));
340
341 if (ctrl.fma_write_unit == REG_WRITE_TWO)
342 printf("port 2: R%d (write FMA) ", srcs.reg2);
343 else if (ctrl.add_write_unit == REG_WRITE_TWO)
344 printf("port 2: R%d (write ADD) ", srcs.reg2);
345
346 if (ctrl.fma_write_unit == REG_WRITE_THREE)
347 printf("port 3: R%d (write FMA) ", srcs.reg3);
348 else if (ctrl.add_write_unit == REG_WRITE_THREE)
349 printf("port 3: R%d (write ADD) ", srcs.reg3);
350 else if (ctrl.read_reg3)
351 printf("port 3: R%d (read) ", srcs.reg3);
352
353 if (srcs.uniform_const) {
354 if (srcs.uniform_const & 0x80) {
355 printf("uniform: U%d", (srcs.uniform_const & 0x7f) * 2);
356 }
357 }
358
359 printf("\n");
360 }
361 static void dump_const_imm(uint32_t imm)
362 {
363 union {
364 float f;
365 uint32_t i;
366 } fi;
367 fi.i = imm;
368 printf("0x%08x /* %f */", imm, fi.f);
369 }
370
371 static uint64_t get_const(uint64_t *consts, struct bifrost_regs srcs)
372 {
373 unsigned low_bits = srcs.uniform_const & 0xf;
374 uint64_t imm;
375 switch (srcs.uniform_const >> 4) {
376 case 4: imm = consts[0]; break;
377 case 5: imm = consts[1]; break;
378 case 6: imm = consts[2]; break;
379 case 7: imm = consts[3]; break;
380 case 2: imm = consts[4]; break;
381 case 3: imm = consts[5]; break;
382 default: assert(0); break;
383 }
384 return imm | low_bits;
385 }
386
387 static void dump_uniform_const_src(struct bifrost_regs srcs, uint64_t *consts, bool high32)
388 {
389 if (srcs.uniform_const & 0x80) {
390 unsigned uniform = (srcs.uniform_const & 0x7f) * 2;
391 printf("U%d", uniform + (high32 ? 1 : 0));
392 } else if (srcs.uniform_const >= 0x20) {
393 uint64_t imm = get_const(consts, srcs);
394 if (high32)
395 dump_const_imm(imm >> 32);
396 else
397 dump_const_imm(imm);
398 } else {
399 switch (srcs.uniform_const) {
400 case 0: printf("0"); break;
401 case 5: printf("atest-data"); break;
402 case 6: printf("sample-ptr"); break;
403 case 8:
404 case 9:
405 case 10:
406 case 11:
407 case 12:
408 case 13:
409 case 14:
410 case 15:
411 printf("blend-descriptor%u", (unsigned) srcs.uniform_const - 8);
412 break;
413 default:
414 printf("unkConst%u", (unsigned) srcs.uniform_const);
415 break;
416 }
417
418 if (high32)
419 printf(".y");
420 else
421 printf(".x");
422 }
423 }
424
425 static void dump_src(unsigned src, struct bifrost_regs srcs, uint64_t *consts, bool isFMA)
426 {
427 switch (src) {
428 case 0: printf("R%d", get_reg0(srcs)); break;
429 case 1: printf("R%d", get_reg1(srcs)); break;
430 case 2: printf("R%d", srcs.reg3); break;
431 case 3:
432 if (isFMA)
433 printf("0");
434 else
435 printf("T"); // i.e. the output of FMA this cycle
436 break;
437 case 4:
438 dump_uniform_const_src(srcs, consts, false);
439 break;
440 case 5:
441 dump_uniform_const_src(srcs, consts, true);
442 break;
443 case 6: printf("T0"); break;
444 case 7: printf("T1"); break;
445 }
446 }
447
448 static void dump_output_mod(unsigned mod)
449 {
450 switch (mod) {
451 case 0:
452 break;
453 case 1:
454 printf(".clamp_0_inf"); break; // max(out, 0)
455 case 2:
456 printf(".clamp_m1_1"); break; // clamp(out, -1, 1)
457 case 3:
458 printf(".clamp_0_1"); break; // clamp(out, 0, 1)
459 default:
460 break;
461 }
462 }
463
464 static void dump_minmax_mode(unsigned mod)
465 {
466 switch (mod) {
467 case 0:
468 /* Same as fmax() and fmin() -- return the other number if any
469 * number is NaN. Also always return +0 if one argument is +0 and
470 * the other is -0.
471 */
472 break;
473 case 1:
474 /* Instead of never returning a NaN, always return one. The
475 * "greater"/"lesser" NaN is always returned, first by checking the
476 * sign and then the mantissa bits.
477 */
478 printf(".nan_wins"); break;
479 case 2:
480 /* For max, implement src0 > src1 ? src0 : src1
481 * For min, implement src0 < src1 ? src0 : src1
482 *
483 * This includes handling NaN's and signedness of 0 differently
484 * from above, since +0 and -0 compare equal and comparisons always
485 * return false for NaN's. As a result, this mode is *not*
486 * commutative.
487 */
488 printf(".src1_wins"); break;
489 case 3:
490 /* For max, implement src0 < src1 ? src1 : src0
491 * For min, implement src0 > src1 ? src1 : src0
492 */
493 printf(".src0_wins"); break;
494 default:
495 break;
496 }
497 }
498
499 static void dump_round_mode(unsigned mod)
500 {
501 switch (mod) {
502 case 0:
503 /* roundTiesToEven, the IEEE default. */
504 break;
505 case 1:
506 /* roundTowardPositive in the IEEE spec. */
507 printf(".round_pos"); break;
508 case 2:
509 /* roundTowardNegative in the IEEE spec. */
510 printf(".round_neg"); break;
511 case 3:
512 /* roundTowardZero in the IEEE spec. */
513 printf(".round_zero"); break;
514 default:
515 break;
516 }
517 }
518
519 static const struct fma_op_info FMAOpInfos[] = {
520 { 0x00000, "FMA.f32", FMA_FMA },
521 { 0x40000, "MAX.f32", FMA_FMINMAX },
522 { 0x44000, "MIN.f32", FMA_FMINMAX },
523 { 0x48000, "FCMP.GL", FMA_FCMP },
524 { 0x4c000, "FCMP.D3D", FMA_FCMP },
525 { 0x4ff98, "ADD.i32", FMA_TWO_SRC },
526 { 0x4ffd8, "SUB.i32", FMA_TWO_SRC },
527 { 0x4fff0, "SUBB.i32", FMA_TWO_SRC },
528 { 0x50000, "FMA_MSCALE", FMA_FMA_MSCALE },
529 { 0x58000, "ADD.f32", FMA_FADD },
530 { 0x5c000, "CSEL.FEQ.f32", FMA_FOUR_SRC },
531 { 0x5c200, "CSEL.FGT.f32", FMA_FOUR_SRC },
532 { 0x5c400, "CSEL.FGE.f32", FMA_FOUR_SRC },
533 { 0x5c600, "CSEL.IEQ.f32", FMA_FOUR_SRC },
534 { 0x5c800, "CSEL.IGT.i32", FMA_FOUR_SRC },
535 { 0x5ca00, "CSEL.IGE.i32", FMA_FOUR_SRC },
536 { 0x5cc00, "CSEL.UGT.i32", FMA_FOUR_SRC },
537 { 0x5ce00, "CSEL.UGE.i32", FMA_FOUR_SRC },
538 { 0x5d8d0, "ICMP.D3D.GT.v2i16", FMA_TWO_SRC },
539 { 0x5d9d0, "UCMP.D3D.GT.v2i16", FMA_TWO_SRC },
540 { 0x5dad0, "ICMP.D3D.GE.v2i16", FMA_TWO_SRC },
541 { 0x5dbd0, "UCMP.D3D.GE.v2i16", FMA_TWO_SRC },
542 { 0x5dcd0, "ICMP.D3D.EQ.v2i16", FMA_TWO_SRC },
543 { 0x5de40, "ICMP.GL.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? 1 : 0
544 { 0x5de48, "ICMP.GL.GE.i32", FMA_TWO_SRC },
545 { 0x5de50, "UCMP.GL.GT.i32", FMA_TWO_SRC },
546 { 0x5de58, "UCMP.GL.GE.i32", FMA_TWO_SRC },
547 { 0x5de60, "ICMP.GL.EQ.i32", FMA_TWO_SRC },
548 { 0x5dec0, "ICMP.D3D.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? ~0 : 0
549 { 0x5dec8, "ICMP.D3D.GE.i32", FMA_TWO_SRC },
550 { 0x5ded0, "UCMP.D3D.GT.i32", FMA_TWO_SRC },
551 { 0x5ded8, "UCMP.D3D.GE.i32", FMA_TWO_SRC },
552 { 0x5dee0, "ICMP.D3D.EQ.i32", FMA_TWO_SRC },
553 { 0x60200, "RSHIFT_NAND.i32", FMA_THREE_SRC },
554 { 0x603c0, "RSHIFT_NAND.v2i16", FMA_THREE_SRC },
555 { 0x60e00, "RSHIFT_OR.i32", FMA_THREE_SRC },
556 { 0x60fc0, "RSHIFT_OR.v2i16", FMA_THREE_SRC },
557 { 0x61200, "RSHIFT_AND.i32", FMA_THREE_SRC },
558 { 0x613c0, "RSHIFT_AND.v2i16", FMA_THREE_SRC },
559 { 0x61e00, "RSHIFT_NOR.i32", FMA_THREE_SRC }, // ~((src0 << src2) | src1)
560 { 0x61fc0, "RSHIFT_NOR.v2i16", FMA_THREE_SRC }, // ~((src0 << src2) | src1)
561 { 0x62200, "LSHIFT_NAND.i32", FMA_THREE_SRC },
562 { 0x623c0, "LSHIFT_NAND.v2i16", FMA_THREE_SRC },
563 { 0x62e00, "LSHIFT_OR.i32", FMA_THREE_SRC }, // (src0 << src2) | src1
564 { 0x62fc0, "LSHIFT_OR.v2i16", FMA_THREE_SRC }, // (src0 << src2) | src1
565 { 0x63200, "LSHIFT_AND.i32", FMA_THREE_SRC }, // (src0 << src2) & src1
566 { 0x633c0, "LSHIFT_AND.v2i16", FMA_THREE_SRC },
567 { 0x63e00, "LSHIFT_NOR.i32", FMA_THREE_SRC },
568 { 0x63fc0, "LSHIFT_NOR.v2i16", FMA_THREE_SRC },
569 { 0x64200, "RSHIFT_XOR.i32", FMA_THREE_SRC },
570 { 0x643c0, "RSHIFT_XOR.v2i16", FMA_THREE_SRC },
571 { 0x64600, "RSHIFT_XNOR.i32", FMA_THREE_SRC }, // ~((src0 >> src2) ^ src1)
572 { 0x647c0, "RSHIFT_XNOR.v2i16", FMA_THREE_SRC }, // ~((src0 >> src2) ^ src1)
573 { 0x64a00, "LSHIFT_XOR.i32", FMA_THREE_SRC },
574 { 0x64bc0, "LSHIFT_XOR.v2i16", FMA_THREE_SRC },
575 { 0x64e00, "LSHIFT_XNOR.i32", FMA_THREE_SRC }, // ~((src0 >> src2) ^ src1)
576 { 0x64fc0, "LSHIFT_XNOR.v2i16", FMA_THREE_SRC }, // ~((src0 >> src2) ^ src1)
577 { 0x65200, "LSHIFT_ADD.i32", FMA_THREE_SRC },
578 { 0x65600, "LSHIFT_SUB.i32", FMA_THREE_SRC }, // (src0 << src2) - src1
579 { 0x65a00, "LSHIFT_RSUB.i32", FMA_THREE_SRC }, // src1 - (src0 << src2)
580 { 0x65e00, "RSHIFT_ADD.i32", FMA_THREE_SRC },
581 { 0x66200, "RSHIFT_SUB.i32", FMA_THREE_SRC },
582 { 0x66600, "RSHIFT_RSUB.i32", FMA_THREE_SRC },
583 { 0x66a00, "ARSHIFT_ADD.i32", FMA_THREE_SRC },
584 { 0x66e00, "ARSHIFT_SUB.i32", FMA_THREE_SRC },
585 { 0x67200, "ARSHIFT_RSUB.i32", FMA_THREE_SRC },
586 { 0x80000, "FMA.v2f16", FMA_FMA16 },
587 { 0xc0000, "MAX.v2f16", FMA_FMINMAX16 },
588 { 0xc4000, "MIN.v2f16", FMA_FMINMAX16 },
589 { 0xc8000, "FCMP.GL", FMA_FCMP16 },
590 { 0xcc000, "FCMP.D3D", FMA_FCMP16 },
591 { 0xcf900, "ADD.v2i16", FMA_TWO_SRC },
592 { 0xcfc10, "ADDC.i32", FMA_TWO_SRC },
593 { 0xcfd80, "ADD.i32.i16.X", FMA_TWO_SRC },
594 { 0xcfd90, "ADD.i32.u16.X", FMA_TWO_SRC },
595 { 0xcfdc0, "ADD.i32.i16.Y", FMA_TWO_SRC },
596 { 0xcfdd0, "ADD.i32.u16.Y", FMA_TWO_SRC },
597 { 0xd8000, "ADD.v2f16", FMA_FADD16 },
598 { 0xdc000, "CSEL.FEQ.v2f16", FMA_FOUR_SRC },
599 { 0xdc200, "CSEL.FGT.v2f16", FMA_FOUR_SRC },
600 { 0xdc400, "CSEL.FGE.v2f16", FMA_FOUR_SRC },
601 { 0xdc600, "CSEL.IEQ.v2f16", FMA_FOUR_SRC },
602 { 0xdc800, "CSEL.IGT.v2i16", FMA_FOUR_SRC },
603 { 0xdca00, "CSEL.IGE.v2i16", FMA_FOUR_SRC },
604 { 0xdcc00, "CSEL.UGT.v2i16", FMA_FOUR_SRC },
605 { 0xdce00, "CSEL.UGE.v2i16", FMA_FOUR_SRC },
606 { 0xdd000, "F32_TO_F16", FMA_TWO_SRC },
607 { 0xe0046, "F16_TO_I16.XX", FMA_ONE_SRC },
608 { 0xe0047, "F16_TO_U16.XX", FMA_ONE_SRC },
609 { 0xe004e, "F16_TO_I16.YX", FMA_ONE_SRC },
610 { 0xe004f, "F16_TO_U16.YX", FMA_ONE_SRC },
611 { 0xe0056, "F16_TO_I16.XY", FMA_ONE_SRC },
612 { 0xe0057, "F16_TO_U16.XY", FMA_ONE_SRC },
613 { 0xe005e, "F16_TO_I16.YY", FMA_ONE_SRC },
614 { 0xe005f, "F16_TO_U16.YY", FMA_ONE_SRC },
615 { 0xe00c0, "I16_TO_F16.XX", FMA_ONE_SRC },
616 { 0xe00c1, "U16_TO_F16.XX", FMA_ONE_SRC },
617 { 0xe00c8, "I16_TO_F16.YX", FMA_ONE_SRC },
618 { 0xe00c9, "U16_TO_F16.YX", FMA_ONE_SRC },
619 { 0xe00d0, "I16_TO_F16.XY", FMA_ONE_SRC },
620 { 0xe00d1, "U16_TO_F16.XY", FMA_ONE_SRC },
621 { 0xe00d8, "I16_TO_F16.YY", FMA_ONE_SRC },
622 { 0xe00d9, "U16_TO_F16.YY", FMA_ONE_SRC },
623 { 0xe0136, "F32_TO_I32", FMA_ONE_SRC },
624 { 0xe0137, "F32_TO_U32", FMA_ONE_SRC },
625 { 0xe0178, "I32_TO_F32", FMA_ONE_SRC },
626 { 0xe0179, "U32_TO_F32", FMA_ONE_SRC },
627 { 0xe0198, "I16_TO_I32.X", FMA_ONE_SRC },
628 { 0xe0199, "U16_TO_U32.X", FMA_ONE_SRC },
629 { 0xe019a, "I16_TO_I32.Y", FMA_ONE_SRC },
630 { 0xe019b, "U16_TO_U32.Y", FMA_ONE_SRC },
631 { 0xe019c, "I16_TO_F32.X", FMA_ONE_SRC },
632 { 0xe019d, "U16_TO_F32.X", FMA_ONE_SRC },
633 { 0xe019e, "I16_TO_F32.Y", FMA_ONE_SRC },
634 { 0xe019f, "U16_TO_F32.Y", FMA_ONE_SRC },
635 { 0xe01a2, "F16_TO_F32.X", FMA_ONE_SRC },
636 { 0xe01a3, "F16_TO_F32.Y", FMA_ONE_SRC },
637 { 0xe032c, "NOP", FMA_ONE_SRC },
638 { 0xe032d, "MOV", FMA_ONE_SRC },
639 { 0xe032f, "SWZ.YY.v2i16", FMA_ONE_SRC },
640 // From the ARM patent US20160364209A1:
641 // "Decompose v (the input) into numbers x1 and s such that v = x1 * 2^s,
642 // and x1 is a floating point value in a predetermined range where the
643 // value 1 is within the range and not at one extremity of the range (e.g.
644 // choose a range where 1 is towards middle of range)."
645 //
646 // This computes x1.
647 { 0xe0345, "LOG_FREXPM", FMA_ONE_SRC },
648 // Given a floating point number m * 2^e, returns m * 2^{-1}. This is
649 // exactly the same as the mantissa part of frexp().
650 { 0xe0365, "FRCP_FREXPM", FMA_ONE_SRC },
651 // Given a floating point number m * 2^e, returns m * 2^{-2} if e is even,
652 // and m * 2^{-1} if e is odd. In other words, scales by powers of 4 until
653 // within the range [0.25, 1). Used for square-root and reciprocal
654 // square-root.
655 { 0xe0375, "FSQRT_FREXPM", FMA_ONE_SRC },
656 // Given a floating point number m * 2^e, computes -e - 1 as an integer.
657 // Zero and infinity/NaN return 0.
658 { 0xe038d, "FRCP_FREXPE", FMA_ONE_SRC },
659 // Computes floor(e/2) + 1.
660 { 0xe03a5, "FSQRT_FREXPE", FMA_ONE_SRC },
661 // Given a floating point number m * 2^e, computes -floor(e/2) - 1 as an
662 // integer.
663 { 0xe03ad, "FRSQ_FREXPE", FMA_ONE_SRC },
664 { 0xe03c5, "LOG_FREXPE", FMA_ONE_SRC },
665 { 0xe03fa, "CLZ", FMA_ONE_SRC },
666 { 0xe0b80, "IMAX3", FMA_THREE_SRC },
667 { 0xe0bc0, "UMAX3", FMA_THREE_SRC },
668 { 0xe0c00, "IMIN3", FMA_THREE_SRC },
669 { 0xe0c40, "UMIN3", FMA_THREE_SRC },
670 { 0xe0ec5, "ROUND", FMA_ONE_SRC },
671 { 0xe0f40, "CSEL", FMA_THREE_SRC }, // src2 != 0 ? src1 : src0
672 { 0xe0fc0, "MUX.i32", FMA_THREE_SRC }, // see ADD comment
673 { 0xe1805, "ROUNDEVEN", FMA_ONE_SRC },
674 { 0xe1845, "CEIL", FMA_ONE_SRC },
675 { 0xe1885, "FLOOR", FMA_ONE_SRC },
676 { 0xe18c5, "TRUNC", FMA_ONE_SRC },
677 { 0xe19b0, "ATAN_LDEXP.Y.f32", FMA_TWO_SRC },
678 { 0xe19b8, "ATAN_LDEXP.X.f32", FMA_TWO_SRC },
679 // These instructions in the FMA slot, together with LSHIFT_ADD_HIGH32.i32
680 // in the ADD slot, allow one to do a 64-bit addition with an extra small
681 // shift on one of the sources. There are three possible scenarios:
682 //
683 // 1) Full 64-bit addition. Do:
684 // out.x = LSHIFT_ADD_LOW32.i64 src1.x, src2.x, shift
685 // out.y = LSHIFT_ADD_HIGH32.i32 src1.y, src2.y
686 //
687 // The shift amount is applied to src2 before adding. The shift amount, and
688 // any extra bits from src2 plus the overflow bit, are sent directly from
689 // FMA to ADD instead of being passed explicitly. Hence, these two must be
690 // bundled together into the same instruction.
691 //
692 // 2) Add a 64-bit value src1 to a zero-extended 32-bit value src2. Do:
693 // out.x = LSHIFT_ADD_LOW32.u32 src1.x, src2, shift
694 // out.y = LSHIFT_ADD_HIGH32.i32 src1.x, 0
695 //
696 // Note that in this case, the second argument to LSHIFT_ADD_HIGH32 is
697 // ignored, so it can actually be anything. As before, the shift is applied
698 // to src2 before adding.
699 //
700 // 3) Add a 64-bit value to a sign-extended 32-bit value src2. Do:
701 // out.x = LSHIFT_ADD_LOW32.i32 src1.x, src2, shift
702 // out.y = LSHIFT_ADD_HIGH32.i32 src1.x, 0
703 //
704 // The only difference is the .i32 instead of .u32. Otherwise, this is
705 // exactly the same as before.
706 //
707 // In all these instructions, the shift amount is stored where the third
708 // source would be, so the shift has to be a small immediate from 0 to 7.
709 // This is fine for the expected use-case of these instructions, which is
710 // manipulating 64-bit pointers.
711 //
712 // These instructions can also be combined with various load/store
713 // instructions which normally take a 64-bit pointer in order to add a
714 // 32-bit or 64-bit offset to the pointer before doing the operation,
715 // optionally shifting the offset. The load/store op implicity does
716 // LSHIFT_ADD_HIGH32.i32 internally. Letting ptr be the pointer, and offset
717 // the desired offset, the cases go as follows:
718 //
719 // 1) Add a 64-bit offset:
720 // LSHIFT_ADD_LOW32.i64 ptr.x, offset.x, shift
721 // ld_st_op ptr.y, offset.y, ...
722 //
723 // Note that the output of LSHIFT_ADD_LOW32.i64 is not used, instead being
724 // implicitly sent to the load/store op to serve as the low 32 bits of the
725 // pointer.
726 //
727 // 2) Add a 32-bit unsigned offset:
728 // temp = LSHIFT_ADD_LOW32.u32 ptr.x, offset, shift
729 // ld_st_op temp, ptr.y, ...
730 //
731 // Now, the low 32 bits of offset << shift + ptr are passed explicitly to
732 // the ld_st_op, to match the case where there is no offset and ld_st_op is
733 // called directly.
734 //
735 // 3) Add a 32-bit signed offset:
736 // temp = LSHIFT_ADD_LOW32.i32 ptr.x, offset, shift
737 // ld_st_op temp, ptr.y, ...
738 //
739 // Again, the same as the unsigned case except for the offset.
740 { 0xe1c80, "LSHIFT_ADD_LOW32.u32", FMA_SHIFT_ADD64 },
741 { 0xe1cc0, "LSHIFT_ADD_LOW32.i64", FMA_SHIFT_ADD64 },
742 { 0xe1d80, "LSHIFT_ADD_LOW32.i32", FMA_SHIFT_ADD64 },
743 { 0xe1e00, "SEL.XX.i16", FMA_TWO_SRC },
744 { 0xe1e08, "SEL.YX.i16", FMA_TWO_SRC },
745 { 0xe1e10, "SEL.XY.i16", FMA_TWO_SRC },
746 { 0xe1e18, "SEL.YY.i16", FMA_TWO_SRC },
747 { 0xe7800, "IMAD", FMA_THREE_SRC },
748 { 0xe78db, "POPCNT", FMA_ONE_SRC },
749 };
750
751 static struct fma_op_info find_fma_op_info(unsigned op)
752 {
753 for (unsigned i = 0; i < ARRAY_SIZE(FMAOpInfos); i++) {
754 unsigned opCmp = ~0;
755 switch (FMAOpInfos[i].src_type) {
756 case FMA_ONE_SRC:
757 opCmp = op;
758 break;
759 case FMA_TWO_SRC:
760 opCmp = op & ~0x7;
761 break;
762 case FMA_FCMP:
763 case FMA_FCMP16:
764 opCmp = op & ~0x1fff;
765 break;
766 case FMA_THREE_SRC:
767 case FMA_SHIFT_ADD64:
768 opCmp = op & ~0x3f;
769 break;
770 case FMA_FADD:
771 case FMA_FMINMAX:
772 case FMA_FADD16:
773 case FMA_FMINMAX16:
774 opCmp = op & ~0x3fff;
775 break;
776 case FMA_FMA:
777 case FMA_FMA16:
778 opCmp = op & ~0x3ffff;
779 break;
780 case FMA_FOUR_SRC:
781 opCmp = op & ~0x1ff;
782 break;
783 case FMA_FMA_MSCALE:
784 opCmp = op & ~0x7fff;
785 break;
786 default:
787 opCmp = ~0;
788 break;
789 }
790 if (FMAOpInfos[i].op == opCmp)
791 return FMAOpInfos[i];
792 }
793
794 struct fma_op_info info;
795 snprintf(info.name, sizeof(info.name), "op%04x", op);
796 info.op = op;
797 info.src_type = FMA_THREE_SRC;
798 return info;
799 }
800
801 static void dump_fcmp(unsigned op)
802 {
803 switch (op) {
804 case 0:
805 printf(".OEQ");
806 break;
807 case 1:
808 printf(".OGT");
809 break;
810 case 2:
811 printf(".OGE");
812 break;
813 case 3:
814 printf(".UNE");
815 break;
816 case 4:
817 printf(".OLT");
818 break;
819 case 5:
820 printf(".OLE");
821 break;
822 default:
823 printf(".unk%d", op);
824 break;
825 }
826 }
827
828 static void dump_16swizzle(unsigned swiz)
829 {
830 if (swiz == 2)
831 return;
832 printf(".%c%c", "xy"[swiz & 1], "xy"[(swiz >> 1) & 1]);
833 }
834
835 static void dump_fma_expand_src0(unsigned ctrl)
836 {
837 switch (ctrl) {
838 case 3:
839 case 4:
840 case 6:
841 printf(".x");
842 break;
843 case 5:
844 case 7:
845 printf(".y");
846 break;
847 case 0:
848 case 1:
849 case 2:
850 break;
851 default:
852 printf(".unk");
853 break;
854 }
855 }
856
857 static void dump_fma_expand_src1(unsigned ctrl)
858 {
859 switch (ctrl) {
860 case 1:
861 case 3:
862 printf(".x");
863 break;
864 case 2:
865 case 4:
866 case 5:
867 printf(".y");
868 break;
869 case 0:
870 case 6:
871 case 7:
872 break;
873 default:
874 printf(".unk");
875 break;
876 }
877 }
878
879 static void dump_fma(uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts, bool verbose)
880 {
881 if (verbose) {
882 printf("# FMA: %016" PRIx64 "\n", word);
883 }
884 struct bifrost_fma_inst FMA;
885 memcpy((char *) &FMA, (char *) &word, sizeof(struct bifrost_fma_inst));
886 struct fma_op_info info = find_fma_op_info(FMA.op);
887
888 printf("%s", info.name);
889 if (info.src_type == FMA_FADD ||
890 info.src_type == FMA_FMINMAX ||
891 info.src_type == FMA_FMA ||
892 info.src_type == FMA_FADD16 ||
893 info.src_type == FMA_FMINMAX16 ||
894 info.src_type == FMA_FMA16) {
895 dump_output_mod(bits(FMA.op, 12, 14));
896 switch (info.src_type) {
897 case FMA_FADD:
898 case FMA_FMA:
899 case FMA_FADD16:
900 case FMA_FMA16:
901 dump_round_mode(bits(FMA.op, 10, 12));
902 break;
903 case FMA_FMINMAX:
904 case FMA_FMINMAX16:
905 dump_minmax_mode(bits(FMA.op, 10, 12));
906 break;
907 default:
908 assert(0);
909 }
910 } else if (info.src_type == FMA_FCMP || info.src_type == FMA_FCMP16) {
911 dump_fcmp(bits(FMA.op, 10, 13));
912 if (info.src_type == FMA_FCMP)
913 printf(".f32");
914 else
915 printf(".v2f16");
916 } else if (info.src_type == FMA_FMA_MSCALE) {
917 if (FMA.op & (1 << 11)) {
918 switch ((FMA.op >> 9) & 0x3) {
919 case 0:
920 /* This mode seems to do a few things:
921 * - Makes 0 * infinity (and incidentally 0 * nan) return 0,
922 * since generating a nan would poison the result of
923 * 1/infinity and 1/0.
924 * - Fiddles with which nan is returned in nan * nan,
925 * presumably to make sure that the same exact nan is
926 * returned for 1/nan.
927 */
928 printf(".rcp_mode");
929 break;
930 case 3:
931 /* Similar to the above, but src0 always wins when multiplying
932 * 0 by infinity.
933 */
934 printf(".sqrt_mode");
935 break;
936 default:
937 printf(".unk%d_mode", (int) (FMA.op >> 9) & 0x3);
938 }
939 } else {
940 dump_output_mod(bits(FMA.op, 9, 11));
941 }
942 }
943
944 printf(" ");
945
946 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(next_regs);
947 if (next_ctrl.fma_write_unit != REG_WRITE_NONE) {
948 printf("{R%d, T0}, ", GetRegToWrite(next_ctrl.fma_write_unit, next_regs));
949 } else {
950 printf("T0, ");
951 }
952
953 switch (info.src_type) {
954 case FMA_ONE_SRC:
955 dump_src(FMA.src0, regs, consts, true);
956 break;
957 case FMA_TWO_SRC:
958 dump_src(FMA.src0, regs, consts, true);
959 printf(", ");
960 dump_src(FMA.op & 0x7, regs, consts, true);
961 break;
962 case FMA_FADD:
963 case FMA_FMINMAX:
964 if (FMA.op & 0x10)
965 printf("-");
966 if (FMA.op & 0x200)
967 printf("abs(");
968 dump_src(FMA.src0, regs, consts, true);
969 dump_fma_expand_src0((FMA.op >> 6) & 0x7);
970 if (FMA.op & 0x200)
971 printf(")");
972 printf(", ");
973 if (FMA.op & 0x20)
974 printf("-");
975 if (FMA.op & 0x8)
976 printf("abs(");
977 dump_src(FMA.op & 0x7, regs, consts, true);
978 dump_fma_expand_src1((FMA.op >> 6) & 0x7);
979 if (FMA.op & 0x8)
980 printf(")");
981 break;
982 case FMA_FADD16:
983 case FMA_FMINMAX16: {
984 bool abs1 = FMA.op & 0x8;
985 bool abs2 = (FMA.op & 0x7) < FMA.src0;
986 if (FMA.op & 0x10)
987 printf("-");
988 if (abs1 || abs2)
989 printf("abs(");
990 dump_src(FMA.src0, regs, consts, true);
991 dump_16swizzle((FMA.op >> 6) & 0x3);
992 if (abs1 || abs2)
993 printf(")");
994 printf(", ");
995 if (FMA.op & 0x20)
996 printf("-");
997 if (abs1 && abs2)
998 printf("abs(");
999 dump_src(FMA.op & 0x7, regs, consts, true);
1000 dump_16swizzle((FMA.op >> 8) & 0x3);
1001 if (abs1 && abs2)
1002 printf(")");
1003 break;
1004 }
1005 case FMA_FCMP:
1006 if (FMA.op & 0x200)
1007 printf("abs(");
1008 dump_src(FMA.src0, regs, consts, true);
1009 dump_fma_expand_src0((FMA.op >> 6) & 0x7);
1010 if (FMA.op & 0x200)
1011 printf(")");
1012 printf(", ");
1013 if (FMA.op & 0x20)
1014 printf("-");
1015 if (FMA.op & 0x8)
1016 printf("abs(");
1017 dump_src(FMA.op & 0x7, regs, consts, true);
1018 dump_fma_expand_src1((FMA.op >> 6) & 0x7);
1019 if (FMA.op & 0x8)
1020 printf(")");
1021 break;
1022 case FMA_FCMP16:
1023 dump_src(FMA.src0, regs, consts, true);
1024 // Note: this is kinda a guess, I haven't seen the blob set this to
1025 // anything other than the identity, but it matches FMA_TWO_SRCFmod16
1026 dump_16swizzle((FMA.op >> 6) & 0x3);
1027 printf(", ");
1028 dump_src(FMA.op & 0x7, regs, consts, true);
1029 dump_16swizzle((FMA.op >> 8) & 0x3);
1030 break;
1031 case FMA_SHIFT_ADD64:
1032 dump_src(FMA.src0, regs, consts, true);
1033 printf(", ");
1034 dump_src(FMA.op & 0x7, regs, consts, true);
1035 printf(", ");
1036 printf("shift:%u", (FMA.op >> 3) & 0x7);
1037 break;
1038 case FMA_THREE_SRC:
1039 dump_src(FMA.src0, regs, consts, true);
1040 printf(", ");
1041 dump_src(FMA.op & 0x7, regs, consts, true);
1042 printf(", ");
1043 dump_src((FMA.op >> 3) & 0x7, regs, consts, true);
1044 break;
1045 case FMA_FMA:
1046 if (FMA.op & (1 << 14))
1047 printf("-");
1048 if (FMA.op & (1 << 9))
1049 printf("abs(");
1050 dump_src(FMA.src0, regs, consts, true);
1051 dump_fma_expand_src0((FMA.op >> 6) & 0x7);
1052 if (FMA.op & (1 << 9))
1053 printf(")");
1054 printf(", ");
1055 if (FMA.op & (1 << 16))
1056 printf("abs(");
1057 dump_src(FMA.op & 0x7, regs, consts, true);
1058 dump_fma_expand_src1((FMA.op >> 6) & 0x7);
1059 if (FMA.op & (1 << 16))
1060 printf(")");
1061 printf(", ");
1062 if (FMA.op & (1 << 15))
1063 printf("-");
1064 if (FMA.op & (1 << 17))
1065 printf("abs(");
1066 dump_src((FMA.op >> 3) & 0x7, regs, consts, true);
1067 if (FMA.op & (1 << 17))
1068 printf(")");
1069 break;
1070 case FMA_FMA16:
1071 if (FMA.op & (1 << 14))
1072 printf("-");
1073 dump_src(FMA.src0, regs, consts, true);
1074 dump_16swizzle((FMA.op >> 6) & 0x3);
1075 printf(", ");
1076 dump_src(FMA.op & 0x7, regs, consts, true);
1077 dump_16swizzle((FMA.op >> 8) & 0x3);
1078 printf(", ");
1079 if (FMA.op & (1 << 15))
1080 printf("-");
1081 dump_src((FMA.op >> 3) & 0x7, regs, consts, true);
1082 dump_16swizzle((FMA.op >> 16) & 0x3);
1083 break;
1084 case FMA_FOUR_SRC:
1085 dump_src(FMA.src0, regs, consts, true);
1086 printf(", ");
1087 dump_src(FMA.op & 0x7, regs, consts, true);
1088 printf(", ");
1089 dump_src((FMA.op >> 3) & 0x7, regs, consts, true);
1090 printf(", ");
1091 dump_src((FMA.op >> 6) & 0x7, regs, consts, true);
1092 break;
1093 case FMA_FMA_MSCALE:
1094 if (FMA.op & (1 << 12))
1095 printf("abs(");
1096 dump_src(FMA.src0, regs, consts, true);
1097 if (FMA.op & (1 << 12))
1098 printf(")");
1099 printf(", ");
1100 if (FMA.op & (1 << 13))
1101 printf("-");
1102 dump_src(FMA.op & 0x7, regs, consts, true);
1103 printf(", ");
1104 if (FMA.op & (1 << 14))
1105 printf("-");
1106 dump_src((FMA.op >> 3) & 0x7, regs, consts, true);
1107 printf(", ");
1108 dump_src((FMA.op >> 6) & 0x7, regs, consts, true);
1109 break;
1110 }
1111 printf("\n");
1112 }
1113
1114 static const struct add_op_info add_op_infos[] = {
1115 { 0x00000, "MAX.f32", ADD_FMINMAX },
1116 { 0x02000, "MIN.f32", ADD_FMINMAX },
1117 { 0x04000, "ADD.f32", ADD_FADD },
1118 { 0x06000, "FCMP.GL", ADD_FCMP },
1119 { 0x07000, "FCMP.D3D", ADD_FCMP },
1120 { 0x07856, "F16_TO_I16", ADD_ONE_SRC },
1121 { 0x07857, "F16_TO_U16", ADD_ONE_SRC },
1122 { 0x078c0, "I16_TO_F16.XX", ADD_ONE_SRC },
1123 { 0x078c1, "U16_TO_F16.XX", ADD_ONE_SRC },
1124 { 0x078c8, "I16_TO_F16.YX", ADD_ONE_SRC },
1125 { 0x078c9, "U16_TO_F16.YX", ADD_ONE_SRC },
1126 { 0x078d0, "I16_TO_F16.XY", ADD_ONE_SRC },
1127 { 0x078d1, "U16_TO_F16.XY", ADD_ONE_SRC },
1128 { 0x078d8, "I16_TO_F16.YY", ADD_ONE_SRC },
1129 { 0x078d9, "U16_TO_F16.YY", ADD_ONE_SRC },
1130 { 0x07936, "F32_TO_I32", ADD_ONE_SRC },
1131 { 0x07937, "F32_TO_U32", ADD_ONE_SRC },
1132 { 0x07978, "I32_TO_F32", ADD_ONE_SRC },
1133 { 0x07979, "U32_TO_F32", ADD_ONE_SRC },
1134 { 0x07998, "I16_TO_I32.X", ADD_ONE_SRC },
1135 { 0x07999, "U16_TO_U32.X", ADD_ONE_SRC },
1136 { 0x0799a, "I16_TO_I32.Y", ADD_ONE_SRC },
1137 { 0x0799b, "U16_TO_U32.Y", ADD_ONE_SRC },
1138 { 0x0799c, "I16_TO_F32.X", ADD_ONE_SRC },
1139 { 0x0799d, "U16_TO_F32.X", ADD_ONE_SRC },
1140 { 0x0799e, "I16_TO_F32.Y", ADD_ONE_SRC },
1141 { 0x0799f, "U16_TO_F32.Y", ADD_ONE_SRC },
1142 // take the low 16 bits, and expand it to a 32-bit float
1143 { 0x079a2, "F16_TO_F32.X", ADD_ONE_SRC },
1144 // take the high 16 bits, ...
1145 { 0x079a3, "F16_TO_F32.Y", ADD_ONE_SRC },
1146 { 0x07b2b, "SWZ.YX.v2i16", ADD_ONE_SRC },
1147 { 0x07b2c, "NOP", ADD_ONE_SRC },
1148 { 0x07b29, "SWZ.XX.v2i16", ADD_ONE_SRC },
1149 // Logically, this should be SWZ.XY, but that's equivalent to a move, and
1150 // this seems to be the canonical way the blob generates a MOV.
1151 { 0x07b2d, "MOV", ADD_ONE_SRC },
1152 { 0x07b2f, "SWZ.YY.v2i16", ADD_ONE_SRC },
1153 // Given a floating point number m * 2^e, returns m ^ 2^{-1}.
1154 { 0x07b65, "FRCP_FREXPM", ADD_ONE_SRC },
1155 { 0x07b75, "FSQRT_FREXPM", ADD_ONE_SRC },
1156 { 0x07b8d, "FRCP_FREXPE", ADD_ONE_SRC },
1157 { 0x07ba5, "FSQRT_FREXPE", ADD_ONE_SRC },
1158 { 0x07bad, "FRSQ_FREXPE", ADD_ONE_SRC },
1159 // From the ARM patent US20160364209A1:
1160 // "Decompose v (the input) into numbers x1 and s such that v = x1 * 2^s,
1161 // and x1 is a floating point value in a predetermined range where the
1162 // value 1 is within the range and not at one extremity of the range (e.g.
1163 // choose a range where 1 is towards middle of range)."
1164 //
1165 // This computes s.
1166 { 0x07bc5, "FLOG_FREXPE", ADD_ONE_SRC },
1167 { 0x07d45, "CEIL", ADD_ONE_SRC },
1168 { 0x07d85, "FLOOR", ADD_ONE_SRC },
1169 { 0x07dc5, "TRUNC", ADD_ONE_SRC },
1170 { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC },
1171 { 0x08000, "LD_ATTR.f16", ADD_LOAD_ATTR, true },
1172 { 0x08100, "LD_ATTR.v2f16", ADD_LOAD_ATTR, true },
1173 { 0x08200, "LD_ATTR.v3f16", ADD_LOAD_ATTR, true },
1174 { 0x08300, "LD_ATTR.v4f16", ADD_LOAD_ATTR, true },
1175 { 0x08400, "LD_ATTR.f32", ADD_LOAD_ATTR, true },
1176 { 0x08500, "LD_ATTR.v3f32", ADD_LOAD_ATTR, true },
1177 { 0x08600, "LD_ATTR.v3f32", ADD_LOAD_ATTR, true },
1178 { 0x08700, "LD_ATTR.v4f32", ADD_LOAD_ATTR, true },
1179 { 0x08800, "LD_ATTR.i32", ADD_LOAD_ATTR, true },
1180 { 0x08900, "LD_ATTR.v3i32", ADD_LOAD_ATTR, true },
1181 { 0x08a00, "LD_ATTR.v3i32", ADD_LOAD_ATTR, true },
1182 { 0x08b00, "LD_ATTR.v4i32", ADD_LOAD_ATTR, true },
1183 { 0x08c00, "LD_ATTR.u32", ADD_LOAD_ATTR, true },
1184 { 0x08d00, "LD_ATTR.v3u32", ADD_LOAD_ATTR, true },
1185 { 0x08e00, "LD_ATTR.v3u32", ADD_LOAD_ATTR, true },
1186 { 0x08f00, "LD_ATTR.v4u32", ADD_LOAD_ATTR, true },
1187 { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP, true },
1188 { 0x0b000, "TEX", ADD_TEX_COMPACT, true },
1189 { 0x0c188, "LOAD.i32", ADD_TWO_SRC, true },
1190 { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC, true },
1191 { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1192 { 0x0c1c8, "LOAD.v2i32", ADD_TWO_SRC, true },
1193 { 0x0c1e0, "LD_UBO.v2i32", ADD_TWO_SRC, true },
1194 { 0x0c1f8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1195 { 0x0c208, "LOAD.v4i32", ADD_TWO_SRC, true },
1196 // src0 = offset, src1 = binding
1197 { 0x0c220, "LD_UBO.v4i32", ADD_TWO_SRC, true },
1198 { 0x0c238, "LD_SCRATCH.v4i32", ADD_TWO_SRC, true },
1199 { 0x0c248, "STORE.v4i32", ADD_TWO_SRC, true },
1200 { 0x0c278, "ST_SCRATCH.v4i32", ADD_TWO_SRC, true },
1201 { 0x0c588, "STORE.i32", ADD_TWO_SRC, true },
1202 { 0x0c5b8, "ST_SCRATCH.i32", ADD_TWO_SRC, true },
1203 { 0x0c5c8, "STORE.v2i32", ADD_TWO_SRC, true },
1204 { 0x0c5f8, "ST_SCRATCH.v2i32", ADD_TWO_SRC, true },
1205 { 0x0c648, "LOAD.u16", ADD_TWO_SRC, true }, // zero-extends
1206 { 0x0ca88, "LOAD.v3i32", ADD_TWO_SRC, true },
1207 { 0x0caa0, "LD_UBO.v3i32", ADD_TWO_SRC, true },
1208 { 0x0cab8, "LD_SCRATCH.v3i32", ADD_TWO_SRC, true },
1209 { 0x0cb88, "STORE.v3i32", ADD_TWO_SRC, true },
1210 { 0x0cbb8, "ST_SCRATCH.v3i32", ADD_TWO_SRC, true },
1211 // *_FAST does not exist on G71 (added to G51, G72, and everything after)
1212 { 0x0cc00, "FRCP_FAST.f32", ADD_ONE_SRC },
1213 { 0x0cc20, "FRSQ_FAST.f32", ADD_ONE_SRC },
1214 // Given a floating point number m * 2^e, produces a table-based
1215 // approximation of 2/m using the top 17 bits. Includes special cases for
1216 // infinity, NaN, and zero, and copies the sign bit.
1217 { 0x0ce00, "FRCP_TABLE", ADD_ONE_SRC },
1218 // Exists on G71
1219 { 0x0ce10, "FRCP_FAST.f16.X", ADD_ONE_SRC },
1220 // A similar table for inverse square root, using the high 17 bits of the
1221 // mantissa as well as the low bit of the exponent.
1222 { 0x0ce20, "FRSQ_TABLE", ADD_ONE_SRC },
1223 { 0x0ce30, "FRCP_FAST.f16.Y", ADD_ONE_SRC },
1224 { 0x0ce50, "FRSQ_FAST.f16.X", ADD_ONE_SRC },
1225 // Used in the argument reduction for log. Given a floating-point number
1226 // m * 2^e, uses the top 4 bits of m to produce an approximation to 1/m
1227 // with the exponent forced to 0 and only the top 5 bits are nonzero. 0,
1228 // infinity, and NaN all return 1.0.
1229 // See the ARM patent for more information.
1230 { 0x0ce60, "FRCP_APPROX", ADD_ONE_SRC },
1231 { 0x0ce70, "FRSQ_FAST.f16.Y", ADD_ONE_SRC },
1232 { 0x0cf40, "ATAN_ASSIST", ADD_TWO_SRC },
1233 { 0x0cf48, "ATAN_TABLE", ADD_TWO_SRC },
1234 { 0x0cf50, "SIN_TABLE", ADD_ONE_SRC },
1235 { 0x0cf51, "COS_TABLE", ADD_ONE_SRC },
1236 { 0x0cf58, "EXP_TABLE", ADD_ONE_SRC },
1237 { 0x0cf60, "FLOG2_TABLE", ADD_ONE_SRC },
1238 { 0x0cf64, "FLOGE_TABLE", ADD_ONE_SRC },
1239 { 0x0d000, "BRANCH", ADD_BRANCH },
1240 // For each bit i, return src2[i] ? src0[i] : src1[i]. In other words, this
1241 // is the same as (src2 & src0) | (~src2 & src1).
1242 { 0x0e8c0, "MUX", ADD_THREE_SRC },
1243 { 0x0e9b0, "ATAN_LDEXP.Y.f32", ADD_TWO_SRC },
1244 { 0x0e9b8, "ATAN_LDEXP.X.f32", ADD_TWO_SRC },
1245 { 0x0ea60, "SEL.XX.i16", ADD_TWO_SRC },
1246 { 0x0ea70, "SEL.XY.i16", ADD_TWO_SRC },
1247 { 0x0ea68, "SEL.YX.i16", ADD_TWO_SRC },
1248 { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC },
1249 { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC },
1250 { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC }, // src0 > src1 ? 1 : 0
1251 { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC },
1252 { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC },
1253 { 0x0f658, "UCMP.GL.GE", ADD_TWO_SRC },
1254 { 0x0f660, "ICMP.GL.EQ", ADD_TWO_SRC },
1255 { 0x0f6c0, "ICMP.D3D.GT", ADD_TWO_SRC }, // src0 > src1 ? ~0 : 0
1256 { 0x0f6c8, "ICMP.D3D.GE", ADD_TWO_SRC },
1257 { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC },
1258 { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC },
1259 { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC },
1260 { 0x10000, "MAX.v2f16", ADD_FMINMAX16 },
1261 { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale },
1262 { 0x12000, "MIN.v2f16", ADD_FMINMAX16 },
1263 { 0x14000, "ADD.v2f16", ADD_FADD16 },
1264 { 0x17000, "FCMP.D3D", ADD_FCMP16 },
1265 { 0x178c0, "ADD.i32", ADD_TWO_SRC },
1266 { 0x17900, "ADD.v2i16", ADD_TWO_SRC },
1267 { 0x17ac0, "SUB.i32", ADD_TWO_SRC },
1268 { 0x17c10, "ADDC.i32", ADD_TWO_SRC }, // adds src0 to the bottom bit of src1
1269 { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC },
1270 { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC },
1271 { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC },
1272 { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC },
1273 // Compute varying address and datatype (for storing in the vertex shader),
1274 // and store the vec3 result in the data register. The result is passed as
1275 // the 3 normal arguments to ST_VAR.
1276 { 0x18000, "LD_VAR_ADDR.f16", ADD_VARYING_ADDRESS, true },
1277 { 0x18100, "LD_VAR_ADDR.f32", ADD_VARYING_ADDRESS, true },
1278 { 0x18200, "LD_VAR_ADDR.i32", ADD_VARYING_ADDRESS, true },
1279 { 0x18300, "LD_VAR_ADDR.u32", ADD_VARYING_ADDRESS, true },
1280 // Implements alpha-to-coverage, as well as possibly the late depth and
1281 // stencil tests. The first source is the existing sample mask in R60
1282 // (possibly modified by gl_SampleMask), and the second source is the alpha
1283 // value. The sample mask is written right away based on the
1284 // alpha-to-coverage result using the normal register write mechanism,
1285 // since that doesn't need to read from any memory, and then written again
1286 // later based on the result of the stencil and depth tests using the
1287 // special register.
1288 { 0x191e8, "ATEST.f32", ADD_TWO_SRC, true },
1289 { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC, true },
1290 { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC, true },
1291 // store a varying given the address and datatype from LD_VAR_ADDR
1292 { 0x19300, "ST_VAR.v1", ADD_THREE_SRC, true },
1293 { 0x19340, "ST_VAR.v2", ADD_THREE_SRC, true },
1294 { 0x19380, "ST_VAR.v3", ADD_THREE_SRC, true },
1295 { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC, true },
1296 // This takes the sample coverage mask (computed by ATEST above) as a
1297 // regular argument, in addition to the vec4 color in the special register.
1298 { 0x1952c, "BLEND", ADD_BLENDING, true },
1299 { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP, true },
1300 { 0x1ae60, "TEX", ADD_TEX, true },
1301 { 0x1c000, "RSHIFT_NAND.i32", ADD_THREE_SRC },
1302 { 0x1c300, "RSHIFT_OR.i32", ADD_THREE_SRC },
1303 { 0x1c400, "RSHIFT_AND.i32", ADD_THREE_SRC },
1304 { 0x1c700, "RSHIFT_NOR.i32", ADD_THREE_SRC },
1305 { 0x1c800, "LSHIFT_NAND.i32", ADD_THREE_SRC },
1306 { 0x1cb00, "LSHIFT_OR.i32", ADD_THREE_SRC },
1307 { 0x1cc00, "LSHIFT_AND.i32", ADD_THREE_SRC },
1308 { 0x1cf00, "LSHIFT_NOR.i32", ADD_THREE_SRC },
1309 { 0x1d000, "RSHIFT_XOR.i32", ADD_THREE_SRC },
1310 { 0x1d100, "RSHIFT_XNOR.i32", ADD_THREE_SRC },
1311 { 0x1d200, "LSHIFT_XOR.i32", ADD_THREE_SRC },
1312 { 0x1d300, "LSHIFT_XNOR.i32", ADD_THREE_SRC },
1313 { 0x1d400, "LSHIFT_ADD.i32", ADD_THREE_SRC },
1314 { 0x1d500, "LSHIFT_SUB.i32", ADD_THREE_SRC },
1315 { 0x1d500, "LSHIFT_RSUB.i32", ADD_THREE_SRC },
1316 { 0x1d700, "RSHIFT_ADD.i32", ADD_THREE_SRC },
1317 { 0x1d800, "RSHIFT_SUB.i32", ADD_THREE_SRC },
1318 { 0x1d900, "RSHIFT_RSUB.i32", ADD_THREE_SRC },
1319 { 0x1da00, "ARSHIFT_ADD.i32", ADD_THREE_SRC },
1320 { 0x1db00, "ARSHIFT_SUB.i32", ADD_THREE_SRC },
1321 { 0x1dc00, "ARSHIFT_RSUB.i32", ADD_THREE_SRC },
1322 { 0x1dd18, "OR.i32", ADD_TWO_SRC },
1323 { 0x1dd20, "AND.i32", ADD_TWO_SRC },
1324 { 0x1dd60, "LSHIFT.i32", ADD_TWO_SRC },
1325 { 0x1dd50, "XOR.i32", ADD_TWO_SRC },
1326 { 0x1dd80, "RSHIFT.i32", ADD_TWO_SRC },
1327 { 0x1dda0, "ARSHIFT.i32", ADD_TWO_SRC },
1328 };
1329
1330 static struct add_op_info find_add_op_info(unsigned op)
1331 {
1332 for (unsigned i = 0; i < ARRAY_SIZE(add_op_infos); i++) {
1333 unsigned opCmp = ~0;
1334 switch (add_op_infos[i].src_type) {
1335 case ADD_ONE_SRC:
1336 case ADD_BLENDING:
1337 opCmp = op;
1338 break;
1339 case ADD_TWO_SRC:
1340 opCmp = op & ~0x7;
1341 break;
1342 case ADD_THREE_SRC:
1343 opCmp = op & ~0x3f;
1344 break;
1345 case ADD_TEX:
1346 opCmp = op & ~0xf;
1347 break;
1348 case ADD_FADD:
1349 case ADD_FMINMAX:
1350 case ADD_FADD16:
1351 opCmp = op & ~0x1fff;
1352 break;
1353 case ADD_FMINMAX16:
1354 case ADD_FADDMscale:
1355 opCmp = op & ~0xfff;
1356 break;
1357 case ADD_FCMP:
1358 case ADD_FCMP16:
1359 opCmp = op & ~0x7ff;
1360 break;
1361 case ADD_TEX_COMPACT:
1362 opCmp = op & ~0x3ff;
1363 break;
1364 case ADD_VARYING_INTERP:
1365 opCmp = op & ~0x7ff;
1366 break;
1367 case ADD_VARYING_ADDRESS:
1368 opCmp = op & ~0xff;
1369 break;
1370 case ADD_LOAD_ATTR:
1371 opCmp = op & ~0x7f;
1372 break;
1373 case ADD_BRANCH:
1374 opCmp = op & ~0xfff;
1375 break;
1376 default:
1377 opCmp = ~0;
1378 break;
1379 }
1380 if (add_op_infos[i].op == opCmp)
1381 return add_op_infos[i];
1382 }
1383
1384 struct add_op_info info;
1385 snprintf(info.name, sizeof(info.name), "op%04x", op);
1386 info.op = op;
1387 info.src_type = ADD_TWO_SRC;
1388 info.has_data_reg = true;
1389 return info;
1390 }
1391
1392 static void dump_add(uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts,
1393 unsigned data_reg, unsigned offset, bool verbose)
1394 {
1395 if (verbose) {
1396 printf("# ADD: %016" PRIx64 "\n", word);
1397 }
1398 struct bifrost_add_inst ADD;
1399 memcpy((char *) &ADD, (char *) &word, sizeof(ADD));
1400 struct add_op_info info = find_add_op_info(ADD.op);
1401
1402 printf("%s", info.name);
1403
1404 // float16 seems like it doesn't support output modifiers
1405 if (info.src_type == ADD_FADD || info.src_type == ADD_FMINMAX) {
1406 // output modifiers
1407 dump_output_mod(bits(ADD.op, 8, 10));
1408 if (info.src_type == ADD_FADD)
1409 dump_round_mode(bits(ADD.op, 10, 12));
1410 else
1411 dump_minmax_mode(bits(ADD.op, 10, 12));
1412 } else if (info.src_type == ADD_FCMP || info.src_type == ADD_FCMP16) {
1413 dump_fcmp(bits(ADD.op, 3, 6));
1414 if (info.src_type == ADD_FCMP)
1415 printf(".f32");
1416 else
1417 printf(".v2f16");
1418 } else if (info.src_type == ADD_FADDMscale) {
1419 switch ((ADD.op >> 6) & 0x7) {
1420 case 0: break;
1421 // causes GPU hangs on G71
1422 case 1: printf(".invalid"); break;
1423 // Same as usual outmod value.
1424 case 2: printf(".clamp_0_1"); break;
1425 // If src0 is infinite or NaN, flush it to zero so that the other
1426 // source is passed through unmodified.
1427 case 3: printf(".flush_src0_inf_nan"); break;
1428 // Vice versa.
1429 case 4: printf(".flush_src1_inf_nan"); break;
1430 // Every other case seems to behave the same as the above?
1431 default: printf(".unk%d", (ADD.op >> 6) & 0x7); break;
1432 }
1433 } else if (info.src_type == ADD_VARYING_INTERP) {
1434 if (ADD.op & 0x200)
1435 printf(".reuse");
1436 if (ADD.op & 0x400)
1437 printf(".flat");
1438 switch ((ADD.op >> 7) & 0x3) {
1439 case 0: printf(".per_frag"); break;
1440 case 1: printf(".centroid"); break;
1441 case 2: break;
1442 case 3: printf(".explicit"); break;
1443 }
1444 printf(".v%d", ((ADD.op >> 5) & 0x3) + 1);
1445 } else if (info.src_type == ADD_BRANCH) {
1446 enum branch_code branchCode = (enum branch_code) ((ADD.op >> 6) & 0x3f);
1447 if (branchCode == BR_ALWAYS) {
1448 // unconditional branch
1449 } else {
1450 enum branch_cond cond = (enum branch_cond) ((ADD.op >> 6) & 0x7);
1451 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1452 bool portSwapped = (ADD.op & 0x7) < ADD.src0;
1453 // See the comment in branch_bit_size
1454 if (size == BR_SIZE_16YX0)
1455 portSwapped = true;
1456 if (size == BR_SIZE_16YX1)
1457 portSwapped = false;
1458 // These sizes are only for floating point comparisons, so the
1459 // non-floating-point comparisons are reused to encode the flipped
1460 // versions.
1461 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y)
1462 portSwapped = false;
1463 // There's only one argument, so we reuse the extra argument to
1464 // encode this.
1465 if (size == BR_SIZE_ZERO)
1466 portSwapped = !(ADD.op & 1);
1467
1468 switch (cond) {
1469 case BR_COND_LT:
1470 if (portSwapped)
1471 printf(".LT.u");
1472 else
1473 printf(".LT.i");
1474 break;
1475 case BR_COND_LE:
1476 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y) {
1477 printf(".UNE.f");
1478 } else {
1479 if (portSwapped)
1480 printf(".LE.u");
1481 else
1482 printf(".LE.i");
1483 }
1484 break;
1485 case BR_COND_GT:
1486 if (portSwapped)
1487 printf(".GT.u");
1488 else
1489 printf(".GT.i");
1490 break;
1491 case BR_COND_GE:
1492 if (portSwapped)
1493 printf(".GE.u");
1494 else
1495 printf(".GE.i");
1496 break;
1497 case BR_COND_EQ:
1498 if (portSwapped)
1499 printf(".NE.i");
1500 else
1501 printf(".EQ.i");
1502 break;
1503 case BR_COND_OEQ:
1504 if (portSwapped)
1505 printf(".UNE.f");
1506 else
1507 printf(".OEQ.f");
1508 break;
1509 case BR_COND_OGT:
1510 if (portSwapped)
1511 printf(".OGT.unk.f");
1512 else
1513 printf(".OGT.f");
1514 break;
1515 case BR_COND_OLT:
1516 if (portSwapped)
1517 printf(".OLT.unk.f");
1518 else
1519 printf(".OLT.f");
1520 break;
1521 }
1522 switch (size) {
1523 case BR_SIZE_32:
1524 case BR_SIZE_32_AND_16X:
1525 case BR_SIZE_32_AND_16Y:
1526 printf("32");
1527 break;
1528 case BR_SIZE_16XX:
1529 case BR_SIZE_16YY:
1530 case BR_SIZE_16YX0:
1531 case BR_SIZE_16YX1:
1532 printf("16");
1533 break;
1534 case BR_SIZE_ZERO: {
1535 unsigned ctrl = (ADD.op >> 1) & 0x3;
1536 if (ctrl == 0)
1537 printf("32.Z");
1538 else
1539 printf("16.Z");
1540 break;
1541 }
1542 }
1543 }
1544 }
1545 printf(" ");
1546
1547 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(next_regs);
1548 if (next_ctrl.add_write_unit != REG_WRITE_NONE) {
1549 printf("{R%d, T1}, ", GetRegToWrite(next_ctrl.add_write_unit, next_regs));
1550 } else {
1551 printf("T1, ");
1552 }
1553
1554 switch (info.src_type) {
1555 case ADD_BLENDING:
1556 // Note: in this case, regs.uniform_const == location | 0x8
1557 // This probably means we can't load uniforms or immediates in the
1558 // same instruction. This re-uses the encoding that normally means
1559 // "disabled", where the low 4 bits are ignored. Perhaps the extra
1560 // 0x8 or'd in indicates this is happening.
1561 printf("location:%d, ", regs.uniform_const & 0x7);
1562 // fallthrough
1563 case ADD_ONE_SRC:
1564 dump_src(ADD.src0, regs, consts, false);
1565 break;
1566 case ADD_TEX:
1567 case ADD_TEX_COMPACT: {
1568 int tex_index;
1569 int sampler_index;
1570 bool dualTex = false;
1571 if (info.src_type == ADD_TEX_COMPACT) {
1572 tex_index = (ADD.op >> 3) & 0x7;
1573 sampler_index = (ADD.op >> 7) & 0x7;
1574 bool unknown = (ADD.op & 0x40);
1575 // TODO: figure out if the unknown bit is ever 0
1576 if (!unknown)
1577 printf("unknown ");
1578 } else {
1579 uint64_t constVal = get_const(consts, regs);
1580 uint32_t controlBits = (ADD.op & 0x8) ? (constVal >> 32) : constVal;
1581 struct bifrost_tex_ctrl ctrl;
1582 memcpy((char *) &ctrl, (char *) &controlBits, sizeof(ctrl));
1583
1584 // TODO: figure out what actually triggers dual-tex
1585 if (ctrl.result_type == 9) {
1586 struct bifrost_dual_tex_ctrl dualCtrl;
1587 memcpy((char *) &dualCtrl, (char *) &controlBits, sizeof(ctrl));
1588 printf("(dualtex) tex0:%d samp0:%d tex1:%d samp1:%d ",
1589 dualCtrl.tex_index0, dualCtrl.sampler_index0,
1590 dualCtrl.tex_index1, dualCtrl.sampler_index1);
1591 if (dualCtrl.unk0 != 3)
1592 printf("unk:%d ", dualCtrl.unk0);
1593 dualTex = true;
1594 } else {
1595 if (ctrl.no_merge_index) {
1596 tex_index = ctrl.tex_index;
1597 sampler_index = ctrl.sampler_index;
1598 } else {
1599 tex_index = sampler_index = ctrl.tex_index;
1600 unsigned unk = ctrl.sampler_index >> 2;
1601 if (unk != 3)
1602 printf("unk:%d ", unk);
1603 if (ctrl.sampler_index & 1)
1604 tex_index = -1;
1605 if (ctrl.sampler_index & 2)
1606 sampler_index = -1;
1607 }
1608
1609 if (ctrl.unk0 != 3)
1610 printf("unk0:%d ", ctrl.unk0);
1611 if (ctrl.unk1)
1612 printf("unk1 ");
1613 if (ctrl.unk2 != 0xf)
1614 printf("unk2:%x ", ctrl.unk2);
1615
1616 switch (ctrl.result_type) {
1617 case 0x4:
1618 printf("f32 "); break;
1619 case 0xe:
1620 printf("i32 "); break;
1621 case 0xf:
1622 printf("u32 "); break;
1623 default:
1624 printf("unktype(%x) ", ctrl.result_type);
1625 }
1626
1627 switch (ctrl.tex_type) {
1628 case 0:
1629 printf("cube "); break;
1630 case 1:
1631 printf("buffer "); break;
1632 case 2:
1633 printf("2D "); break;
1634 case 3:
1635 printf("3D "); break;
1636 }
1637
1638 if (ctrl.is_shadow)
1639 printf("shadow ");
1640 if (ctrl.is_array)
1641 printf("array ");
1642
1643 if (!ctrl.filter) {
1644 if (ctrl.calc_gradients) {
1645 int comp = (controlBits >> 20) & 0x3;
1646 printf("txg comp:%d ", comp);
1647 } else {
1648 printf("txf ");
1649 }
1650 } else {
1651 if (!ctrl.not_supply_lod) {
1652 if (ctrl.compute_lod)
1653 printf("lod_bias ");
1654 else
1655 printf("lod ");
1656 }
1657
1658 if (!ctrl.calc_gradients)
1659 printf("grad ");
1660 }
1661
1662 if (ctrl.texel_offset)
1663 printf("offset ");
1664 }
1665 }
1666
1667 if (!dualTex) {
1668 if (tex_index == -1)
1669 printf("tex:indirect ");
1670 else
1671 printf("tex:%d ", tex_index);
1672
1673 if (sampler_index == -1)
1674 printf("samp:indirect ");
1675 else
1676 printf("samp:%d ", sampler_index);
1677 }
1678 break;
1679 }
1680 case ADD_VARYING_INTERP: {
1681 unsigned addr = ADD.op & 0x1f;
1682 if (addr < 0b10100) {
1683 // direct addr
1684 printf("%d", addr);
1685 } else if (addr < 0b11000) {
1686 if (addr == 22)
1687 printf("fragw");
1688 else if (addr == 23)
1689 printf("fragz");
1690 else
1691 printf("unk%d", addr);
1692 } else {
1693 dump_src(ADD.op & 0x7, regs, consts, false);
1694 }
1695 printf(", ");
1696 dump_src(ADD.src0, regs, consts, false);
1697 break;
1698 }
1699 case ADD_VARYING_ADDRESS: {
1700 dump_src(ADD.src0, regs, consts, false);
1701 printf(", ");
1702 dump_src(ADD.op & 0x7, regs, consts, false);
1703 printf(", ");
1704 unsigned location = (ADD.op >> 3) & 0x1f;
1705 if (location < 16) {
1706 printf("location:%d", location);
1707 } else if (location == 20) {
1708 printf("location:%u", (uint32_t) get_const(consts, regs));
1709 } else if (location == 21) {
1710 printf("location:%u", (uint32_t) (get_const(consts, regs) >> 32));
1711 } else {
1712 printf("location:%d(unk)", location);
1713 }
1714 break;
1715 }
1716 case ADD_LOAD_ATTR:
1717 printf("location:%d, ", (ADD.op >> 3) & 0xf);
1718 case ADD_TWO_SRC:
1719 dump_src(ADD.src0, regs, consts, false);
1720 printf(", ");
1721 dump_src(ADD.op & 0x7, regs, consts, false);
1722 break;
1723 case ADD_THREE_SRC:
1724 dump_src(ADD.src0, regs, consts, false);
1725 printf(", ");
1726 dump_src(ADD.op & 0x7, regs, consts, false);
1727 printf(", ");
1728 dump_src((ADD.op >> 3) & 0x7, regs, consts, false);
1729 break;
1730 case ADD_FADD:
1731 case ADD_FMINMAX:
1732 if (ADD.op & 0x10)
1733 printf("-");
1734 if (ADD.op & 0x1000)
1735 printf("abs(");
1736 dump_src(ADD.src0, regs, consts, false);
1737 switch ((ADD.op >> 6) & 0x3) {
1738 case 3:
1739 printf(".x");
1740 break;
1741 default:
1742 break;
1743 }
1744 if (ADD.op & 0x1000)
1745 printf(")");
1746 printf(", ");
1747 if (ADD.op & 0x20)
1748 printf("-");
1749 if (ADD.op & 0x8)
1750 printf("abs(");
1751 dump_src(ADD.op & 0x7, regs, consts, false);
1752 switch ((ADD.op >> 6) & 0x3) {
1753 case 1:
1754 case 3:
1755 printf(".x");
1756 break;
1757 case 2:
1758 printf(".y");
1759 break;
1760 case 0:
1761 break;
1762 default:
1763 printf(".unk");
1764 break;
1765 }
1766 if (ADD.op & 0x8)
1767 printf(")");
1768 break;
1769 case ADD_FADD16:
1770 if (ADD.op & 0x10)
1771 printf("-");
1772 if (ADD.op & 0x1000)
1773 printf("abs(");
1774 dump_src(ADD.src0, regs, consts, false);
1775 if (ADD.op & 0x1000)
1776 printf(")");
1777 dump_16swizzle((ADD.op >> 6) & 0x3);
1778 printf(", ");
1779 if (ADD.op & 0x20)
1780 printf("-");
1781 if (ADD.op & 0x8)
1782 printf("abs(");
1783 dump_src(ADD.op & 0x7, regs, consts, false);
1784 dump_16swizzle((ADD.op >> 8) & 0x3);
1785 if (ADD.op & 0x8)
1786 printf(")");
1787 break;
1788 case ADD_FMINMAX16: {
1789 bool abs1 = ADD.op & 0x8;
1790 bool abs2 = (ADD.op & 0x7) < ADD.src0;
1791 if (ADD.op & 0x10)
1792 printf("-");
1793 if (abs1 || abs2)
1794 printf("abs(");
1795 dump_src(ADD.src0, regs, consts, false);
1796 dump_16swizzle((ADD.op >> 6) & 0x3);
1797 if (abs1 || abs2)
1798 printf(")");
1799 printf(", ");
1800 if (ADD.op & 0x20)
1801 printf("-");
1802 if (abs1 && abs2)
1803 printf("abs(");
1804 dump_src(ADD.op & 0x7, regs, consts, false);
1805 dump_16swizzle((ADD.op >> 8) & 0x3);
1806 if (abs1 && abs2)
1807 printf(")");
1808 break;
1809 }
1810 case ADD_FADDMscale: {
1811 if (ADD.op & 0x400)
1812 printf("-");
1813 if (ADD.op & 0x200)
1814 printf("abs(");
1815 dump_src(ADD.src0, regs, consts, false);
1816 if (ADD.op & 0x200)
1817 printf(")");
1818
1819 printf(", ");
1820
1821 if (ADD.op & 0x800)
1822 printf("-");
1823 dump_src(ADD.op & 0x7, regs, consts, false);
1824
1825 printf(", ");
1826
1827 dump_src((ADD.op >> 3) & 0x7, regs, consts, false);
1828 break;
1829 }
1830 case ADD_FCMP:
1831 if (ADD.op & 0x400) {
1832 printf("-");
1833 }
1834 if (ADD.op & 0x100) {
1835 printf("abs(");
1836 }
1837 dump_src(ADD.src0, regs, consts, false);
1838 switch ((ADD.op >> 6) & 0x3) {
1839 case 3:
1840 printf(".x");
1841 break;
1842 default:
1843 break;
1844 }
1845 if (ADD.op & 0x100) {
1846 printf(")");
1847 }
1848 printf(", ");
1849 if (ADD.op & 0x200) {
1850 printf("abs(");
1851 }
1852 dump_src(ADD.op & 0x7, regs, consts, false);
1853 switch ((ADD.op >> 6) & 0x3) {
1854 case 1:
1855 case 3:
1856 printf(".x");
1857 break;
1858 case 2:
1859 printf(".y");
1860 break;
1861 case 0:
1862 break;
1863 default:
1864 printf(".unk");
1865 break;
1866 }
1867 if (ADD.op & 0x200) {
1868 printf(")");
1869 }
1870 break;
1871 case ADD_FCMP16:
1872 dump_src(ADD.src0, regs, consts, false);
1873 dump_16swizzle((ADD.op >> 6) & 0x3);
1874 printf(", ");
1875 dump_src(ADD.op & 0x7, regs, consts, false);
1876 dump_16swizzle((ADD.op >> 8) & 0x3);
1877 break;
1878 case ADD_BRANCH: {
1879 enum branch_code code = (enum branch_code) ((ADD.op >> 6) & 0x3f);
1880 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1881 if (code != BR_ALWAYS) {
1882 dump_src(ADD.src0, regs, consts, false);
1883 switch (size) {
1884 case BR_SIZE_16XX:
1885 printf(".x");
1886 break;
1887 case BR_SIZE_16YY:
1888 case BR_SIZE_16YX0:
1889 case BR_SIZE_16YX1:
1890 printf(".y");
1891 break;
1892 case BR_SIZE_ZERO: {
1893 unsigned ctrl = (ADD.op >> 1) & 0x3;
1894 switch (ctrl) {
1895 case 1:
1896 printf(".y");
1897 break;
1898 case 2:
1899 printf(".x");
1900 break;
1901 default:
1902 break;
1903 }
1904 }
1905 default:
1906 break;
1907 }
1908 printf(", ");
1909 }
1910 if (code != BR_ALWAYS && size != BR_SIZE_ZERO) {
1911 dump_src(ADD.op & 0x7, regs, consts, false);
1912 switch (size) {
1913 case BR_SIZE_16XX:
1914 case BR_SIZE_16YX0:
1915 case BR_SIZE_16YX1:
1916 case BR_SIZE_32_AND_16X:
1917 printf(".x");
1918 break;
1919 case BR_SIZE_16YY:
1920 case BR_SIZE_32_AND_16Y:
1921 printf(".y");
1922 break;
1923 default:
1924 break;
1925 }
1926 printf(", ");
1927 }
1928 // I haven't had the chance to test if this actually specifies the
1929 // branch offset, since I couldn't get it to produce values other
1930 // than 5 (uniform/const high), but these three bits are always
1931 // consistent across branch instructions, so it makes sense...
1932 int offsetSrc = (ADD.op >> 3) & 0x7;
1933 if (offsetSrc == 4 || offsetSrc == 5) {
1934 // If the offset is known/constant, we can decode it
1935 uint32_t raw_offset;
1936 if (offsetSrc == 4)
1937 raw_offset = get_const(consts, regs);
1938 else
1939 raw_offset = get_const(consts, regs) >> 32;
1940 // The high 4 bits are flags, while the rest is the
1941 // twos-complement offset in bytes (here we convert to
1942 // clauses).
1943 int32_t branch_offset = ((int32_t) raw_offset << 4) >> 8;
1944
1945 // If high4 is the high 4 bits of the last 64-bit constant,
1946 // this is calculated as (high4 + 4) & 0xf, or 0 if the branch
1947 // offset itself is the last constant. Not sure if this is
1948 // actually used, or just garbage in unused bits, but in any
1949 // case, we can just ignore it here since it's redundant. Note
1950 // that if there is any padding, this will be 4 since the
1951 // padding counts as the last constant.
1952 unsigned flags = raw_offset >> 28;
1953 (void) flags;
1954
1955 // Note: the offset is in bytes, relative to the beginning of the
1956 // current clause, so a zero offset would be a loop back to the
1957 // same clause (annoyingly different from Midgard).
1958 printf("clause_%d", offset + branch_offset);
1959 } else {
1960 dump_src(offsetSrc, regs, consts, false);
1961 }
1962 }
1963 }
1964 if (info.has_data_reg) {
1965 printf(", R%d", data_reg);
1966 }
1967 printf("\n");
1968 }
1969
1970 void dump_instr(const struct bifrost_alu_inst *instr, struct bifrost_regs next_regs, uint64_t *consts,
1971 unsigned data_reg, unsigned offset, bool verbose)
1972 {
1973 struct bifrost_regs regs;
1974 memcpy((char *) &regs, (char *) &instr->reg_bits, sizeof(regs));
1975
1976 if (verbose) {
1977 printf("# regs: %016" PRIx64 "\n", instr->reg_bits);
1978 dump_regs(regs);
1979 }
1980 dump_fma(instr->fma_bits, regs, next_regs, consts, verbose);
1981 dump_add(instr->add_bits, regs, next_regs, consts, data_reg, offset, verbose);
1982 }
1983
1984 bool dump_clause(uint32_t *words, unsigned *size, unsigned offset, bool verbose) {
1985 // State for a decoded clause
1986 struct bifrost_alu_inst instrs[8] = {};
1987 uint64_t consts[6] = {};
1988 unsigned num_instrs = 0;
1989 unsigned num_consts = 0;
1990 uint64_t header_bits = 0;
1991 bool stopbit = false;
1992
1993 unsigned i;
1994 for (i = 0; ; i++, words += 4) {
1995 if (verbose) {
1996 printf("# ");
1997 for (int j = 0; j < 4; j++)
1998 printf("%08x ", words[3 - j]); // low bit on the right
1999 printf("\n");
2000 }
2001 unsigned tag = bits(words[0], 0, 8);
2002
2003 // speculatively decode some things that are common between many formats, so we can share some code
2004 struct bifrost_alu_inst main_instr = {};
2005 // 20 bits
2006 main_instr.add_bits = bits(words[2], 2, 32 - 13);
2007 // 23 bits
2008 main_instr.fma_bits = bits(words[1], 11, 32) | bits(words[2], 0, 2) << (32 - 11);
2009 // 35 bits
2010 main_instr.reg_bits = ((uint64_t) bits(words[1], 0, 11)) << 24 | (uint64_t) bits(words[0], 8, 32);
2011
2012 uint64_t const0 = bits(words[0], 8, 32) << 4 | (uint64_t) words[1] << 28 | bits(words[2], 0, 4) << 60;
2013 uint64_t const1 = bits(words[2], 4, 32) << 4 | (uint64_t) words[3] << 32;
2014
2015 bool stop = tag & 0x40;
2016
2017 if (verbose) {
2018 printf("# tag: 0x%02x\n", tag);
2019 }
2020 if (tag & 0x80) {
2021 unsigned idx = stop ? 5 : 2;
2022 main_instr.add_bits |= ((tag >> 3) & 0x7) << 17;
2023 instrs[idx + 1] = main_instr;
2024 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17);
2025 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10;
2026 consts[0] = bits(words[3], 17, 32) << 4;
2027 } else {
2028 bool done = false;
2029 switch ((tag >> 3) & 0x7) {
2030 case 0x0:
2031 switch (tag & 0x7) {
2032 case 0x3:
2033 main_instr.add_bits |= bits(words[3], 29, 32) << 17;
2034 instrs[1] = main_instr;
2035 num_instrs = 2;
2036 done = stop;
2037 break;
2038 case 0x4:
2039 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2040 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
2041 consts[0] = const0;
2042 num_instrs = 3;
2043 num_consts = 1;
2044 done = stop;
2045 break;
2046 case 0x1:
2047 case 0x5:
2048 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2049 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
2050 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
2051 instrs[3] = main_instr;
2052 if ((tag & 0x7) == 0x5) {
2053 num_instrs = 4;
2054 done = stop;
2055 }
2056 break;
2057 case 0x6:
2058 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2059 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
2060 consts[0] = const0;
2061 num_instrs = 6;
2062 num_consts = 1;
2063 done = stop;
2064 break;
2065 case 0x7:
2066 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2067 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
2068 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
2069 instrs[6] = main_instr;
2070 num_instrs = 7;
2071 done = stop;
2072 break;
2073 default:
2074 printf("unknown tag bits 0x%02x\n", tag);
2075 }
2076 break;
2077 case 0x2:
2078 case 0x3: {
2079 unsigned idx = ((tag >> 3) & 0x7) == 2 ? 4 : 7;
2080 main_instr.add_bits |= (tag & 0x7) << 17;
2081 instrs[idx] = main_instr;
2082 consts[0] |= (bits(words[2], 19, 32) | ((uint64_t) words[3] << 13)) << 19;
2083 num_consts = 1;
2084 num_instrs = idx + 1;
2085 done = stop;
2086 break;
2087 }
2088 case 0x4: {
2089 unsigned idx = stop ? 4 : 1;
2090 main_instr.add_bits |= (tag & 0x7) << 17;
2091 instrs[idx] = main_instr;
2092 instrs[idx + 1].fma_bits |= bits(words[3], 22, 32);
2093 instrs[idx + 1].reg_bits = bits(words[2], 19, 32) | (bits(words[3], 0, 22) << (32 - 19));
2094 break;
2095 }
2096 case 0x1:
2097 // only constants can come after this
2098 num_instrs = 1;
2099 done = stop;
2100 case 0x5:
2101 header_bits = bits(words[2], 19, 32) | ((uint64_t) words[3] << (32 - 19));
2102 main_instr.add_bits |= (tag & 0x7) << 17;
2103 instrs[0] = main_instr;
2104 break;
2105 case 0x6:
2106 case 0x7: {
2107 unsigned pos = tag & 0xf;
2108 // note that `pos' encodes both the total number of
2109 // instructions and the position in the constant stream,
2110 // presumably because decoded constants and instructions
2111 // share a buffer in the decoder, but we only care about
2112 // the position in the constant stream; the total number of
2113 // instructions is redundant.
2114 unsigned const_idx = 7;
2115 switch (pos) {
2116 case 0:
2117 case 1:
2118 case 2:
2119 case 6:
2120 const_idx = 0;
2121 break;
2122 case 3:
2123 case 4:
2124 case 7:
2125 case 9:
2126 const_idx = 1;
2127 break;
2128 case 5:
2129 case 0xa:
2130 const_idx = 2;
2131 break;
2132 case 8:
2133 case 0xb:
2134 case 0xc:
2135 const_idx = 3;
2136 break;
2137 case 0xd:
2138 const_idx = 4;
2139 break;
2140 default:
2141 printf("# unknown pos 0x%x\n", pos);
2142 }
2143 if (num_consts < const_idx + 2)
2144 num_consts = const_idx + 2;
2145 consts[const_idx] = const0;
2146 consts[const_idx + 1] = const1;
2147 done = stop;
2148 break;
2149 }
2150 default:
2151 break;
2152 }
2153
2154 if (done)
2155 break;
2156 }
2157 }
2158
2159 *size = i + 1;
2160
2161 if (verbose) {
2162 printf("# header: %012" PRIx64 "\n", header_bits);
2163 }
2164
2165 struct bifrost_header header;
2166 memcpy((char *) &header, (char *) &header_bits, sizeof(struct bifrost_header));
2167 dump_header(header, verbose);
2168 if (!header.no_end_of_shader)
2169 stopbit = true;
2170
2171 printf("{\n");
2172 for (i = 0; i < num_instrs; i++) {
2173 struct bifrost_regs next_regs;
2174 if (i + 1 == num_instrs) {
2175 memcpy((char *) &next_regs, (char *) &instrs[0].reg_bits,
2176 sizeof(next_regs));
2177 } else {
2178 memcpy((char *) &next_regs, (char *) &instrs[i + 1].reg_bits,
2179 sizeof(next_regs));
2180 }
2181
2182 dump_instr(&instrs[i], next_regs, consts, header.datareg, offset, verbose);
2183 }
2184 printf("}\n");
2185
2186 if (verbose) {
2187 for (unsigned i = 0; i < num_consts; i++) {
2188 printf("# const%d: %08" PRIx64 "\n", 2 * i, consts[i] & 0xffffffff);
2189 printf("# const%d: %08" PRIx64 "\n", 2 * i + 1, consts[i] >> 32);
2190 }
2191 }
2192 return stopbit;
2193 }
2194
2195 void disassemble_bifrost(uint8_t *code, size_t size, bool verbose)
2196 {
2197 uint32_t *words = (uint32_t *) code;
2198 uint32_t *words_end = words + (size / 4);
2199 // used for displaying branch targets
2200 unsigned offset = 0;
2201 while (words != words_end)
2202 {
2203 // we don't know what the program-end bit is quite yet, so for now just
2204 // assume that an all-0 quadword is padding
2205 uint32_t zero[4] = {};
2206 if (memcmp(words, zero, 4 * sizeof(uint32_t)) == 0)
2207 break;
2208 printf("clause_%d:\n", offset);
2209 unsigned size;
2210 if (dump_clause(words, &size, offset, verbose) == true) {
2211 break;
2212 }
2213 words += size * 4;
2214 offset += size;
2215 }
2216 }
2217