projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
pan/bi: Identify extended FMA opcodes
[mesa.git] / src / panfrost / bifrost / disassemble.c
1 /*
2 * Copyright (C) 2019 Connor Abbott <cwabbott0@gmail.com>
3 * Copyright (C) 2019 Lyude Paul <thatslyude@gmail.com>
4 * Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #include <stdbool.h>
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <assert.h>
30 #include <inttypes.h>
31 #include <string.h>
32
33 #include "bifrost.h"
34 #include "bifrost_ops.h"
35 #include "disassemble.h"
36 #include "util/macros.h"
37
38 // return bits (high, lo]
39 static uint64_t bits(uint32_t word, unsigned lo, unsigned high)
40 {
41 if (high == 32)
42 return word >> lo;
43 return (word & ((1 << high) - 1)) >> lo;
44 }
45
46 // each of these structs represents an instruction that's dispatched in one
47 // cycle. Note that these instructions are packed in funny ways within the
48 // clause, hence the need for a separate struct.
49 struct bifrost_alu_inst {
50 uint32_t fma_bits;
51 uint32_t add_bits;
52 uint64_t reg_bits;
53 };
54
55 struct bifrost_regs {
56 unsigned uniform_const : 8;
57 unsigned reg2 : 6;
58 unsigned reg3 : 6;
59 unsigned reg0 : 5;
60 unsigned reg1 : 6;
61 unsigned ctrl : 4;
62 };
63
64 static unsigned get_reg0(struct bifrost_regs regs)
65 {
66 if (regs.ctrl == 0)
67 return regs.reg0 | ((regs.reg1 & 0x1) << 5);
68
69 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0;
70 }
71
72 static unsigned get_reg1(struct bifrost_regs regs)
73 {
74 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1;
75 }
76
77 enum bifrost_reg_write_unit {
78 REG_WRITE_NONE = 0, // don't write
79 REG_WRITE_TWO, // write using reg2
80 REG_WRITE_THREE, // write using reg3
81 };
82
83 // this represents the decoded version of the ctrl register field.
84 struct bifrost_reg_ctrl {
85 bool read_reg0;
86 bool read_reg1;
87 bool read_reg3;
88 enum bifrost_reg_write_unit fma_write_unit;
89 enum bifrost_reg_write_unit add_write_unit;
90 bool clause_start;
91 };
92
93 enum fma_src_type {
94 FMA_ONE_SRC,
95 FMA_TWO_SRC,
96 FMA_FADD,
97 FMA_FMINMAX,
98 FMA_FADD16,
99 FMA_FMINMAX16,
100 FMA_FCMP,
101 FMA_FCMP16,
102 FMA_THREE_SRC,
103 FMA_SHIFT,
104 FMA_FMA,
105 FMA_FMA16,
106 FMA_CSEL4,
107 FMA_FMA_MSCALE,
108 FMA_SHIFT_ADD64,
109 };
110
111 struct fma_op_info {
112 bool extended;
113 unsigned op;
114 char name[30];
115 enum fma_src_type src_type;
116 };
117
118 enum add_src_type {
119 ADD_ONE_SRC,
120 ADD_TWO_SRC,
121 ADD_FADD,
122 ADD_FMINMAX,
123 ADD_FADD16,
124 ADD_FMINMAX16,
125 ADD_THREE_SRC,
126 ADD_FADDMscale,
127 ADD_FCMP,
128 ADD_FCMP16,
129 ADD_TEX_COMPACT, // texture instruction with embedded sampler
130 ADD_TEX, // texture instruction with sampler/etc. in uniform port
131 ADD_VARYING_INTERP,
132 ADD_BLENDING,
133 ADD_LOAD_ATTR,
134 ADD_VARYING_ADDRESS,
135 ADD_BRANCH,
136 };
137
138 struct add_op_info {
139 unsigned op;
140 char name[30];
141 enum add_src_type src_type;
142 bool has_data_reg;
143 };
144
145 struct bifrost_tex_ctrl {
146 unsigned sampler_index : 4; // also used to signal indirects
147 unsigned tex_index : 7;
148 bool no_merge_index : 1; // whether to merge (direct) sampler & texture indices
149 bool filter : 1; // use the usual filtering pipeline (0 for texelFetch & textureGather)
150 unsigned unk0 : 2;
151 bool texel_offset : 1; // *Offset()
152 bool is_shadow : 1;
153 bool is_array : 1;
154 unsigned tex_type : 2; // 2D, 3D, Cube, Buffer
155 bool compute_lod : 1; // 0 for *Lod()
156 bool not_supply_lod : 1; // 0 for *Lod() or when a bias is applied
157 bool calc_gradients : 1; // 0 for *Grad()
158 unsigned unk1 : 1;
159 unsigned result_type : 4; // integer, unsigned, float TODO: why is this 4 bits?
160 unsigned unk2 : 4;
161 };
162
163 struct bifrost_dual_tex_ctrl {
164 unsigned sampler_index0 : 2;
165 unsigned unk0 : 2;
166 unsigned tex_index0 : 2;
167 unsigned sampler_index1 : 2;
168 unsigned tex_index1 : 2;
169 unsigned unk1 : 22;
170 };
171
172 enum branch_bit_size {
173 BR_SIZE_32 = 0,
174 BR_SIZE_16XX = 1,
175 BR_SIZE_16YY = 2,
176 // For the above combinations of bitsize and location, an extra bit is
177 // encoded via comparing the sources. The only possible source of ambiguity
178 // would be if the sources were the same, but then the branch condition
179 // would be always true or always false anyways, so we can ignore it. But
180 // this no longer works when comparing the y component to the x component,
181 // since it's valid to compare the y component of a source against its own
182 // x component. Instead, the extra bit is encoded via an extra bitsize.
183 BR_SIZE_16YX0 = 3,
184 BR_SIZE_16YX1 = 4,
185 BR_SIZE_32_AND_16X = 5,
186 BR_SIZE_32_AND_16Y = 6,
187 // Used for comparisons with zero and always-true, see below. I think this
188 // only works for integer comparisons.
189 BR_SIZE_ZERO = 7,
190 };
191
192 void dump_header(FILE *fp, struct bifrost_header header, bool verbose);
193 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
194 struct bifrost_regs next_regs, uint64_t *consts,
195 unsigned data_reg, unsigned offset, bool verbose);
196 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose);
197
198 void dump_header(FILE *fp, struct bifrost_header header, bool verbose)
199 {
200 if (header.clause_type != 0) {
201 fprintf(fp, "id(%du) ", header.scoreboard_index);
202 }
203
204 if (header.scoreboard_deps != 0) {
205 fprintf(fp, "next-wait(");
206 bool first = true;
207 for (unsigned i = 0; i < 8; i++) {
208 if (header.scoreboard_deps & (1 << i)) {
209 if (!first) {
210 fprintf(fp, ", ");
211 }
212 fprintf(fp, "%d", i);
213 first = false;
214 }
215 }
216 fprintf(fp, ") ");
217 }
218
219 if (header.datareg_writebarrier)
220 fprintf(fp, "data-reg-barrier ");
221
222 if (!header.no_end_of_shader)
223 fprintf(fp, "eos ");
224
225 if (!header.back_to_back) {
226 fprintf(fp, "nbb ");
227 if (header.branch_cond)
228 fprintf(fp, "branch-cond ");
229 else
230 fprintf(fp, "branch-uncond ");
231 }
232
233 if (header.elide_writes)
234 fprintf(fp, "we ");
235
236 if (header.suppress_inf)
237 fprintf(fp, "suppress-inf ");
238 if (header.suppress_nan)
239 fprintf(fp, "suppress-nan ");
240
241 if (header.unk0)
242 fprintf(fp, "unk0 ");
243 if (header.unk1)
244 fprintf(fp, "unk1 ");
245 if (header.unk2)
246 fprintf(fp, "unk2 ");
247 if (header.unk3)
248 fprintf(fp, "unk3 ");
249 if (header.unk4)
250 fprintf(fp, "unk4 ");
251
252 fprintf(fp, "\n");
253
254 if (verbose) {
255 fprintf(fp, "# clause type %d, next clause type %d\n",
256 header.clause_type, header.next_clause_type);
257 }
258 }
259
260 static struct bifrost_reg_ctrl DecodeRegCtrl(FILE *fp, struct bifrost_regs regs)
261 {
262 struct bifrost_reg_ctrl decoded = {};
263 unsigned ctrl;
264 if (regs.ctrl == 0) {
265 ctrl = regs.reg1 >> 2;
266 decoded.read_reg0 = !(regs.reg1 & 0x2);
267 decoded.read_reg1 = false;
268 } else {
269 ctrl = regs.ctrl;
270 decoded.read_reg0 = decoded.read_reg1 = true;
271 }
272 switch (ctrl) {
273 case 1:
274 decoded.fma_write_unit = REG_WRITE_TWO;
275 break;
276 case 2:
277 case 3:
278 decoded.fma_write_unit = REG_WRITE_TWO;
279 decoded.read_reg3 = true;
280 break;
281 case 4:
282 decoded.read_reg3 = true;
283 break;
284 case 5:
285 decoded.add_write_unit = REG_WRITE_TWO;
286 break;
287 case 6:
288 decoded.add_write_unit = REG_WRITE_TWO;
289 decoded.read_reg3 = true;
290 break;
291 case 8:
292 decoded.clause_start = true;
293 break;
294 case 9:
295 decoded.fma_write_unit = REG_WRITE_TWO;
296 decoded.clause_start = true;
297 break;
298 case 11:
299 break;
300 case 12:
301 decoded.read_reg3 = true;
302 decoded.clause_start = true;
303 break;
304 case 13:
305 decoded.add_write_unit = REG_WRITE_TWO;
306 decoded.clause_start = true;
307 break;
308
309 case 7:
310 case 15:
311 decoded.fma_write_unit = REG_WRITE_THREE;
312 decoded.add_write_unit = REG_WRITE_TWO;
313 break;
314 default:
315 fprintf(fp, "# unknown reg ctrl %d\n", ctrl);
316 }
317
318 return decoded;
319 }
320
321 // Pass in the add_write_unit or fma_write_unit, and this returns which register
322 // the ADD/FMA units are writing to
323 static unsigned GetRegToWrite(enum bifrost_reg_write_unit unit, struct bifrost_regs regs)
324 {
325 switch (unit) {
326 case REG_WRITE_TWO:
327 return regs.reg2;
328 case REG_WRITE_THREE:
329 return regs.reg3;
330 default: /* REG_WRITE_NONE */
331 assert(0);
332 return 0;
333 }
334 }
335
336 static void dump_regs(FILE *fp, struct bifrost_regs srcs)
337 {
338 struct bifrost_reg_ctrl ctrl = DecodeRegCtrl(fp, srcs);
339 fprintf(fp, "# ");
340 if (ctrl.read_reg0)
341 fprintf(fp, "port 0: R%d ", get_reg0(srcs));
342 if (ctrl.read_reg1)
343 fprintf(fp, "port 1: R%d ", get_reg1(srcs));
344
345 if (ctrl.fma_write_unit == REG_WRITE_TWO)
346 fprintf(fp, "port 2: R%d (write FMA) ", srcs.reg2);
347 else if (ctrl.add_write_unit == REG_WRITE_TWO)
348 fprintf(fp, "port 2: R%d (write ADD) ", srcs.reg2);
349
350 if (ctrl.fma_write_unit == REG_WRITE_THREE)
351 fprintf(fp, "port 3: R%d (write FMA) ", srcs.reg3);
352 else if (ctrl.add_write_unit == REG_WRITE_THREE)
353 fprintf(fp, "port 3: R%d (write ADD) ", srcs.reg3);
354 else if (ctrl.read_reg3)
355 fprintf(fp, "port 3: R%d (read) ", srcs.reg3);
356
357 if (srcs.uniform_const) {
358 if (srcs.uniform_const & 0x80) {
359 fprintf(fp, "uniform: U%d", (srcs.uniform_const & 0x7f) * 2);
360 }
361 }
362
363 fprintf(fp, "\n");
364 }
365 static void dump_const_imm(FILE *fp, uint32_t imm)
366 {
367 union {
368 float f;
369 uint32_t i;
370 } fi;
371 fi.i = imm;
372 fprintf(fp, "0x%08x /* %f */", imm, fi.f);
373 }
374
375 static uint64_t get_const(uint64_t *consts, struct bifrost_regs srcs)
376 {
377 unsigned low_bits = srcs.uniform_const & 0xf;
378 uint64_t imm;
379 switch (srcs.uniform_const >> 4) {
380 case 4:
381 imm = consts[0];
382 break;
383 case 5:
384 imm = consts[1];
385 break;
386 case 6:
387 imm = consts[2];
388 break;
389 case 7:
390 imm = consts[3];
391 break;
392 case 2:
393 imm = consts[4];
394 break;
395 case 3:
396 imm = consts[5];
397 break;
398 default:
399 assert(0);
400 break;
401 }
402 return imm | low_bits;
403 }
404
405 static void dump_uniform_const_src(FILE *fp, struct bifrost_regs srcs, uint64_t *consts, bool high32)
406 {
407 if (srcs.uniform_const & 0x80) {
408 unsigned uniform = (srcs.uniform_const & 0x7f) * 2;
409 fprintf(fp, "U%d", uniform + (high32 ? 1 : 0));
410 } else if (srcs.uniform_const >= 0x20) {
411 uint64_t imm = get_const(consts, srcs);
412 if (high32)
413 dump_const_imm(fp, imm >> 32);
414 else
415 dump_const_imm(fp, imm);
416 } else {
417 switch (srcs.uniform_const) {
418 case 0:
419 fprintf(fp, "0");
420 break;
421 case 5:
422 fprintf(fp, "atest-data");
423 break;
424 case 6:
425 fprintf(fp, "sample-ptr");
426 break;
427 case 8:
428 case 9:
429 case 10:
430 case 11:
431 case 12:
432 case 13:
433 case 14:
434 case 15:
435 fprintf(fp, "blend-descriptor%u", (unsigned) srcs.uniform_const - 8);
436 break;
437 default:
438 fprintf(fp, "unkConst%u", (unsigned) srcs.uniform_const);
439 break;
440 }
441
442 if (high32)
443 fprintf(fp, ".y");
444 else
445 fprintf(fp, ".x");
446 }
447 }
448
449 static void dump_src(FILE *fp, unsigned src, struct bifrost_regs srcs, uint64_t *consts, bool isFMA)
450 {
451 switch (src) {
452 case 0:
453 fprintf(fp, "R%d", get_reg0(srcs));
454 break;
455 case 1:
456 fprintf(fp, "R%d", get_reg1(srcs));
457 break;
458 case 2:
459 fprintf(fp, "R%d", srcs.reg3);
460 break;
461 case 3:
462 if (isFMA)
463 fprintf(fp, "0");
464 else
465 fprintf(fp, "T"); // i.e. the output of FMA this cycle
466 break;
467 case 4:
468 dump_uniform_const_src(fp, srcs, consts, false);
469 break;
470 case 5:
471 dump_uniform_const_src(fp, srcs, consts, true);
472 break;
473 case 6:
474 fprintf(fp, "T0");
475 break;
476 case 7:
477 fprintf(fp, "T1");
478 break;
479 }
480 }
481
482 static void dump_output_mod(FILE *fp, unsigned mod)
483 {
484 switch (mod) {
485 case 0:
486 break;
487 case 1:
488 fprintf(fp, ".clamp_0_inf");
489 break; // max(out, 0)
490 case 2:
491 fprintf(fp, ".clamp_m1_1");
492 break; // clamp(out, -1, 1)
493 case 3:
494 fprintf(fp, ".clamp_0_1");
495 break; // clamp(out, 0, 1)
496 default:
497 break;
498 }
499 }
500
501 static void dump_minmax_mode(FILE *fp, unsigned mod)
502 {
503 switch (mod) {
504 case 0:
505 /* Same as fmax() and fmin() -- return the other number if any
506 * number is NaN. Also always return +0 if one argument is +0 and
507 * the other is -0.
508 */
509 break;
510 case 1:
511 /* Instead of never returning a NaN, always return one. The
512 * "greater"/"lesser" NaN is always returned, first by checking the
513 * sign and then the mantissa bits.
514 */
515 fprintf(fp, ".nan_wins");
516 break;
517 case 2:
518 /* For max, implement src0 > src1 ? src0 : src1
519 * For min, implement src0 < src1 ? src0 : src1
520 *
521 * This includes handling NaN's and signedness of 0 differently
522 * from above, since +0 and -0 compare equal and comparisons always
523 * return false for NaN's. As a result, this mode is *not*
524 * commutative.
525 */
526 fprintf(fp, ".src1_wins");
527 break;
528 case 3:
529 /* For max, implement src0 < src1 ? src1 : src0
530 * For min, implement src0 > src1 ? src1 : src0
531 */
532 fprintf(fp, ".src0_wins");
533 break;
534 default:
535 break;
536 }
537 }
538
539 static void dump_round_mode(FILE *fp, unsigned mod)
540 {
541 switch (mod) {
542 case 0:
543 /* roundTiesToEven, the IEEE default. */
544 break;
545 case 1:
546 /* roundTowardPositive in the IEEE spec. */
547 fprintf(fp, ".round_pos");
548 break;
549 case 2:
550 /* roundTowardNegative in the IEEE spec. */
551 fprintf(fp, ".round_neg");
552 break;
553 case 3:
554 /* roundTowardZero in the IEEE spec. */
555 fprintf(fp, ".round_zero");
556 break;
557 default:
558 break;
559 }
560 }
561
562 static const char *
563 csel_cond_name(enum bifrost_csel_cond cond)
564 {
565 switch (cond) {
566 case BIFROST_FEQ_F: return "feq.f";
567 case BIFROST_FGT_F: return "fgt.f";
568 case BIFROST_FGE_F: return "fge.f";
569 case BIFROST_IEQ_F: return "ieq.f";
570 case BIFROST_IGT_I: return "igt.i";
571 case BIFROST_IGE_I: return "uge.i";
572 case BIFROST_UGT_I: return "ugt.i";
573 case BIFROST_UGE_I: return "uge.i";
574 default: return "invalid";
575 }
576 }
577
578 static const struct fma_op_info FMAOpInfos[] = {
579 { false, 0x00000, "FMA.f32", FMA_FMA },
580 { false, 0x40000, "MAX.f32", FMA_FMINMAX },
581 { false, 0x44000, "MIN.f32", FMA_FMINMAX },
582 { false, 0x48000, "FCMP.GL", FMA_FCMP },
583 { false, 0x4c000, "FCMP.D3D", FMA_FCMP },
584 { false, 0x4ff98, "ADD.i32", FMA_TWO_SRC },
585 { false, 0x4ffd8, "SUB.i32", FMA_TWO_SRC },
586 { false, 0x4fff0, "SUBB.i32", FMA_TWO_SRC },
587 { false, 0x50000, "FMA_MSCALE", FMA_FMA_MSCALE },
588 { false, 0x58000, "ADD.f32", FMA_FADD },
589 { false, 0x5c000, "CSEL4", FMA_CSEL4 },
590 { false, 0x5d8d0, "ICMP.D3D.GT.v2i16", FMA_TWO_SRC },
591 { false, 0x5d9d0, "UCMP.D3D.GT.v2i16", FMA_TWO_SRC },
592 { false, 0x5dad0, "ICMP.D3D.GE.v2i16", FMA_TWO_SRC },
593 { false, 0x5dbd0, "UCMP.D3D.GE.v2i16", FMA_TWO_SRC },
594 { false, 0x5dcd0, "ICMP.D3D.EQ.v2i16", FMA_TWO_SRC },
595 { false, 0x5de40, "ICMP.GL.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? 1 : 0
596 { false, 0x5de48, "ICMP.GL.GE.i32", FMA_TWO_SRC },
597 { false, 0x5de50, "UCMP.GL.GT.i32", FMA_TWO_SRC },
598 { false, 0x5de58, "UCMP.GL.GE.i32", FMA_TWO_SRC },
599 { false, 0x5de60, "ICMP.GL.EQ.i32", FMA_TWO_SRC },
600 { false, 0x5dec0, "ICMP.D3D.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? ~0 : 0
601 { false, 0x5dec8, "ICMP.D3D.GE.i32", FMA_TWO_SRC },
602 { false, 0x5ded0, "UCMP.D3D.GT.i32", FMA_TWO_SRC },
603 { false, 0x5ded8, "UCMP.D3D.GE.i32", FMA_TWO_SRC },
604 { false, 0x5dee0, "ICMP.D3D.EQ.i32", FMA_TWO_SRC },
605 { false, 0x60000, "RSHIFT_NAND", FMA_SHIFT },
606 { false, 0x61000, "RSHIFT_AND", FMA_SHIFT },
607 { false, 0x62000, "LSHIFT_NAND", FMA_SHIFT },
608 { false, 0x63000, "LSHIFT_AND", FMA_SHIFT }, // (src0 << src2) & src1
609 { false, 0x64000, "RSHIFT_XOR", FMA_SHIFT },
610 { false, 0x65200, "LSHIFT_ADD.i32", FMA_THREE_SRC },
611 { false, 0x65600, "LSHIFT_SUB.i32", FMA_THREE_SRC }, // (src0 << src2) - src1
612 { false, 0x65a00, "LSHIFT_RSUB.i32", FMA_THREE_SRC }, // src1 - (src0 << src2)
613 { false, 0x65e00, "RSHIFT_ADD.i32", FMA_THREE_SRC },
614 { false, 0x66200, "RSHIFT_SUB.i32", FMA_THREE_SRC },
615 { false, 0x66600, "RSHIFT_RSUB.i32", FMA_THREE_SRC },
616 { false, 0x66a00, "ARSHIFT_ADD.i32", FMA_THREE_SRC },
617 { false, 0x66e00, "ARSHIFT_SUB.i32", FMA_THREE_SRC },
618 { false, 0x67200, "ARSHIFT_RSUB.i32", FMA_THREE_SRC },
619 { false, 0x80000, "FMA.v2f16", FMA_FMA16 },
620 { false, 0xc0000, "MAX.v2f16", FMA_FMINMAX16 },
621 { false, 0xc4000, "MIN.v2f16", FMA_FMINMAX16 },
622 { false, 0xc8000, "FCMP.GL", FMA_FCMP16 },
623 { false, 0xcc000, "FCMP.D3D", FMA_FCMP16 },
624 { false, 0xcf900, "ADD.v2i16", FMA_TWO_SRC },
625 { false, 0xcfc10, "ADDC.i32", FMA_TWO_SRC },
626 { false, 0xcfd80, "ADD.i32.i16.X", FMA_TWO_SRC },
627 { false, 0xcfd90, "ADD.i32.u16.X", FMA_TWO_SRC },
628 { false, 0xcfdc0, "ADD.i32.i16.Y", FMA_TWO_SRC },
629 { false, 0xcfdd0, "ADD.i32.u16.Y", FMA_TWO_SRC },
630 { false, 0xd8000, "ADD.v2f16", FMA_FADD16 },
631 { false, 0xdc000, "CSEL4.v16", FMA_CSEL4 },
632 { false, 0xdd000, "F32_TO_F16", FMA_TWO_SRC },
633 { true, 0x00046, "F16_TO_I16.XX", FMA_ONE_SRC },
634 { true, 0x00047, "F16_TO_U16.XX", FMA_ONE_SRC },
635 { true, 0x0004e, "F16_TO_I16.YX", FMA_ONE_SRC },
636 { true, 0x0004f, "F16_TO_U16.YX", FMA_ONE_SRC },
637 { true, 0x00056, "F16_TO_I16.XY", FMA_ONE_SRC },
638 { true, 0x00057, "F16_TO_U16.XY", FMA_ONE_SRC },
639 { true, 0x0005e, "F16_TO_I16.YY", FMA_ONE_SRC },
640 { true, 0x0005f, "F16_TO_U16.YY", FMA_ONE_SRC },
641 { true, 0x000c0, "I16_TO_F16.XX", FMA_ONE_SRC },
642 { true, 0x000c1, "U16_TO_F16.XX", FMA_ONE_SRC },
643 { true, 0x000c8, "I16_TO_F16.YX", FMA_ONE_SRC },
644 { true, 0x000c9, "U16_TO_F16.YX", FMA_ONE_SRC },
645 { true, 0x000d0, "I16_TO_F16.XY", FMA_ONE_SRC },
646 { true, 0x000d1, "U16_TO_F16.XY", FMA_ONE_SRC },
647 { true, 0x000d8, "I16_TO_F16.YY", FMA_ONE_SRC },
648 { true, 0x000d9, "U16_TO_F16.YY", FMA_ONE_SRC },
649 { true, 0x00136, "F32_TO_I32", FMA_ONE_SRC },
650 { true, 0x00137, "F32_TO_U32", FMA_ONE_SRC },
651 { true, 0x00178, "I32_TO_F32", FMA_ONE_SRC },
652 { true, 0x00179, "U32_TO_F32", FMA_ONE_SRC },
653 { true, 0x00198, "I16_TO_I32.X", FMA_ONE_SRC },
654 { true, 0x00199, "U16_TO_U32.X", FMA_ONE_SRC },
655 { true, 0x0019a, "I16_TO_I32.Y", FMA_ONE_SRC },
656 { true, 0x0019b, "U16_TO_U32.Y", FMA_ONE_SRC },
657 { true, 0x0019c, "I16_TO_F32.X", FMA_ONE_SRC },
658 { true, 0x0019d, "U16_TO_F32.X", FMA_ONE_SRC },
659 { true, 0x0019e, "I16_TO_F32.Y", FMA_ONE_SRC },
660 { true, 0x0019f, "U16_TO_F32.Y", FMA_ONE_SRC },
661 { true, 0x001a2, "F16_TO_F32.X", FMA_ONE_SRC },
662 { true, 0x001a3, "F16_TO_F32.Y", FMA_ONE_SRC },
663 { true, 0x0032c, "NOP", FMA_ONE_SRC },
664 { true, 0x0032d, "MOV", FMA_ONE_SRC },
665 { true, 0x0032f, "SWZ.YY.v2i16", FMA_ONE_SRC },
666 { true, 0x00345, "LOG_FREXPM", FMA_ONE_SRC },
667 { true, 0x00365, "FRCP_FREXPM", FMA_ONE_SRC },
668 { true, 0x00375, "FSQRT_FREXPM", FMA_ONE_SRC },
669 { true, 0x0038d, "FRCP_FREXPE", FMA_ONE_SRC },
670 { true, 0x003a5, "FSQRT_FREXPE", FMA_ONE_SRC },
671 { true, 0x003ad, "FRSQ_FREXPE", FMA_ONE_SRC },
672 { true, 0x003c5, "LOG_FREXPE", FMA_ONE_SRC },
673 { true, 0x003fa, "CLZ", FMA_ONE_SRC },
674 { true, 0x00b80, "IMAX3", FMA_THREE_SRC },
675 { true, 0x00bc0, "UMAX3", FMA_THREE_SRC },
676 { true, 0x00c00, "IMIN3", FMA_THREE_SRC },
677 { true, 0x00c40, "UMIN3", FMA_THREE_SRC },
678 { true, 0x00ec5, "ROUND", FMA_ONE_SRC },
679 { true, 0x00f40, "CSEL", FMA_THREE_SRC }, // src2 != 0 ? src1 : src0
680 { true, 0x00fc0, "MUX.i32", FMA_THREE_SRC }, // see ADD comment
681 { true, 0x01805, "ROUNDEVEN", FMA_ONE_SRC },
682 { true, 0x01845, "CEIL", FMA_ONE_SRC },
683 { true, 0x01885, "FLOOR", FMA_ONE_SRC },
684 { true, 0x018c5, "TRUNC", FMA_ONE_SRC },
685 { true, 0x019b0, "ATAN_LDEXP.Y.f32", FMA_TWO_SRC },
686 { true, 0x019b8, "ATAN_LDEXP.X.f32", FMA_TWO_SRC },
687 { true, 0x01c80, "LSHIFT_ADD_LOW32.u32", FMA_SHIFT_ADD64 },
688 { true, 0x01cc0, "LSHIFT_ADD_LOW32.i64", FMA_SHIFT_ADD64 },
689 { true, 0x01d80, "LSHIFT_ADD_LOW32.i32", FMA_SHIFT_ADD64 },
690 { true, 0x01e00, "SEL.XX.i16", FMA_TWO_SRC },
691 { true, 0x01e08, "SEL.YX.i16", FMA_TWO_SRC },
692 { true, 0x01e10, "SEL.XY.i16", FMA_TWO_SRC },
693 { true, 0x01e18, "SEL.YY.i16", FMA_TWO_SRC },
694 { true, 0x00800, "IMAD", FMA_THREE_SRC },
695 { true, 0x078db, "POPCNT", FMA_ONE_SRC },
696 };
697
698 static struct fma_op_info find_fma_op_info(unsigned op, bool extended)
699 {
700 for (unsigned i = 0; i < ARRAY_SIZE(FMAOpInfos); i++) {
701 unsigned opCmp = ~0;
702
703 if (FMAOpInfos[i].extended != extended)
704 continue;
705
706 if (extended)
707 op &= ~0xe0000;
708
709 switch (FMAOpInfos[i].src_type) {
710 case FMA_ONE_SRC:
711 opCmp = op;
712 break;
713 case FMA_TWO_SRC:
714 opCmp = op & ~0x7;
715 break;
716 case FMA_FCMP:
717 case FMA_FCMP16:
718 opCmp = op & ~0x1fff;
719 break;
720 case FMA_THREE_SRC:
721 case FMA_SHIFT_ADD64:
722 opCmp = op & ~0x3f;
723 break;
724 case FMA_FADD:
725 case FMA_FMINMAX:
726 case FMA_FADD16:
727 case FMA_FMINMAX16:
728 opCmp = op & ~0x3fff;
729 break;
730 case FMA_FMA:
731 case FMA_FMA16:
732 opCmp = op & ~0x3ffff;
733 break;
734 case FMA_CSEL4:
735 case FMA_SHIFT:
736 opCmp = op & ~0xfff;
737 break;
738 case FMA_FMA_MSCALE:
739 opCmp = op & ~0x7fff;
740 break;
741 default:
742 opCmp = ~0;
743 break;
744 }
745 if (FMAOpInfos[i].op == opCmp)
746 return FMAOpInfos[i];
747 }
748
749 struct fma_op_info info;
750 snprintf(info.name, sizeof(info.name), "op%04x", op);
751 info.op = op;
752 info.src_type = FMA_THREE_SRC;
753 return info;
754 }
755
756 static void dump_fcmp(FILE *fp, unsigned op)
757 {
758 switch (op) {
759 case 0:
760 fprintf(fp, ".OEQ");
761 break;
762 case 1:
763 fprintf(fp, ".OGT");
764 break;
765 case 2:
766 fprintf(fp, ".OGE");
767 break;
768 case 3:
769 fprintf(fp, ".UNE");
770 break;
771 case 4:
772 fprintf(fp, ".OLT");
773 break;
774 case 5:
775 fprintf(fp, ".OLE");
776 break;
777 default:
778 fprintf(fp, ".unk%d", op);
779 break;
780 }
781 }
782
783 static void dump_16swizzle(FILE *fp, unsigned swiz)
784 {
785 if (swiz == 2)
786 return;
787 fprintf(fp, ".%c%c", "xy"[swiz & 1], "xy"[(swiz >> 1) & 1]);
788 }
789
790 static void dump_fma_expand_src0(FILE *fp, unsigned ctrl)
791 {
792 switch (ctrl) {
793 case 3:
794 case 4:
795 case 6:
796 fprintf(fp, ".x");
797 break;
798 case 5:
799 case 7:
800 fprintf(fp, ".y");
801 break;
802 case 0:
803 case 1:
804 case 2:
805 break;
806 default:
807 fprintf(fp, ".unk");
808 break;
809 }
810 }
811
812 static void dump_fma_expand_src1(FILE *fp, unsigned ctrl)
813 {
814 switch (ctrl) {
815 case 1:
816 case 3:
817 fprintf(fp, ".x");
818 break;
819 case 2:
820 case 4:
821 case 5:
822 fprintf(fp, ".y");
823 break;
824 case 0:
825 case 6:
826 case 7:
827 break;
828 default:
829 fprintf(fp, ".unk");
830 break;
831 }
832 }
833
834 static void dump_fma(FILE *fp, uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts, bool verbose)
835 {
836 if (verbose) {
837 fprintf(fp, "# FMA: %016" PRIx64 "\n", word);
838 }
839 struct bifrost_fma_inst FMA;
840 memcpy((char *) &FMA, (char *) &word, sizeof(struct bifrost_fma_inst));
841 struct fma_op_info info = find_fma_op_info(FMA.op, (FMA.op & 0xe0000) == 0xe0000);
842
843 fprintf(fp, "%s", info.name);
844 if (info.src_type == FMA_FADD ||
845 info.src_type == FMA_FMINMAX ||
846 info.src_type == FMA_FMA ||
847 info.src_type == FMA_FADD16 ||
848 info.src_type == FMA_FMINMAX16 ||
849 info.src_type == FMA_FMA16) {
850 dump_output_mod(fp, bits(FMA.op, 12, 14));
851 switch (info.src_type) {
852 case FMA_FADD:
853 case FMA_FMA:
854 case FMA_FADD16:
855 case FMA_FMA16:
856 dump_round_mode(fp, bits(FMA.op, 10, 12));
857 break;
858 case FMA_FMINMAX:
859 case FMA_FMINMAX16:
860 dump_minmax_mode(fp, bits(FMA.op, 10, 12));
861 break;
862 default:
863 assert(0);
864 }
865 } else if (info.src_type == FMA_FCMP || info.src_type == FMA_FCMP16) {
866 dump_fcmp(fp, bits(FMA.op, 10, 13));
867 if (info.src_type == FMA_FCMP)
868 fprintf(fp, ".f32");
869 else
870 fprintf(fp, ".v2f16");
871 } else if (info.src_type == FMA_FMA_MSCALE) {
872 if (FMA.op & (1 << 11)) {
873 switch ((FMA.op >> 9) & 0x3) {
874 case 0:
875 /* This mode seems to do a few things:
876 * - Makes 0 * infinity (and incidentally 0 * nan) return 0,
877 * since generating a nan would poison the result of
878 * 1/infinity and 1/0.
879 * - Fiddles with which nan is returned in nan * nan,
880 * presumably to make sure that the same exact nan is
881 * returned for 1/nan.
882 */
883 fprintf(fp, ".rcp_mode");
884 break;
885 case 3:
886 /* Similar to the above, but src0 always wins when multiplying
887 * 0 by infinity.
888 */
889 fprintf(fp, ".sqrt_mode");
890 break;
891 default:
892 fprintf(fp, ".unk%d_mode", (int) (FMA.op >> 9) & 0x3);
893 }
894 } else {
895 dump_output_mod(fp, bits(FMA.op, 9, 11));
896 }
897 } else if (info.src_type == FMA_SHIFT) {
898 struct bifrost_shift_fma shift;
899 memcpy(&shift, &FMA, sizeof(shift));
900
901 if (shift.half == 0x7)
902 fprintf(fp, ".v2i16");
903 else if (shift.half == 0)
904 fprintf(fp, ".i32");
905 else if (shift.half == 0x4)
906 fprintf(fp, ".v4i8");
907 else
908 fprintf(fp, ".unk%u", shift.half);
909
910 if (!shift.unk)
911 fprintf(fp, ".no_unk");
912
913 if (shift.invert_1)
914 fprintf(fp, ".invert_1");
915
916 if (shift.invert_2)
917 fprintf(fp, ".invert_2");
918 }
919
920 fprintf(fp, " ");
921
922 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
923 if (next_ctrl.fma_write_unit != REG_WRITE_NONE) {
924 fprintf(fp, "{R%d, T0}, ", GetRegToWrite(next_ctrl.fma_write_unit, next_regs));
925 } else {
926 fprintf(fp, "T0, ");
927 }
928
929 switch (info.src_type) {
930 case FMA_ONE_SRC:
931 dump_src(fp, FMA.src0, regs, consts, true);
932 break;
933 case FMA_TWO_SRC:
934 dump_src(fp, FMA.src0, regs, consts, true);
935 fprintf(fp, ", ");
936 dump_src(fp, FMA.op & 0x7, regs, consts, true);
937 break;
938 case FMA_FADD:
939 case FMA_FMINMAX:
940 if (FMA.op & 0x10)
941 fprintf(fp, "-");
942 if (FMA.op & 0x200)
943 fprintf(fp, "abs(");
944 dump_src(fp, FMA.src0, regs, consts, true);
945 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
946 if (FMA.op & 0x200)
947 fprintf(fp, ")");
948 fprintf(fp, ", ");
949 if (FMA.op & 0x20)
950 fprintf(fp, "-");
951 if (FMA.op & 0x8)
952 fprintf(fp, "abs(");
953 dump_src(fp, FMA.op & 0x7, regs, consts, true);
954 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
955 if (FMA.op & 0x8)
956 fprintf(fp, ")");
957 break;
958 case FMA_FADD16:
959 case FMA_FMINMAX16: {
960 bool abs1 = FMA.op & 0x8;
961 bool abs2 = (FMA.op & 0x7) < FMA.src0;
962 if (FMA.op & 0x10)
963 fprintf(fp, "-");
964 if (abs1 || abs2)
965 fprintf(fp, "abs(");
966 dump_src(fp, FMA.src0, regs, consts, true);
967 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
968 if (abs1 || abs2)
969 fprintf(fp, ")");
970 fprintf(fp, ", ");
971 if (FMA.op & 0x20)
972 fprintf(fp, "-");
973 if (abs1 && abs2)
974 fprintf(fp, "abs(");
975 dump_src(fp, FMA.op & 0x7, regs, consts, true);
976 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
977 if (abs1 && abs2)
978 fprintf(fp, ")");
979 break;
980 }
981 case FMA_FCMP:
982 if (FMA.op & 0x200)
983 fprintf(fp, "abs(");
984 dump_src(fp, FMA.src0, regs, consts, true);
985 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
986 if (FMA.op & 0x200)
987 fprintf(fp, ")");
988 fprintf(fp, ", ");
989 if (FMA.op & 0x20)
990 fprintf(fp, "-");
991 if (FMA.op & 0x8)
992 fprintf(fp, "abs(");
993 dump_src(fp, FMA.op & 0x7, regs, consts, true);
994 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
995 if (FMA.op & 0x8)
996 fprintf(fp, ")");
997 break;
998 case FMA_FCMP16:
999 dump_src(fp, FMA.src0, regs, consts, true);
1000 // Note: this is kinda a guess, I haven't seen the blob set this to
1001 // anything other than the identity, but it matches FMA_TWO_SRCFmod16
1002 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
1003 fprintf(fp, ", ");
1004 dump_src(fp, FMA.op & 0x7, regs, consts, true);
1005 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
1006 break;
1007 case FMA_SHIFT_ADD64:
1008 dump_src(fp, FMA.src0, regs, consts, true);
1009 fprintf(fp, ", ");
1010 dump_src(fp, FMA.op & 0x7, regs, consts, true);
1011 fprintf(fp, ", ");
1012 fprintf(fp, "shift:%u", (FMA.op >> 3) & 0x7);
1013 break;
1014 case FMA_THREE_SRC:
1015 dump_src(fp, FMA.src0, regs, consts, true);
1016 fprintf(fp, ", ");
1017 dump_src(fp, FMA.op & 0x7, regs, consts, true);
1018 fprintf(fp, ", ");
1019 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
1020 break;
1021 case FMA_SHIFT: {
1022 struct bifrost_shift_fma shift;
1023 memcpy(&shift, &FMA, sizeof(shift));
1024
1025 dump_src(fp, shift.src0, regs, consts, true);
1026 fprintf(fp, ", ");
1027 dump_src(fp, shift.src1, regs, consts, true);
1028 fprintf(fp, ", ");
1029 dump_src(fp, shift.src2, regs, consts, true);
1030 break;
1031 }
1032 case FMA_FMA:
1033 if (FMA.op & (1 << 14))
1034 fprintf(fp, "-");
1035 if (FMA.op & (1 << 9))
1036 fprintf(fp, "abs(");
1037 dump_src(fp, FMA.src0, regs, consts, true);
1038 dump_fma_expand_src0(fp, (FMA.op >> 6) & 0x7);
1039 if (FMA.op & (1 << 9))
1040 fprintf(fp, ")");
1041 fprintf(fp, ", ");
1042 if (FMA.op & (1 << 16))
1043 fprintf(fp, "abs(");
1044 dump_src(fp, FMA.op & 0x7, regs, consts, true);
1045 dump_fma_expand_src1(fp, (FMA.op >> 6) & 0x7);
1046 if (FMA.op & (1 << 16))
1047 fprintf(fp, ")");
1048 fprintf(fp, ", ");
1049 if (FMA.op & (1 << 15))
1050 fprintf(fp, "-");
1051 if (FMA.op & (1 << 17))
1052 fprintf(fp, "abs(");
1053 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
1054 if (FMA.op & (1 << 17))
1055 fprintf(fp, ")");
1056 break;
1057 case FMA_FMA16:
1058 if (FMA.op & (1 << 14))
1059 fprintf(fp, "-");
1060 dump_src(fp, FMA.src0, regs, consts, true);
1061 dump_16swizzle(fp, (FMA.op >> 6) & 0x3);
1062 fprintf(fp, ", ");
1063 dump_src(fp, FMA.op & 0x7, regs, consts, true);
1064 dump_16swizzle(fp, (FMA.op >> 8) & 0x3);
1065 fprintf(fp, ", ");
1066 if (FMA.op & (1 << 15))
1067 fprintf(fp, "-");
1068 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
1069 dump_16swizzle(fp, (FMA.op >> 16) & 0x3);
1070 break;
1071 case FMA_CSEL4: {
1072 struct bifrost_csel4 csel;
1073 memcpy(&csel, &FMA, sizeof(csel));
1074 fprintf(fp, ".%s ", csel_cond_name(csel.cond));
1075
1076 dump_src(fp, csel.src0, regs, consts, true);
1077 fprintf(fp, ", ");
1078 dump_src(fp, csel.src1, regs, consts, true);
1079 fprintf(fp, ", ");
1080 dump_src(fp, csel.src2, regs, consts, true);
1081 fprintf(fp, ", ");
1082 dump_src(fp, csel.src3, regs, consts, true);
1083 break;
1084 }
1085 case FMA_FMA_MSCALE:
1086 if (FMA.op & (1 << 12))
1087 fprintf(fp, "abs(");
1088 dump_src(fp, FMA.src0, regs, consts, true);
1089 if (FMA.op & (1 << 12))
1090 fprintf(fp, ")");
1091 fprintf(fp, ", ");
1092 if (FMA.op & (1 << 13))
1093 fprintf(fp, "-");
1094 dump_src(fp, FMA.op & 0x7, regs, consts, true);
1095 fprintf(fp, ", ");
1096 if (FMA.op & (1 << 14))
1097 fprintf(fp, "-");
1098 dump_src(fp, (FMA.op >> 3) & 0x7, regs, consts, true);
1099 fprintf(fp, ", ");
1100 dump_src(fp, (FMA.op >> 6) & 0x7, regs, consts, true);
1101 break;
1102 }
1103 fprintf(fp, "\n");
1104 }
1105
1106 static const struct add_op_info add_op_infos[] = {
1107 { 0x00000, "MAX.f32", ADD_FMINMAX },
1108 { 0x02000, "MIN.f32", ADD_FMINMAX },
1109 { 0x04000, "ADD.f32", ADD_FADD },
1110 { 0x06000, "FCMP.GL", ADD_FCMP },
1111 { 0x07000, "FCMP.D3D", ADD_FCMP },
1112 { 0x07856, "F16_TO_I16", ADD_ONE_SRC },
1113 { 0x07857, "F16_TO_U16", ADD_ONE_SRC },
1114 { 0x078c0, "I16_TO_F16.XX", ADD_ONE_SRC },
1115 { 0x078c1, "U16_TO_F16.XX", ADD_ONE_SRC },
1116 { 0x078c8, "I16_TO_F16.YX", ADD_ONE_SRC },
1117 { 0x078c9, "U16_TO_F16.YX", ADD_ONE_SRC },
1118 { 0x078d0, "I16_TO_F16.XY", ADD_ONE_SRC },
1119 { 0x078d1, "U16_TO_F16.XY", ADD_ONE_SRC },
1120 { 0x078d8, "I16_TO_F16.YY", ADD_ONE_SRC },
1121 { 0x078d9, "U16_TO_F16.YY", ADD_ONE_SRC },
1122 { 0x07936, "F32_TO_I32", ADD_ONE_SRC },
1123 { 0x07937, "F32_TO_U32", ADD_ONE_SRC },
1124 { 0x07978, "I32_TO_F32", ADD_ONE_SRC },
1125 { 0x07979, "U32_TO_F32", ADD_ONE_SRC },
1126 { 0x07998, "I16_TO_I32.X", ADD_ONE_SRC },
1127 { 0x07999, "U16_TO_U32.X", ADD_ONE_SRC },
1128 { 0x0799a, "I16_TO_I32.Y", ADD_ONE_SRC },
1129 { 0x0799b, "U16_TO_U32.Y", ADD_ONE_SRC },
1130 { 0x0799c, "I16_TO_F32.X", ADD_ONE_SRC },
1131 { 0x0799d, "U16_TO_F32.X", ADD_ONE_SRC },
1132 { 0x0799e, "I16_TO_F32.Y", ADD_ONE_SRC },
1133 { 0x0799f, "U16_TO_F32.Y", ADD_ONE_SRC },
1134 { 0x079a2, "F16_TO_F32.X", ADD_ONE_SRC },
1135 { 0x079a3, "F16_TO_F32.Y", ADD_ONE_SRC },
1136 { 0x07b2b, "SWZ.YX.v2i16", ADD_ONE_SRC },
1137 { 0x07b2c, "NOP", ADD_ONE_SRC },
1138 { 0x07b29, "SWZ.XX.v2i16", ADD_ONE_SRC },
1139 { 0x07b2d, "MOV", ADD_ONE_SRC },
1140 { 0x07b2f, "SWZ.YY.v2i16", ADD_ONE_SRC },
1141 { 0x07b65, "FRCP_FREXPM", ADD_ONE_SRC },
1142 { 0x07b75, "FSQRT_FREXPM", ADD_ONE_SRC },
1143 { 0x07b8d, "FRCP_FREXPE", ADD_ONE_SRC },
1144 { 0x07ba5, "FSQRT_FREXPE", ADD_ONE_SRC },
1145 { 0x07bad, "FRSQ_FREXPE", ADD_ONE_SRC },
1146 { 0x07bc5, "FLOG_FREXPE", ADD_ONE_SRC },
1147 { 0x07d45, "CEIL", ADD_ONE_SRC },
1148 { 0x07d85, "FLOOR", ADD_ONE_SRC },
1149 { 0x07dc5, "TRUNC", ADD_ONE_SRC },
1150 { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC },
1151 { 0x08000, "LD_ATTR.f16", ADD_LOAD_ATTR, true },
1152 { 0x08100, "LD_ATTR.v2f16", ADD_LOAD_ATTR, true },
1153 { 0x08200, "LD_ATTR.v3f16", ADD_LOAD_ATTR, true },
1154 { 0x08300, "LD_ATTR.v4f16", ADD_LOAD_ATTR, true },
1155 { 0x08400, "LD_ATTR.f32", ADD_LOAD_ATTR, true },
1156 { 0x08500, "LD_ATTR.v3f32", ADD_LOAD_ATTR, true },
1157 { 0x08600, "LD_ATTR.v3f32", ADD_LOAD_ATTR, true },
1158 { 0x08700, "LD_ATTR.v4f32", ADD_LOAD_ATTR, true },
1159 { 0x08800, "LD_ATTR.i32", ADD_LOAD_ATTR, true },
1160 { 0x08900, "LD_ATTR.v3i32", ADD_LOAD_ATTR, true },
1161 { 0x08a00, "LD_ATTR.v3i32", ADD_LOAD_ATTR, true },
1162 { 0x08b00, "LD_ATTR.v4i32", ADD_LOAD_ATTR, true },
1163 { 0x08c00, "LD_ATTR.u32", ADD_LOAD_ATTR, true },
1164 { 0x08d00, "LD_ATTR.v3u32", ADD_LOAD_ATTR, true },
1165 { 0x08e00, "LD_ATTR.v3u32", ADD_LOAD_ATTR, true },
1166 { 0x08f00, "LD_ATTR.v4u32", ADD_LOAD_ATTR, true },
1167 { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP, true },
1168 { 0x0b000, "TEX", ADD_TEX_COMPACT, true },
1169 { 0x0c188, "LOAD.i32", ADD_TWO_SRC, true },
1170 { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC, true },
1171 { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1172 { 0x0c1c8, "LOAD.v2i32", ADD_TWO_SRC, true },
1173 { 0x0c1e0, "LD_UBO.v2i32", ADD_TWO_SRC, true },
1174 { 0x0c1f8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1175 { 0x0c208, "LOAD.v4i32", ADD_TWO_SRC, true },
1176 { 0x0c220, "LD_UBO.v4i32", ADD_TWO_SRC, true },
1177 { 0x0c238, "LD_SCRATCH.v4i32", ADD_TWO_SRC, true },
1178 { 0x0c248, "STORE.v4i32", ADD_TWO_SRC, true },
1179 { 0x0c278, "ST_SCRATCH.v4i32", ADD_TWO_SRC, true },
1180 { 0x0c588, "STORE.i32", ADD_TWO_SRC, true },
1181 { 0x0c5b8, "ST_SCRATCH.i32", ADD_TWO_SRC, true },
1182 { 0x0c5c8, "STORE.v2i32", ADD_TWO_SRC, true },
1183 { 0x0c5f8, "ST_SCRATCH.v2i32", ADD_TWO_SRC, true },
1184 { 0x0c648, "LOAD.u16", ADD_TWO_SRC, true }, // zero-extends
1185 { 0x0ca88, "LOAD.v3i32", ADD_TWO_SRC, true },
1186 { 0x0caa0, "LD_UBO.v3i32", ADD_TWO_SRC, true },
1187 { 0x0cab8, "LD_SCRATCH.v3i32", ADD_TWO_SRC, true },
1188 { 0x0cb88, "STORE.v3i32", ADD_TWO_SRC, true },
1189 { 0x0cbb8, "ST_SCRATCH.v3i32", ADD_TWO_SRC, true },
1190 { 0x0cc00, "FRCP_FAST.f32", ADD_ONE_SRC },
1191 { 0x0cc20, "FRSQ_FAST.f32", ADD_ONE_SRC },
1192 { 0x0ce00, "FRCP_TABLE", ADD_ONE_SRC },
1193 { 0x0ce10, "FRCP_FAST.f16.X", ADD_ONE_SRC },
1194 { 0x0ce20, "FRSQ_TABLE", ADD_ONE_SRC },
1195 { 0x0ce30, "FRCP_FAST.f16.Y", ADD_ONE_SRC },
1196 { 0x0ce50, "FRSQ_FAST.f16.X", ADD_ONE_SRC },
1197 { 0x0ce60, "FRCP_APPROX", ADD_ONE_SRC },
1198 { 0x0ce70, "FRSQ_FAST.f16.Y", ADD_ONE_SRC },
1199 { 0x0cf40, "ATAN_ASSIST", ADD_TWO_SRC },
1200 { 0x0cf48, "ATAN_TABLE", ADD_TWO_SRC },
1201 { 0x0cf50, "SIN_TABLE", ADD_ONE_SRC },
1202 { 0x0cf51, "COS_TABLE", ADD_ONE_SRC },
1203 { 0x0cf58, "EXP_TABLE", ADD_ONE_SRC },
1204 { 0x0cf60, "FLOG2_TABLE", ADD_ONE_SRC },
1205 { 0x0cf64, "FLOGE_TABLE", ADD_ONE_SRC },
1206 { 0x0d000, "BRANCH", ADD_BRANCH },
1207 { 0x0e8c0, "MUX", ADD_THREE_SRC },
1208 { 0x0e9b0, "ATAN_LDEXP.Y.f32", ADD_TWO_SRC },
1209 { 0x0e9b8, "ATAN_LDEXP.X.f32", ADD_TWO_SRC },
1210 { 0x0ea60, "SEL.XX.i16", ADD_TWO_SRC },
1211 { 0x0ea70, "SEL.XY.i16", ADD_TWO_SRC },
1212 { 0x0ea68, "SEL.YX.i16", ADD_TWO_SRC },
1213 { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC },
1214 { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC },
1215 { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC }, // src0 > src1 ? 1 : 0
1216 { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC },
1217 { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC },
1218 { 0x0f658, "UCMP.GL.GE", ADD_TWO_SRC },
1219 { 0x0f660, "ICMP.GL.EQ", ADD_TWO_SRC },
1220 { 0x0f669, "ICMP.GL.NEQ", ADD_TWO_SRC },
1221 { 0x0f6c0, "ICMP.D3D.GT", ADD_TWO_SRC }, // src0 > src1 ? ~0 : 0
1222 { 0x0f6c8, "ICMP.D3D.GE", ADD_TWO_SRC },
1223 { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC },
1224 { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC },
1225 { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC },
1226 { 0x10000, "MAX.v2f16", ADD_FMINMAX16 },
1227 { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale },
1228 { 0x12000, "MIN.v2f16", ADD_FMINMAX16 },
1229 { 0x14000, "ADD.v2f16", ADD_FADD16 },
1230 { 0x17000, "FCMP.D3D", ADD_FCMP16 },
1231 { 0x178c0, "ADD.i32", ADD_TWO_SRC },
1232 { 0x17900, "ADD.v2i16", ADD_TWO_SRC },
1233 { 0x17ac0, "SUB.i32", ADD_TWO_SRC },
1234 { 0x17c10, "ADDC.i32", ADD_TWO_SRC }, // adds src0 to the bottom bit of src1
1235 { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC },
1236 { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC },
1237 { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC },
1238 { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC },
1239 { 0x18000, "LD_VAR_ADDR.f16", ADD_VARYING_ADDRESS, true },
1240 { 0x18100, "LD_VAR_ADDR.f32", ADD_VARYING_ADDRESS, true },
1241 { 0x18200, "LD_VAR_ADDR.i32", ADD_VARYING_ADDRESS, true },
1242 { 0x18300, "LD_VAR_ADDR.u32", ADD_VARYING_ADDRESS, true },
1243 { 0x19181, "DISCARD.FEQ.f32", ADD_TWO_SRC, true },
1244 { 0x19189, "DISCARD.FNE.f32", ADD_TWO_SRC, true },
1245 { 0x1918C, "DISCARD.GL.f32", ADD_TWO_SRC, true }, /* Consumes ICMP.GL/etc with fixed 0 argument */
1246 { 0x19190, "DISCARD.FLE.f32", ADD_TWO_SRC, true },
1247 { 0x19198, "DISCARD.FLT.f32", ADD_TWO_SRC, true },
1248 { 0x191e8, "ATEST.f32", ADD_TWO_SRC, true },
1249 { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC, true },
1250 { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC, true },
1251 { 0x19300, "ST_VAR.v1", ADD_THREE_SRC, true },
1252 { 0x19340, "ST_VAR.v2", ADD_THREE_SRC, true },
1253 { 0x19380, "ST_VAR.v3", ADD_THREE_SRC, true },
1254 { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC, true },
1255 { 0x1952c, "BLEND", ADD_BLENDING, true },
1256 { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP, true },
1257 { 0x1ae60, "TEX", ADD_TEX, true },
1258 { 0x1c000, "RSHIFT_NAND.i32", ADD_THREE_SRC },
1259 { 0x1c300, "RSHIFT_OR.i32", ADD_THREE_SRC },
1260 { 0x1c400, "RSHIFT_AND.i32", ADD_THREE_SRC },
1261 { 0x1c700, "RSHIFT_NOR.i32", ADD_THREE_SRC },
1262 { 0x1c800, "LSHIFT_NAND.i32", ADD_THREE_SRC },
1263 { 0x1cb00, "LSHIFT_OR.i32", ADD_THREE_SRC },
1264 { 0x1cc00, "LSHIFT_AND.i32", ADD_THREE_SRC },
1265 { 0x1cf00, "LSHIFT_NOR.i32", ADD_THREE_SRC },
1266 { 0x1d000, "RSHIFT_XOR.i32", ADD_THREE_SRC },
1267 { 0x1d100, "RSHIFT_XNOR.i32", ADD_THREE_SRC },
1268 { 0x1d200, "LSHIFT_XOR.i32", ADD_THREE_SRC },
1269 { 0x1d300, "LSHIFT_XNOR.i32", ADD_THREE_SRC },
1270 { 0x1d400, "LSHIFT_ADD.i32", ADD_THREE_SRC },
1271 { 0x1d500, "LSHIFT_SUB.i32", ADD_THREE_SRC },
1272 { 0x1d500, "LSHIFT_RSUB.i32", ADD_THREE_SRC },
1273 { 0x1d700, "RSHIFT_ADD.i32", ADD_THREE_SRC },
1274 { 0x1d800, "RSHIFT_SUB.i32", ADD_THREE_SRC },
1275 { 0x1d900, "RSHIFT_RSUB.i32", ADD_THREE_SRC },
1276 { 0x1da00, "ARSHIFT_ADD.i32", ADD_THREE_SRC },
1277 { 0x1db00, "ARSHIFT_SUB.i32", ADD_THREE_SRC },
1278 { 0x1dc00, "ARSHIFT_RSUB.i32", ADD_THREE_SRC },
1279 { 0x1dd18, "OR.i32", ADD_TWO_SRC },
1280 { 0x1dd20, "AND.i32", ADD_TWO_SRC },
1281 { 0x1dd60, "LSHIFT.i32", ADD_TWO_SRC },
1282 { 0x1dd50, "XOR.i32", ADD_TWO_SRC },
1283 { 0x1dd80, "RSHIFT.i32", ADD_TWO_SRC },
1284 { 0x1dda0, "ARSHIFT.i32", ADD_TWO_SRC },
1285 };
1286
1287 static struct add_op_info find_add_op_info(unsigned op)
1288 {
1289 for (unsigned i = 0; i < ARRAY_SIZE(add_op_infos); i++) {
1290 unsigned opCmp = ~0;
1291 switch (add_op_infos[i].src_type) {
1292 case ADD_ONE_SRC:
1293 case ADD_BLENDING:
1294 opCmp = op;
1295 break;
1296 case ADD_TWO_SRC:
1297 opCmp = op & ~0x7;
1298 break;
1299 case ADD_THREE_SRC:
1300 opCmp = op & ~0x3f;
1301 break;
1302 case ADD_TEX:
1303 opCmp = op & ~0xf;
1304 break;
1305 case ADD_FADD:
1306 case ADD_FMINMAX:
1307 case ADD_FADD16:
1308 opCmp = op & ~0x1fff;
1309 break;
1310 case ADD_FMINMAX16:
1311 case ADD_FADDMscale:
1312 opCmp = op & ~0xfff;
1313 break;
1314 case ADD_FCMP:
1315 case ADD_FCMP16:
1316 opCmp = op & ~0x7ff;
1317 break;
1318 case ADD_TEX_COMPACT:
1319 opCmp = op & ~0x3ff;
1320 break;
1321 case ADD_VARYING_INTERP:
1322 opCmp = op & ~0x7ff;
1323 break;
1324 case ADD_VARYING_ADDRESS:
1325 opCmp = op & ~0xff;
1326 break;
1327 case ADD_LOAD_ATTR:
1328 opCmp = op & ~0x7f;
1329 break;
1330 case ADD_BRANCH:
1331 opCmp = op & ~0xfff;
1332 break;
1333 default:
1334 opCmp = ~0;
1335 break;
1336 }
1337 if (add_op_infos[i].op == opCmp)
1338 return add_op_infos[i];
1339 }
1340
1341 struct add_op_info info;
1342 snprintf(info.name, sizeof(info.name), "op%04x", op);
1343 info.op = op;
1344 info.src_type = ADD_TWO_SRC;
1345 info.has_data_reg = true;
1346 return info;
1347 }
1348
1349 static void dump_add(FILE *fp, uint64_t word, struct bifrost_regs regs,
1350 struct bifrost_regs next_regs, uint64_t *consts,
1351 unsigned data_reg, unsigned offset, bool verbose)
1352 {
1353 if (verbose) {
1354 fprintf(fp, "# ADD: %016" PRIx64 "\n", word);
1355 }
1356 struct bifrost_add_inst ADD;
1357 memcpy((char *) &ADD, (char *) &word, sizeof(ADD));
1358 struct add_op_info info = find_add_op_info(ADD.op);
1359
1360 fprintf(fp, "%s", info.name);
1361
1362 // float16 seems like it doesn't support output modifiers
1363 if (info.src_type == ADD_FADD || info.src_type == ADD_FMINMAX) {
1364 // output modifiers
1365 dump_output_mod(fp, bits(ADD.op, 8, 10));
1366 if (info.src_type == ADD_FADD)
1367 dump_round_mode(fp, bits(ADD.op, 10, 12));
1368 else
1369 dump_minmax_mode(fp, bits(ADD.op, 10, 12));
1370 } else if (info.src_type == ADD_FCMP || info.src_type == ADD_FCMP16) {
1371 dump_fcmp(fp, bits(ADD.op, 3, 6));
1372 if (info.src_type == ADD_FCMP)
1373 fprintf(fp, ".f32");
1374 else
1375 fprintf(fp, ".v2f16");
1376 } else if (info.src_type == ADD_FADDMscale) {
1377 switch ((ADD.op >> 6) & 0x7) {
1378 case 0:
1379 break;
1380 // causes GPU hangs on G71
1381 case 1:
1382 fprintf(fp, ".invalid");
1383 break;
1384 // Same as usual outmod value.
1385 case 2:
1386 fprintf(fp, ".clamp_0_1");
1387 break;
1388 // If src0 is infinite or NaN, flush it to zero so that the other
1389 // source is passed through unmodified.
1390 case 3:
1391 fprintf(fp, ".flush_src0_inf_nan");
1392 break;
1393 // Vice versa.
1394 case 4:
1395 fprintf(fp, ".flush_src1_inf_nan");
1396 break;
1397 // Every other case seems to behave the same as the above?
1398 default:
1399 fprintf(fp, ".unk%d", (ADD.op >> 6) & 0x7);
1400 break;
1401 }
1402 } else if (info.src_type == ADD_VARYING_INTERP) {
1403 if (ADD.op & 0x200)
1404 fprintf(fp, ".reuse");
1405 if (ADD.op & 0x400)
1406 fprintf(fp, ".flat");
1407 switch ((ADD.op >> 7) & 0x3) {
1408 case 0:
1409 fprintf(fp, ".per_frag");
1410 break;
1411 case 1:
1412 fprintf(fp, ".centroid");
1413 break;
1414 case 2:
1415 break;
1416 case 3:
1417 fprintf(fp, ".explicit");
1418 break;
1419 }
1420 fprintf(fp, ".v%d", ((ADD.op >> 5) & 0x3) + 1);
1421 } else if (info.src_type == ADD_BRANCH) {
1422 enum branch_code branchCode = (enum branch_code) ((ADD.op >> 6) & 0x3f);
1423 if (branchCode == BR_ALWAYS) {
1424 // unconditional branch
1425 } else {
1426 enum branch_cond cond = (enum branch_cond) ((ADD.op >> 6) & 0x7);
1427 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1428 bool portSwapped = (ADD.op & 0x7) < ADD.src0;
1429 // See the comment in branch_bit_size
1430 if (size == BR_SIZE_16YX0)
1431 portSwapped = true;
1432 if (size == BR_SIZE_16YX1)
1433 portSwapped = false;
1434 // These sizes are only for floating point comparisons, so the
1435 // non-floating-point comparisons are reused to encode the flipped
1436 // versions.
1437 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y)
1438 portSwapped = false;
1439 // There's only one argument, so we reuse the extra argument to
1440 // encode this.
1441 if (size == BR_SIZE_ZERO)
1442 portSwapped = !(ADD.op & 1);
1443
1444 switch (cond) {
1445 case BR_COND_LT:
1446 if (portSwapped)
1447 fprintf(fp, ".LT.u");
1448 else
1449 fprintf(fp, ".LT.i");
1450 break;
1451 case BR_COND_LE:
1452 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y) {
1453 fprintf(fp, ".UNE.f");
1454 } else {
1455 if (portSwapped)
1456 fprintf(fp, ".LE.u");
1457 else
1458 fprintf(fp, ".LE.i");
1459 }
1460 break;
1461 case BR_COND_GT:
1462 if (portSwapped)
1463 fprintf(fp, ".GT.u");
1464 else
1465 fprintf(fp, ".GT.i");
1466 break;
1467 case BR_COND_GE:
1468 if (portSwapped)
1469 fprintf(fp, ".GE.u");
1470 else
1471 fprintf(fp, ".GE.i");
1472 break;
1473 case BR_COND_EQ:
1474 if (portSwapped)
1475 fprintf(fp, ".NE.i");
1476 else
1477 fprintf(fp, ".EQ.i");
1478 break;
1479 case BR_COND_OEQ:
1480 if (portSwapped)
1481 fprintf(fp, ".UNE.f");
1482 else
1483 fprintf(fp, ".OEQ.f");
1484 break;
1485 case BR_COND_OGT:
1486 if (portSwapped)
1487 fprintf(fp, ".OGT.unk.f");
1488 else
1489 fprintf(fp, ".OGT.f");
1490 break;
1491 case BR_COND_OLT:
1492 if (portSwapped)
1493 fprintf(fp, ".OLT.unk.f");
1494 else
1495 fprintf(fp, ".OLT.f");
1496 break;
1497 }
1498 switch (size) {
1499 case BR_SIZE_32:
1500 case BR_SIZE_32_AND_16X:
1501 case BR_SIZE_32_AND_16Y:
1502 fprintf(fp, "32");
1503 break;
1504 case BR_SIZE_16XX:
1505 case BR_SIZE_16YY:
1506 case BR_SIZE_16YX0:
1507 case BR_SIZE_16YX1:
1508 fprintf(fp, "16");
1509 break;
1510 case BR_SIZE_ZERO: {
1511 unsigned ctrl = (ADD.op >> 1) & 0x3;
1512 if (ctrl == 0)
1513 fprintf(fp, "32.Z");
1514 else
1515 fprintf(fp, "16.Z");
1516 break;
1517 }
1518 }
1519 }
1520 }
1521 fprintf(fp, " ");
1522
1523 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(fp, next_regs);
1524 if (next_ctrl.add_write_unit != REG_WRITE_NONE) {
1525 fprintf(fp, "{R%d, T1}, ", GetRegToWrite(next_ctrl.add_write_unit, next_regs));
1526 } else {
1527 fprintf(fp, "T1, ");
1528 }
1529
1530 switch (info.src_type) {
1531 case ADD_BLENDING:
1532 // Note: in this case, regs.uniform_const == location | 0x8
1533 // This probably means we can't load uniforms or immediates in the
1534 // same instruction. This re-uses the encoding that normally means
1535 // "disabled", where the low 4 bits are ignored. Perhaps the extra
1536 // 0x8 or'd in indicates this is happening.
1537 fprintf(fp, "location:%d, ", regs.uniform_const & 0x7);
1538 // fallthrough
1539 case ADD_ONE_SRC:
1540 dump_src(fp, ADD.src0, regs, consts, false);
1541 break;
1542 case ADD_TEX:
1543 case ADD_TEX_COMPACT: {
1544 int tex_index;
1545 int sampler_index;
1546 bool dualTex = false;
1547 if (info.src_type == ADD_TEX_COMPACT) {
1548 tex_index = (ADD.op >> 3) & 0x7;
1549 sampler_index = (ADD.op >> 7) & 0x7;
1550 bool unknown = (ADD.op & 0x40);
1551 // TODO: figure out if the unknown bit is ever 0
1552 if (!unknown)
1553 fprintf(fp, "unknown ");
1554 } else {
1555 uint64_t constVal = get_const(consts, regs);
1556 uint32_t controlBits = (ADD.op & 0x8) ? (constVal >> 32) : constVal;
1557 struct bifrost_tex_ctrl ctrl;
1558 memcpy((char *) &ctrl, (char *) &controlBits, sizeof(ctrl));
1559
1560 // TODO: figure out what actually triggers dual-tex
1561 if (ctrl.result_type == 9) {
1562 struct bifrost_dual_tex_ctrl dualCtrl;
1563 memcpy((char *) &dualCtrl, (char *) &controlBits, sizeof(ctrl));
1564 fprintf(fp, "(dualtex) tex0:%d samp0:%d tex1:%d samp1:%d ",
1565 dualCtrl.tex_index0, dualCtrl.sampler_index0,
1566 dualCtrl.tex_index1, dualCtrl.sampler_index1);
1567 if (dualCtrl.unk0 != 3)
1568 fprintf(fp, "unk:%d ", dualCtrl.unk0);
1569 dualTex = true;
1570 } else {
1571 if (ctrl.no_merge_index) {
1572 tex_index = ctrl.tex_index;
1573 sampler_index = ctrl.sampler_index;
1574 } else {
1575 tex_index = sampler_index = ctrl.tex_index;
1576 unsigned unk = ctrl.sampler_index >> 2;
1577 if (unk != 3)
1578 fprintf(fp, "unk:%d ", unk);
1579 if (ctrl.sampler_index & 1)
1580 tex_index = -1;
1581 if (ctrl.sampler_index & 2)
1582 sampler_index = -1;
1583 }
1584
1585 if (ctrl.unk0 != 3)
1586 fprintf(fp, "unk0:%d ", ctrl.unk0);
1587 if (ctrl.unk1)
1588 fprintf(fp, "unk1 ");
1589 if (ctrl.unk2 != 0xf)
1590 fprintf(fp, "unk2:%x ", ctrl.unk2);
1591
1592 switch (ctrl.result_type) {
1593 case 0x4:
1594 fprintf(fp, "f32 ");
1595 break;
1596 case 0xe:
1597 fprintf(fp, "i32 ");
1598 break;
1599 case 0xf:
1600 fprintf(fp, "u32 ");
1601 break;
1602 default:
1603 fprintf(fp, "unktype(%x) ", ctrl.result_type);
1604 }
1605
1606 switch (ctrl.tex_type) {
1607 case 0:
1608 fprintf(fp, "cube ");
1609 break;
1610 case 1:
1611 fprintf(fp, "buffer ");
1612 break;
1613 case 2:
1614 fprintf(fp, "2D ");
1615 break;
1616 case 3:
1617 fprintf(fp, "3D ");
1618 break;
1619 }
1620
1621 if (ctrl.is_shadow)
1622 fprintf(fp, "shadow ");
1623 if (ctrl.is_array)
1624 fprintf(fp, "array ");
1625
1626 if (!ctrl.filter) {
1627 if (ctrl.calc_gradients) {
1628 int comp = (controlBits >> 20) & 0x3;
1629 fprintf(fp, "txg comp:%d ", comp);
1630 } else {
1631 fprintf(fp, "txf ");
1632 }
1633 } else {
1634 if (!ctrl.not_supply_lod) {
1635 if (ctrl.compute_lod)
1636 fprintf(fp, "lod_bias ");
1637 else
1638 fprintf(fp, "lod ");
1639 }
1640
1641 if (!ctrl.calc_gradients)
1642 fprintf(fp, "grad ");
1643 }
1644
1645 if (ctrl.texel_offset)
1646 fprintf(fp, "offset ");
1647 }
1648 }
1649
1650 if (!dualTex) {
1651 if (tex_index == -1)
1652 fprintf(fp, "tex:indirect ");
1653 else
1654 fprintf(fp, "tex:%d ", tex_index);
1655
1656 if (sampler_index == -1)
1657 fprintf(fp, "samp:indirect ");
1658 else
1659 fprintf(fp, "samp:%d ", sampler_index);
1660 }
1661 break;
1662 }
1663 case ADD_VARYING_INTERP: {
1664 unsigned addr = ADD.op & 0x1f;
1665 if (addr < 0b10100) {
1666 // direct addr
1667 fprintf(fp, "%d", addr);
1668 } else if (addr < 0b11000) {
1669 if (addr == 22)
1670 fprintf(fp, "fragw");
1671 else if (addr == 23)
1672 fprintf(fp, "fragz");
1673 else
1674 fprintf(fp, "unk%d", addr);
1675 } else {
1676 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1677 }
1678 fprintf(fp, ", ");
1679 dump_src(fp, ADD.src0, regs, consts, false);
1680 break;
1681 }
1682 case ADD_VARYING_ADDRESS: {
1683 dump_src(fp, ADD.src0, regs, consts, false);
1684 fprintf(fp, ", ");
1685 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1686 fprintf(fp, ", ");
1687 unsigned location = (ADD.op >> 3) & 0x1f;
1688 if (location < 16) {
1689 fprintf(fp, "location:%d", location);
1690 } else if (location == 20) {
1691 fprintf(fp, "location:%u", (uint32_t) get_const(consts, regs));
1692 } else if (location == 21) {
1693 fprintf(fp, "location:%u", (uint32_t) (get_const(consts, regs) >> 32));
1694 } else {
1695 fprintf(fp, "location:%d(unk)", location);
1696 }
1697 break;
1698 }
1699 case ADD_LOAD_ATTR:
1700 fprintf(fp, "location:%d, ", (ADD.op >> 3) & 0xf);
1701 case ADD_TWO_SRC:
1702 dump_src(fp, ADD.src0, regs, consts, false);
1703 fprintf(fp, ", ");
1704 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1705 break;
1706 case ADD_THREE_SRC:
1707 dump_src(fp, ADD.src0, regs, consts, false);
1708 fprintf(fp, ", ");
1709 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1710 fprintf(fp, ", ");
1711 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1712 break;
1713 case ADD_FADD:
1714 case ADD_FMINMAX:
1715 if (ADD.op & 0x10)
1716 fprintf(fp, "-");
1717 if (ADD.op & 0x1000)
1718 fprintf(fp, "abs(");
1719 dump_src(fp, ADD.src0, regs, consts, false);
1720 switch ((ADD.op >> 6) & 0x3) {
1721 case 3:
1722 fprintf(fp, ".x");
1723 break;
1724 default:
1725 break;
1726 }
1727 if (ADD.op & 0x1000)
1728 fprintf(fp, ")");
1729 fprintf(fp, ", ");
1730 if (ADD.op & 0x20)
1731 fprintf(fp, "-");
1732 if (ADD.op & 0x8)
1733 fprintf(fp, "abs(");
1734 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1735 switch ((ADD.op >> 6) & 0x3) {
1736 case 1:
1737 case 3:
1738 fprintf(fp, ".x");
1739 break;
1740 case 2:
1741 fprintf(fp, ".y");
1742 break;
1743 case 0:
1744 break;
1745 default:
1746 fprintf(fp, ".unk");
1747 break;
1748 }
1749 if (ADD.op & 0x8)
1750 fprintf(fp, ")");
1751 break;
1752 case ADD_FADD16:
1753 if (ADD.op & 0x10)
1754 fprintf(fp, "-");
1755 if (ADD.op & 0x1000)
1756 fprintf(fp, "abs(");
1757 dump_src(fp, ADD.src0, regs, consts, false);
1758 if (ADD.op & 0x1000)
1759 fprintf(fp, ")");
1760 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1761 fprintf(fp, ", ");
1762 if (ADD.op & 0x20)
1763 fprintf(fp, "-");
1764 if (ADD.op & 0x8)
1765 fprintf(fp, "abs(");
1766 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1767 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1768 if (ADD.op & 0x8)
1769 fprintf(fp, ")");
1770 break;
1771 case ADD_FMINMAX16: {
1772 bool abs1 = ADD.op & 0x8;
1773 bool abs2 = (ADD.op & 0x7) < ADD.src0;
1774 if (ADD.op & 0x10)
1775 fprintf(fp, "-");
1776 if (abs1 || abs2)
1777 fprintf(fp, "abs(");
1778 dump_src(fp, ADD.src0, regs, consts, false);
1779 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1780 if (abs1 || abs2)
1781 fprintf(fp, ")");
1782 fprintf(fp, ", ");
1783 if (ADD.op & 0x20)
1784 fprintf(fp, "-");
1785 if (abs1 && abs2)
1786 fprintf(fp, "abs(");
1787 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1788 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1789 if (abs1 && abs2)
1790 fprintf(fp, ")");
1791 break;
1792 }
1793 case ADD_FADDMscale: {
1794 if (ADD.op & 0x400)
1795 fprintf(fp, "-");
1796 if (ADD.op & 0x200)
1797 fprintf(fp, "abs(");
1798 dump_src(fp, ADD.src0, regs, consts, false);
1799 if (ADD.op & 0x200)
1800 fprintf(fp, ")");
1801
1802 fprintf(fp, ", ");
1803
1804 if (ADD.op & 0x800)
1805 fprintf(fp, "-");
1806 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1807
1808 fprintf(fp, ", ");
1809
1810 dump_src(fp, (ADD.op >> 3) & 0x7, regs, consts, false);
1811 break;
1812 }
1813 case ADD_FCMP:
1814 if (ADD.op & 0x400) {
1815 fprintf(fp, "-");
1816 }
1817 if (ADD.op & 0x100) {
1818 fprintf(fp, "abs(");
1819 }
1820 dump_src(fp, ADD.src0, regs, consts, false);
1821 switch ((ADD.op >> 6) & 0x3) {
1822 case 3:
1823 fprintf(fp, ".x");
1824 break;
1825 default:
1826 break;
1827 }
1828 if (ADD.op & 0x100) {
1829 fprintf(fp, ")");
1830 }
1831 fprintf(fp, ", ");
1832 if (ADD.op & 0x200) {
1833 fprintf(fp, "abs(");
1834 }
1835 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1836 switch ((ADD.op >> 6) & 0x3) {
1837 case 1:
1838 case 3:
1839 fprintf(fp, ".x");
1840 break;
1841 case 2:
1842 fprintf(fp, ".y");
1843 break;
1844 case 0:
1845 break;
1846 default:
1847 fprintf(fp, ".unk");
1848 break;
1849 }
1850 if (ADD.op & 0x200) {
1851 fprintf(fp, ")");
1852 }
1853 break;
1854 case ADD_FCMP16:
1855 dump_src(fp, ADD.src0, regs, consts, false);
1856 dump_16swizzle(fp, (ADD.op >> 6) & 0x3);
1857 fprintf(fp, ", ");
1858 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1859 dump_16swizzle(fp, (ADD.op >> 8) & 0x3);
1860 break;
1861 case ADD_BRANCH: {
1862 enum branch_code code = (enum branch_code) ((ADD.op >> 6) & 0x3f);
1863 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1864 if (code != BR_ALWAYS) {
1865 dump_src(fp, ADD.src0, regs, consts, false);
1866 switch (size) {
1867 case BR_SIZE_16XX:
1868 fprintf(fp, ".x");
1869 break;
1870 case BR_SIZE_16YY:
1871 case BR_SIZE_16YX0:
1872 case BR_SIZE_16YX1:
1873 fprintf(fp, ".y");
1874 break;
1875 case BR_SIZE_ZERO: {
1876 unsigned ctrl = (ADD.op >> 1) & 0x3;
1877 switch (ctrl) {
1878 case 1:
1879 fprintf(fp, ".y");
1880 break;
1881 case 2:
1882 fprintf(fp, ".x");
1883 break;
1884 default:
1885 break;
1886 }
1887 }
1888 default:
1889 break;
1890 }
1891 fprintf(fp, ", ");
1892 }
1893 if (code != BR_ALWAYS && size != BR_SIZE_ZERO) {
1894 dump_src(fp, ADD.op & 0x7, regs, consts, false);
1895 switch (size) {
1896 case BR_SIZE_16XX:
1897 case BR_SIZE_16YX0:
1898 case BR_SIZE_16YX1:
1899 case BR_SIZE_32_AND_16X:
1900 fprintf(fp, ".x");
1901 break;
1902 case BR_SIZE_16YY:
1903 case BR_SIZE_32_AND_16Y:
1904 fprintf(fp, ".y");
1905 break;
1906 default:
1907 break;
1908 }
1909 fprintf(fp, ", ");
1910 }
1911 // I haven't had the chance to test if this actually specifies the
1912 // branch offset, since I couldn't get it to produce values other
1913 // than 5 (uniform/const high), but these three bits are always
1914 // consistent across branch instructions, so it makes sense...
1915 int offsetSrc = (ADD.op >> 3) & 0x7;
1916 if (offsetSrc == 4 || offsetSrc == 5) {
1917 // If the offset is known/constant, we can decode it
1918 uint32_t raw_offset;
1919 if (offsetSrc == 4)
1920 raw_offset = get_const(consts, regs);
1921 else
1922 raw_offset = get_const(consts, regs) >> 32;
1923 // The high 4 bits are flags, while the rest is the
1924 // twos-complement offset in bytes (here we convert to
1925 // clauses).
1926 int32_t branch_offset = ((int32_t) raw_offset << 4) >> 8;
1927
1928 // If high4 is the high 4 bits of the last 64-bit constant,
1929 // this is calculated as (high4 + 4) & 0xf, or 0 if the branch
1930 // offset itself is the last constant. Not sure if this is
1931 // actually used, or just garbage in unused bits, but in any
1932 // case, we can just ignore it here since it's redundant. Note
1933 // that if there is any padding, this will be 4 since the
1934 // padding counts as the last constant.
1935 unsigned flags = raw_offset >> 28;
1936 (void) flags;
1937
1938 // Note: the offset is in bytes, relative to the beginning of the
1939 // current clause, so a zero offset would be a loop back to the
1940 // same clause (annoyingly different from Midgard).
1941 fprintf(fp, "clause_%d", offset + branch_offset);
1942 } else {
1943 dump_src(fp, offsetSrc, regs, consts, false);
1944 }
1945 }
1946 }
1947 if (info.has_data_reg) {
1948 fprintf(fp, ", R%d", data_reg);
1949 }
1950 fprintf(fp, "\n");
1951 }
1952
1953 void dump_instr(FILE *fp, const struct bifrost_alu_inst *instr,
1954 struct bifrost_regs next_regs, uint64_t *consts,
1955 unsigned data_reg, unsigned offset, bool verbose)
1956 {
1957 struct bifrost_regs regs;
1958 memcpy((char *) &regs, (char *) &instr->reg_bits, sizeof(regs));
1959
1960 if (verbose) {
1961 fprintf(fp, "# regs: %016" PRIx64 "\n", instr->reg_bits);
1962 dump_regs(fp, regs);
1963 }
1964 dump_fma(fp, instr->fma_bits, regs, next_regs, consts, verbose);
1965 dump_add(fp, instr->add_bits, regs, next_regs, consts, data_reg, offset, verbose);
1966 }
1967
1968 bool dump_clause(FILE *fp, uint32_t *words, unsigned *size, unsigned offset, bool verbose)
1969 {
1970 // State for a decoded clause
1971 struct bifrost_alu_inst instrs[8] = {};
1972 uint64_t consts[6] = {};
1973 unsigned num_instrs = 0;
1974 unsigned num_consts = 0;
1975 uint64_t header_bits = 0;
1976 bool stopbit = false;
1977
1978 unsigned i;
1979 for (i = 0; ; i++, words += 4) {
1980 if (verbose) {
1981 fprintf(fp, "# ");
1982 for (int j = 0; j < 4; j++)
1983 fprintf(fp, "%08x ", words[3 - j]); // low bit on the right
1984 fprintf(fp, "\n");
1985 }
1986 unsigned tag = bits(words[0], 0, 8);
1987
1988 // speculatively decode some things that are common between many formats, so we can share some code
1989 struct bifrost_alu_inst main_instr = {};
1990 // 20 bits
1991 main_instr.add_bits = bits(words[2], 2, 32 - 13);
1992 // 23 bits
1993 main_instr.fma_bits = bits(words[1], 11, 32) | bits(words[2], 0, 2) << (32 - 11);
1994 // 35 bits
1995 main_instr.reg_bits = ((uint64_t) bits(words[1], 0, 11)) << 24 | (uint64_t) bits(words[0], 8, 32);
1996
1997 uint64_t const0 = bits(words[0], 8, 32) << 4 | (uint64_t) words[1] << 28 | bits(words[2], 0, 4) << 60;
1998 uint64_t const1 = bits(words[2], 4, 32) << 4 | (uint64_t) words[3] << 32;
1999
2000 bool stop = tag & 0x40;
2001
2002 if (verbose) {
2003 fprintf(fp, "# tag: 0x%02x\n", tag);
2004 }
2005 if (tag & 0x80) {
2006 unsigned idx = stop ? 5 : 2;
2007 main_instr.add_bits |= ((tag >> 3) & 0x7) << 17;
2008 instrs[idx + 1] = main_instr;
2009 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17);
2010 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10;
2011 consts[0] = bits(words[3], 17, 32) << 4;
2012 } else {
2013 bool done = false;
2014 switch ((tag >> 3) & 0x7) {
2015 case 0x0:
2016 switch (tag & 0x7) {
2017 case 0x3:
2018 main_instr.add_bits |= bits(words[3], 29, 32) << 17;
2019 instrs[1] = main_instr;
2020 num_instrs = 2;
2021 done = stop;
2022 break;
2023 case 0x4:
2024 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2025 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
2026 consts[0] = const0;
2027 num_instrs = 3;
2028 num_consts = 1;
2029 done = stop;
2030 break;
2031 case 0x1:
2032 case 0x5:
2033 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2034 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
2035 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
2036 instrs[3] = main_instr;
2037 if ((tag & 0x7) == 0x5) {
2038 num_instrs = 4;
2039 done = stop;
2040 }
2041 break;
2042 case 0x6:
2043 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2044 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
2045 consts[0] = const0;
2046 num_instrs = 6;
2047 num_consts = 1;
2048 done = stop;
2049 break;
2050 case 0x7:
2051 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2052 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
2053 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
2054 instrs[6] = main_instr;
2055 num_instrs = 7;
2056 done = stop;
2057 break;
2058 default:
2059 fprintf(fp, "unknown tag bits 0x%02x\n", tag);
2060 }
2061 break;
2062 case 0x2:
2063 case 0x3: {
2064 unsigned idx = ((tag >> 3) & 0x7) == 2 ? 4 : 7;
2065 main_instr.add_bits |= (tag & 0x7) << 17;
2066 instrs[idx] = main_instr;
2067 consts[0] |= (bits(words[2], 19, 32) | ((uint64_t) words[3] << 13)) << 19;
2068 num_consts = 1;
2069 num_instrs = idx + 1;
2070 done = stop;
2071 break;
2072 }
2073 case 0x4: {
2074 unsigned idx = stop ? 4 : 1;
2075 main_instr.add_bits |= (tag & 0x7) << 17;
2076 instrs[idx] = main_instr;
2077 instrs[idx + 1].fma_bits |= bits(words[3], 22, 32);
2078 instrs[idx + 1].reg_bits = bits(words[2], 19, 32) | (bits(words[3], 0, 22) << (32 - 19));
2079 break;
2080 }
2081 case 0x1:
2082 // only constants can come after this
2083 num_instrs = 1;
2084 done = stop;
2085 case 0x5:
2086 header_bits = bits(words[2], 19, 32) | ((uint64_t) words[3] << (32 - 19));
2087 main_instr.add_bits |= (tag & 0x7) << 17;
2088 instrs[0] = main_instr;
2089 break;
2090 case 0x6:
2091 case 0x7: {
2092 unsigned pos = tag & 0xf;
2093 // note that `pos' encodes both the total number of
2094 // instructions and the position in the constant stream,
2095 // presumably because decoded constants and instructions
2096 // share a buffer in the decoder, but we only care about
2097 // the position in the constant stream; the total number of
2098 // instructions is redundant.
2099 unsigned const_idx = 0;
2100 switch (pos) {
2101 case 0:
2102 case 1:
2103 case 2:
2104 case 6:
2105 const_idx = 0;
2106 break;
2107 case 3:
2108 case 4:
2109 case 7:
2110 case 9:
2111 const_idx = 1;
2112 break;
2113 case 5:
2114 case 0xa:
2115 const_idx = 2;
2116 break;
2117 case 8:
2118 case 0xb:
2119 case 0xc:
2120 const_idx = 3;
2121 break;
2122 case 0xd:
2123 const_idx = 4;
2124 break;
2125 default:
2126 fprintf(fp, "# unknown pos 0x%x\n", pos);
2127 break;
2128 }
2129
2130 if (num_consts < const_idx + 2)
2131 num_consts = const_idx + 2;
2132
2133 consts[const_idx] = const0;
2134 consts[const_idx + 1] = const1;
2135 done = stop;
2136 break;
2137 }
2138 default:
2139 break;
2140 }
2141
2142 if (done)
2143 break;
2144 }
2145 }
2146
2147 *size = i + 1;
2148
2149 if (verbose) {
2150 fprintf(fp, "# header: %012" PRIx64 "\n", header_bits);
2151 }
2152
2153 struct bifrost_header header;
2154 memcpy((char *) &header, (char *) &header_bits, sizeof(struct bifrost_header));
2155 dump_header(fp, header, verbose);
2156 if (!header.no_end_of_shader)
2157 stopbit = true;
2158
2159 fprintf(fp, "{\n");
2160 for (i = 0; i < num_instrs; i++) {
2161 struct bifrost_regs next_regs;
2162 if (i + 1 == num_instrs) {
2163 memcpy((char *) &next_regs, (char *) &instrs[0].reg_bits,
2164 sizeof(next_regs));
2165 } else {
2166 memcpy((char *) &next_regs, (char *) &instrs[i + 1].reg_bits,
2167 sizeof(next_regs));
2168 }
2169
2170 dump_instr(fp, &instrs[i], next_regs, consts, header.datareg, offset, verbose);
2171 }
2172 fprintf(fp, "}\n");
2173
2174 if (verbose) {
2175 for (unsigned i = 0; i < num_consts; i++) {
2176 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i, consts[i] & 0xffffffff);
2177 fprintf(fp, "# const%d: %08" PRIx64 "\n", 2 * i + 1, consts[i] >> 32);
2178 }
2179 }
2180 return stopbit;
2181 }
2182
2183 void disassemble_bifrost(FILE *fp, uint8_t *code, size_t size, bool verbose)
2184 {
2185 uint32_t *words = (uint32_t *) code;
2186 uint32_t *words_end = words + (size / 4);
2187 // used for displaying branch targets
2188 unsigned offset = 0;
2189 while (words != words_end) {
2190 // we don't know what the program-end bit is quite yet, so for now just
2191 // assume that an all-0 quadword is padding
2192 uint32_t zero[4] = {};
2193 if (memcmp(words, zero, 4 * sizeof(uint32_t)) == 0)
2194 break;
2195 fprintf(fp, "clause_%d:\n", offset);
2196 unsigned size;
2197 if (dump_clause(fp, words, &size, offset, verbose) == true) {
2198 break;
2199 }
2200 words += size * 4;
2201 offset += size;
2202 }
2203 }
2204