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pan/bifrost: Style format the disassembler
[mesa.git] / src / panfrost / bifrost / disassemble.c
1 /*
2 * Copyright (C) 2019 Connor Abbott <cwabbott0@gmail.com>
3 * Copyright (C) 2019 Lyude Paul <thatslyude@gmail.com>
4 * Copyright (C) 2019 Ryan Houdek <Sonicadvance1@gmail.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 */
25
26 #include <stdbool.h>
27 #include <stdio.h>
28 #include <stdint.h>
29 #include <assert.h>
30 #include <inttypes.h>
31 #include <string.h>
32
33 #include "bifrost.h"
34 #include "bifrost_ops.h"
35 #include "disassemble.h"
36 #include "util/macros.h"
37
38 // return bits (high, lo]
39 static uint64_t bits(uint32_t word, unsigned lo, unsigned high)
40 {
41 if (high == 32)
42 return word >> lo;
43 return (word & ((1 << high) - 1)) >> lo;
44 }
45
46 // each of these structs represents an instruction that's dispatched in one
47 // cycle. Note that these instructions are packed in funny ways within the
48 // clause, hence the need for a separate struct.
49 struct bifrost_alu_inst {
50 uint32_t fma_bits;
51 uint32_t add_bits;
52 uint64_t reg_bits;
53 };
54
55 struct bifrost_regs {
56 unsigned uniform_const : 8;
57 unsigned reg2 : 6;
58 unsigned reg3 : 6;
59 unsigned reg0 : 5;
60 unsigned reg1 : 6;
61 unsigned ctrl : 4;
62 };
63
64 static unsigned get_reg0(struct bifrost_regs regs)
65 {
66 if (regs.ctrl == 0)
67 return regs.reg0 | ((regs.reg1 & 0x1) << 5);
68
69 return regs.reg0 <= regs.reg1 ? regs.reg0 : 63 - regs.reg0;
70 }
71
72 static unsigned get_reg1(struct bifrost_regs regs)
73 {
74 return regs.reg0 <= regs.reg1 ? regs.reg1 : 63 - regs.reg1;
75 }
76
77 enum bifrost_reg_write_unit {
78 REG_WRITE_NONE = 0, // don't write
79 REG_WRITE_TWO, // write using reg2
80 REG_WRITE_THREE, // write using reg3
81 };
82
83 // this represents the decoded version of the ctrl register field.
84 struct bifrost_reg_ctrl {
85 bool read_reg0;
86 bool read_reg1;
87 bool read_reg3;
88 enum bifrost_reg_write_unit fma_write_unit;
89 enum bifrost_reg_write_unit add_write_unit;
90 bool clause_start;
91 };
92
93 enum fma_src_type {
94 FMA_ONE_SRC,
95 FMA_TWO_SRC,
96 FMA_FADD,
97 FMA_FMINMAX,
98 FMA_FADD16,
99 FMA_FMINMAX16,
100 FMA_FCMP,
101 FMA_FCMP16,
102 FMA_THREE_SRC,
103 FMA_FMA,
104 FMA_FMA16,
105 FMA_FOUR_SRC,
106 FMA_FMA_MSCALE,
107 FMA_SHIFT_ADD64,
108 };
109
110 struct fma_op_info {
111 unsigned op;
112 char name[30];
113 enum fma_src_type src_type;
114 };
115
116 enum add_src_type {
117 ADD_ONE_SRC,
118 ADD_TWO_SRC,
119 ADD_FADD,
120 ADD_FMINMAX,
121 ADD_FADD16,
122 ADD_FMINMAX16,
123 ADD_THREE_SRC,
124 ADD_FADDMscale,
125 ADD_FCMP,
126 ADD_FCMP16,
127 ADD_TEX_COMPACT, // texture instruction with embedded sampler
128 ADD_TEX, // texture instruction with sampler/etc. in uniform port
129 ADD_VARYING_INTERP,
130 ADD_BLENDING,
131 ADD_LOAD_ATTR,
132 ADD_VARYING_ADDRESS,
133 ADD_BRANCH,
134 };
135
136 struct add_op_info {
137 unsigned op;
138 char name[30];
139 enum add_src_type src_type;
140 bool has_data_reg;
141 };
142
143 struct bifrost_tex_ctrl {
144 unsigned sampler_index : 4; // also used to signal indirects
145 unsigned tex_index : 7;
146 bool no_merge_index : 1; // whether to merge (direct) sampler & texture indices
147 bool filter : 1; // use the usual filtering pipeline (0 for texelFetch & textureGather)
148 unsigned unk0 : 2;
149 bool texel_offset : 1; // *Offset()
150 bool is_shadow : 1;
151 bool is_array : 1;
152 unsigned tex_type : 2; // 2D, 3D, Cube, Buffer
153 bool compute_lod : 1; // 0 for *Lod()
154 bool not_supply_lod : 1; // 0 for *Lod() or when a bias is applied
155 bool calc_gradients : 1; // 0 for *Grad()
156 unsigned unk1 : 1;
157 unsigned result_type : 4; // integer, unsigned, float TODO: why is this 4 bits?
158 unsigned unk2 : 4;
159 };
160
161 struct bifrost_dual_tex_ctrl {
162 unsigned sampler_index0 : 2;
163 unsigned unk0 : 2;
164 unsigned tex_index0 : 2;
165 unsigned sampler_index1 : 2;
166 unsigned tex_index1 : 2;
167 unsigned unk1 : 22;
168 };
169
170 enum branch_bit_size {
171 BR_SIZE_32 = 0,
172 BR_SIZE_16XX = 1,
173 BR_SIZE_16YY = 2,
174 // For the above combinations of bitsize and location, an extra bit is
175 // encoded via comparing the sources. The only possible source of ambiguity
176 // would be if the sources were the same, but then the branch condition
177 // would be always true or always false anyways, so we can ignore it. But
178 // this no longer works when comparing the y component to the x component,
179 // since it's valid to compare the y component of a source against its own
180 // x component. Instead, the extra bit is encoded via an extra bitsize.
181 BR_SIZE_16YX0 = 3,
182 BR_SIZE_16YX1 = 4,
183 BR_SIZE_32_AND_16X = 5,
184 BR_SIZE_32_AND_16Y = 6,
185 // Used for comparisons with zero and always-true, see below. I think this
186 // only works for integer comparisons.
187 BR_SIZE_ZERO = 7,
188 };
189
190 void dump_header(struct bifrost_header header, bool verbose);
191 void dump_instr(const struct bifrost_alu_inst *instr, struct bifrost_regs next_regs, uint64_t *consts,
192 unsigned data_reg, unsigned offset, bool verbose);
193 bool dump_clause(uint32_t *words, unsigned *size, unsigned offset, bool verbose);
194
195 void dump_header(struct bifrost_header header, bool verbose)
196 {
197 if (header.clause_type != 0) {
198 printf("id(%du) ", header.scoreboard_index);
199 }
200
201 if (header.scoreboard_deps != 0) {
202 printf("next-wait(");
203 bool first = true;
204 for (unsigned i = 0; i < 8; i++) {
205 if (header.scoreboard_deps & (1 << i)) {
206 if (!first) {
207 printf(", ");
208 }
209 printf("%d", i);
210 first = false;
211 }
212 }
213 printf(") ");
214 }
215
216 if (header.datareg_writebarrier)
217 printf("data-reg-barrier ");
218
219 if (!header.no_end_of_shader)
220 printf("eos ");
221
222 if (!header.back_to_back) {
223 printf("nbb ");
224 if (header.branch_cond)
225 printf("branch-cond ");
226 else
227 printf("branch-uncond ");
228 }
229
230 if (header.elide_writes)
231 printf("we ");
232
233 if (header.suppress_inf)
234 printf("suppress-inf ");
235 if (header.suppress_nan)
236 printf("suppress-nan ");
237
238 if (header.unk0)
239 printf("unk0 ");
240 if (header.unk1)
241 printf("unk1 ");
242 if (header.unk2)
243 printf("unk2 ");
244 if (header.unk3)
245 printf("unk3 ");
246 if (header.unk4)
247 printf("unk4 ");
248
249 printf("\n");
250
251 if (verbose) {
252 printf("# clause type %d, next clause type %d\n",
253 header.clause_type, header.next_clause_type);
254 }
255 }
256
257 static struct bifrost_reg_ctrl DecodeRegCtrl(struct bifrost_regs regs)
258 {
259 struct bifrost_reg_ctrl decoded = {};
260 unsigned ctrl;
261 if (regs.ctrl == 0) {
262 ctrl = regs.reg1 >> 2;
263 decoded.read_reg0 = !(regs.reg1 & 0x2);
264 decoded.read_reg1 = false;
265 } else {
266 ctrl = regs.ctrl;
267 decoded.read_reg0 = decoded.read_reg1 = true;
268 }
269 switch (ctrl) {
270 case 1:
271 decoded.fma_write_unit = REG_WRITE_TWO;
272 break;
273 case 2:
274 case 3:
275 decoded.fma_write_unit = REG_WRITE_TWO;
276 decoded.read_reg3 = true;
277 break;
278 case 4:
279 decoded.read_reg3 = true;
280 break;
281 case 5:
282 decoded.add_write_unit = REG_WRITE_TWO;
283 break;
284 case 6:
285 decoded.add_write_unit = REG_WRITE_TWO;
286 decoded.read_reg3 = true;
287 break;
288 case 8:
289 decoded.clause_start = true;
290 break;
291 case 9:
292 decoded.fma_write_unit = REG_WRITE_TWO;
293 decoded.clause_start = true;
294 break;
295 case 11:
296 break;
297 case 12:
298 decoded.read_reg3 = true;
299 decoded.clause_start = true;
300 break;
301 case 13:
302 decoded.add_write_unit = REG_WRITE_TWO;
303 decoded.clause_start = true;
304 break;
305
306 case 7:
307 case 15:
308 decoded.fma_write_unit = REG_WRITE_THREE;
309 decoded.add_write_unit = REG_WRITE_TWO;
310 break;
311 default:
312 printf("# unknown reg ctrl %d\n", ctrl);
313 }
314
315 return decoded;
316 }
317
318 // Pass in the add_write_unit or fma_write_unit, and this returns which register
319 // the ADD/FMA units are writing to
320 static unsigned GetRegToWrite(enum bifrost_reg_write_unit unit, struct bifrost_regs regs)
321 {
322 switch (unit) {
323 case REG_WRITE_TWO:
324 return regs.reg2;
325 case REG_WRITE_THREE:
326 return regs.reg3;
327 default: /* REG_WRITE_NONE */
328 assert(0);
329 return 0;
330 }
331 }
332
333 static void dump_regs(struct bifrost_regs srcs)
334 {
335 struct bifrost_reg_ctrl ctrl = DecodeRegCtrl(srcs);
336 printf("# ");
337 if (ctrl.read_reg0)
338 printf("port 0: R%d ", get_reg0(srcs));
339 if (ctrl.read_reg1)
340 printf("port 1: R%d ", get_reg1(srcs));
341
342 if (ctrl.fma_write_unit == REG_WRITE_TWO)
343 printf("port 2: R%d (write FMA) ", srcs.reg2);
344 else if (ctrl.add_write_unit == REG_WRITE_TWO)
345 printf("port 2: R%d (write ADD) ", srcs.reg2);
346
347 if (ctrl.fma_write_unit == REG_WRITE_THREE)
348 printf("port 3: R%d (write FMA) ", srcs.reg3);
349 else if (ctrl.add_write_unit == REG_WRITE_THREE)
350 printf("port 3: R%d (write ADD) ", srcs.reg3);
351 else if (ctrl.read_reg3)
352 printf("port 3: R%d (read) ", srcs.reg3);
353
354 if (srcs.uniform_const) {
355 if (srcs.uniform_const & 0x80) {
356 printf("uniform: U%d", (srcs.uniform_const & 0x7f) * 2);
357 }
358 }
359
360 printf("\n");
361 }
362 static void dump_const_imm(uint32_t imm)
363 {
364 union {
365 float f;
366 uint32_t i;
367 } fi;
368 fi.i = imm;
369 printf("0x%08x /* %f */", imm, fi.f);
370 }
371
372 static uint64_t get_const(uint64_t *consts, struct bifrost_regs srcs)
373 {
374 unsigned low_bits = srcs.uniform_const & 0xf;
375 uint64_t imm;
376 switch (srcs.uniform_const >> 4) {
377 case 4:
378 imm = consts[0];
379 break;
380 case 5:
381 imm = consts[1];
382 break;
383 case 6:
384 imm = consts[2];
385 break;
386 case 7:
387 imm = consts[3];
388 break;
389 case 2:
390 imm = consts[4];
391 break;
392 case 3:
393 imm = consts[5];
394 break;
395 default:
396 assert(0);
397 break;
398 }
399 return imm | low_bits;
400 }
401
402 static void dump_uniform_const_src(struct bifrost_regs srcs, uint64_t *consts, bool high32)
403 {
404 if (srcs.uniform_const & 0x80) {
405 unsigned uniform = (srcs.uniform_const & 0x7f) * 2;
406 printf("U%d", uniform + (high32 ? 1 : 0));
407 } else if (srcs.uniform_const >= 0x20) {
408 uint64_t imm = get_const(consts, srcs);
409 if (high32)
410 dump_const_imm(imm >> 32);
411 else
412 dump_const_imm(imm);
413 } else {
414 switch (srcs.uniform_const) {
415 case 0:
416 printf("0");
417 break;
418 case 5:
419 printf("atest-data");
420 break;
421 case 6:
422 printf("sample-ptr");
423 break;
424 case 8:
425 case 9:
426 case 10:
427 case 11:
428 case 12:
429 case 13:
430 case 14:
431 case 15:
432 printf("blend-descriptor%u", (unsigned) srcs.uniform_const - 8);
433 break;
434 default:
435 printf("unkConst%u", (unsigned) srcs.uniform_const);
436 break;
437 }
438
439 if (high32)
440 printf(".y");
441 else
442 printf(".x");
443 }
444 }
445
446 static void dump_src(unsigned src, struct bifrost_regs srcs, uint64_t *consts, bool isFMA)
447 {
448 switch (src) {
449 case 0:
450 printf("R%d", get_reg0(srcs));
451 break;
452 case 1:
453 printf("R%d", get_reg1(srcs));
454 break;
455 case 2:
456 printf("R%d", srcs.reg3);
457 break;
458 case 3:
459 if (isFMA)
460 printf("0");
461 else
462 printf("T"); // i.e. the output of FMA this cycle
463 break;
464 case 4:
465 dump_uniform_const_src(srcs, consts, false);
466 break;
467 case 5:
468 dump_uniform_const_src(srcs, consts, true);
469 break;
470 case 6:
471 printf("T0");
472 break;
473 case 7:
474 printf("T1");
475 break;
476 }
477 }
478
479 static void dump_output_mod(unsigned mod)
480 {
481 switch (mod) {
482 case 0:
483 break;
484 case 1:
485 printf(".clamp_0_inf");
486 break; // max(out, 0)
487 case 2:
488 printf(".clamp_m1_1");
489 break; // clamp(out, -1, 1)
490 case 3:
491 printf(".clamp_0_1");
492 break; // clamp(out, 0, 1)
493 default:
494 break;
495 }
496 }
497
498 static void dump_minmax_mode(unsigned mod)
499 {
500 switch (mod) {
501 case 0:
502 /* Same as fmax() and fmin() -- return the other number if any
503 * number is NaN. Also always return +0 if one argument is +0 and
504 * the other is -0.
505 */
506 break;
507 case 1:
508 /* Instead of never returning a NaN, always return one. The
509 * "greater"/"lesser" NaN is always returned, first by checking the
510 * sign and then the mantissa bits.
511 */
512 printf(".nan_wins");
513 break;
514 case 2:
515 /* For max, implement src0 > src1 ? src0 : src1
516 * For min, implement src0 < src1 ? src0 : src1
517 *
518 * This includes handling NaN's and signedness of 0 differently
519 * from above, since +0 and -0 compare equal and comparisons always
520 * return false for NaN's. As a result, this mode is *not*
521 * commutative.
522 */
523 printf(".src1_wins");
524 break;
525 case 3:
526 /* For max, implement src0 < src1 ? src1 : src0
527 * For min, implement src0 > src1 ? src1 : src0
528 */
529 printf(".src0_wins");
530 break;
531 default:
532 break;
533 }
534 }
535
536 static void dump_round_mode(unsigned mod)
537 {
538 switch (mod) {
539 case 0:
540 /* roundTiesToEven, the IEEE default. */
541 break;
542 case 1:
543 /* roundTowardPositive in the IEEE spec. */
544 printf(".round_pos");
545 break;
546 case 2:
547 /* roundTowardNegative in the IEEE spec. */
548 printf(".round_neg");
549 break;
550 case 3:
551 /* roundTowardZero in the IEEE spec. */
552 printf(".round_zero");
553 break;
554 default:
555 break;
556 }
557 }
558
559 static const struct fma_op_info FMAOpInfos[] = {
560 { 0x00000, "FMA.f32", FMA_FMA },
561 { 0x40000, "MAX.f32", FMA_FMINMAX },
562 { 0x44000, "MIN.f32", FMA_FMINMAX },
563 { 0x48000, "FCMP.GL", FMA_FCMP },
564 { 0x4c000, "FCMP.D3D", FMA_FCMP },
565 { 0x4ff98, "ADD.i32", FMA_TWO_SRC },
566 { 0x4ffd8, "SUB.i32", FMA_TWO_SRC },
567 { 0x4fff0, "SUBB.i32", FMA_TWO_SRC },
568 { 0x50000, "FMA_MSCALE", FMA_FMA_MSCALE },
569 { 0x58000, "ADD.f32", FMA_FADD },
570 { 0x5c000, "CSEL.FEQ.f32", FMA_FOUR_SRC },
571 { 0x5c200, "CSEL.FGT.f32", FMA_FOUR_SRC },
572 { 0x5c400, "CSEL.FGE.f32", FMA_FOUR_SRC },
573 { 0x5c600, "CSEL.IEQ.f32", FMA_FOUR_SRC },
574 { 0x5c800, "CSEL.IGT.i32", FMA_FOUR_SRC },
575 { 0x5ca00, "CSEL.IGE.i32", FMA_FOUR_SRC },
576 { 0x5cc00, "CSEL.UGT.i32", FMA_FOUR_SRC },
577 { 0x5ce00, "CSEL.UGE.i32", FMA_FOUR_SRC },
578 { 0x5d8d0, "ICMP.D3D.GT.v2i16", FMA_TWO_SRC },
579 { 0x5d9d0, "UCMP.D3D.GT.v2i16", FMA_TWO_SRC },
580 { 0x5dad0, "ICMP.D3D.GE.v2i16", FMA_TWO_SRC },
581 { 0x5dbd0, "UCMP.D3D.GE.v2i16", FMA_TWO_SRC },
582 { 0x5dcd0, "ICMP.D3D.EQ.v2i16", FMA_TWO_SRC },
583 { 0x5de40, "ICMP.GL.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? 1 : 0
584 { 0x5de48, "ICMP.GL.GE.i32", FMA_TWO_SRC },
585 { 0x5de50, "UCMP.GL.GT.i32", FMA_TWO_SRC },
586 { 0x5de58, "UCMP.GL.GE.i32", FMA_TWO_SRC },
587 { 0x5de60, "ICMP.GL.EQ.i32", FMA_TWO_SRC },
588 { 0x5dec0, "ICMP.D3D.GT.i32", FMA_TWO_SRC }, // src0 > src1 ? ~0 : 0
589 { 0x5dec8, "ICMP.D3D.GE.i32", FMA_TWO_SRC },
590 { 0x5ded0, "UCMP.D3D.GT.i32", FMA_TWO_SRC },
591 { 0x5ded8, "UCMP.D3D.GE.i32", FMA_TWO_SRC },
592 { 0x5dee0, "ICMP.D3D.EQ.i32", FMA_TWO_SRC },
593 { 0x60200, "RSHIFT_NAND.i32", FMA_THREE_SRC },
594 { 0x603c0, "RSHIFT_NAND.v2i16", FMA_THREE_SRC },
595 { 0x60e00, "RSHIFT_OR.i32", FMA_THREE_SRC },
596 { 0x60fc0, "RSHIFT_OR.v2i16", FMA_THREE_SRC },
597 { 0x61200, "RSHIFT_AND.i32", FMA_THREE_SRC },
598 { 0x613c0, "RSHIFT_AND.v2i16", FMA_THREE_SRC },
599 { 0x61e00, "RSHIFT_NOR.i32", FMA_THREE_SRC }, // ~((src0 << src2) | src1)
600 { 0x61fc0, "RSHIFT_NOR.v2i16", FMA_THREE_SRC }, // ~((src0 << src2) | src1)
601 { 0x62200, "LSHIFT_NAND.i32", FMA_THREE_SRC },
602 { 0x623c0, "LSHIFT_NAND.v2i16", FMA_THREE_SRC },
603 { 0x62e00, "LSHIFT_OR.i32", FMA_THREE_SRC }, // (src0 << src2) | src1
604 { 0x62fc0, "LSHIFT_OR.v2i16", FMA_THREE_SRC }, // (src0 << src2) | src1
605 { 0x63200, "LSHIFT_AND.i32", FMA_THREE_SRC }, // (src0 << src2) & src1
606 { 0x633c0, "LSHIFT_AND.v2i16", FMA_THREE_SRC },
607 { 0x63e00, "LSHIFT_NOR.i32", FMA_THREE_SRC },
608 { 0x63fc0, "LSHIFT_NOR.v2i16", FMA_THREE_SRC },
609 { 0x64200, "RSHIFT_XOR.i32", FMA_THREE_SRC },
610 { 0x643c0, "RSHIFT_XOR.v2i16", FMA_THREE_SRC },
611 { 0x64600, "RSHIFT_XNOR.i32", FMA_THREE_SRC }, // ~((src0 >> src2) ^ src1)
612 { 0x647c0, "RSHIFT_XNOR.v2i16", FMA_THREE_SRC }, // ~((src0 >> src2) ^ src1)
613 { 0x64a00, "LSHIFT_XOR.i32", FMA_THREE_SRC },
614 { 0x64bc0, "LSHIFT_XOR.v2i16", FMA_THREE_SRC },
615 { 0x64e00, "LSHIFT_XNOR.i32", FMA_THREE_SRC }, // ~((src0 >> src2) ^ src1)
616 { 0x64fc0, "LSHIFT_XNOR.v2i16", FMA_THREE_SRC }, // ~((src0 >> src2) ^ src1)
617 { 0x65200, "LSHIFT_ADD.i32", FMA_THREE_SRC },
618 { 0x65600, "LSHIFT_SUB.i32", FMA_THREE_SRC }, // (src0 << src2) - src1
619 { 0x65a00, "LSHIFT_RSUB.i32", FMA_THREE_SRC }, // src1 - (src0 << src2)
620 { 0x65e00, "RSHIFT_ADD.i32", FMA_THREE_SRC },
621 { 0x66200, "RSHIFT_SUB.i32", FMA_THREE_SRC },
622 { 0x66600, "RSHIFT_RSUB.i32", FMA_THREE_SRC },
623 { 0x66a00, "ARSHIFT_ADD.i32", FMA_THREE_SRC },
624 { 0x66e00, "ARSHIFT_SUB.i32", FMA_THREE_SRC },
625 { 0x67200, "ARSHIFT_RSUB.i32", FMA_THREE_SRC },
626 { 0x80000, "FMA.v2f16", FMA_FMA16 },
627 { 0xc0000, "MAX.v2f16", FMA_FMINMAX16 },
628 { 0xc4000, "MIN.v2f16", FMA_FMINMAX16 },
629 { 0xc8000, "FCMP.GL", FMA_FCMP16 },
630 { 0xcc000, "FCMP.D3D", FMA_FCMP16 },
631 { 0xcf900, "ADD.v2i16", FMA_TWO_SRC },
632 { 0xcfc10, "ADDC.i32", FMA_TWO_SRC },
633 { 0xcfd80, "ADD.i32.i16.X", FMA_TWO_SRC },
634 { 0xcfd90, "ADD.i32.u16.X", FMA_TWO_SRC },
635 { 0xcfdc0, "ADD.i32.i16.Y", FMA_TWO_SRC },
636 { 0xcfdd0, "ADD.i32.u16.Y", FMA_TWO_SRC },
637 { 0xd8000, "ADD.v2f16", FMA_FADD16 },
638 { 0xdc000, "CSEL.FEQ.v2f16", FMA_FOUR_SRC },
639 { 0xdc200, "CSEL.FGT.v2f16", FMA_FOUR_SRC },
640 { 0xdc400, "CSEL.FGE.v2f16", FMA_FOUR_SRC },
641 { 0xdc600, "CSEL.IEQ.v2f16", FMA_FOUR_SRC },
642 { 0xdc800, "CSEL.IGT.v2i16", FMA_FOUR_SRC },
643 { 0xdca00, "CSEL.IGE.v2i16", FMA_FOUR_SRC },
644 { 0xdcc00, "CSEL.UGT.v2i16", FMA_FOUR_SRC },
645 { 0xdce00, "CSEL.UGE.v2i16", FMA_FOUR_SRC },
646 { 0xdd000, "F32_TO_F16", FMA_TWO_SRC },
647 { 0xe0046, "F16_TO_I16.XX", FMA_ONE_SRC },
648 { 0xe0047, "F16_TO_U16.XX", FMA_ONE_SRC },
649 { 0xe004e, "F16_TO_I16.YX", FMA_ONE_SRC },
650 { 0xe004f, "F16_TO_U16.YX", FMA_ONE_SRC },
651 { 0xe0056, "F16_TO_I16.XY", FMA_ONE_SRC },
652 { 0xe0057, "F16_TO_U16.XY", FMA_ONE_SRC },
653 { 0xe005e, "F16_TO_I16.YY", FMA_ONE_SRC },
654 { 0xe005f, "F16_TO_U16.YY", FMA_ONE_SRC },
655 { 0xe00c0, "I16_TO_F16.XX", FMA_ONE_SRC },
656 { 0xe00c1, "U16_TO_F16.XX", FMA_ONE_SRC },
657 { 0xe00c8, "I16_TO_F16.YX", FMA_ONE_SRC },
658 { 0xe00c9, "U16_TO_F16.YX", FMA_ONE_SRC },
659 { 0xe00d0, "I16_TO_F16.XY", FMA_ONE_SRC },
660 { 0xe00d1, "U16_TO_F16.XY", FMA_ONE_SRC },
661 { 0xe00d8, "I16_TO_F16.YY", FMA_ONE_SRC },
662 { 0xe00d9, "U16_TO_F16.YY", FMA_ONE_SRC },
663 { 0xe0136, "F32_TO_I32", FMA_ONE_SRC },
664 { 0xe0137, "F32_TO_U32", FMA_ONE_SRC },
665 { 0xe0178, "I32_TO_F32", FMA_ONE_SRC },
666 { 0xe0179, "U32_TO_F32", FMA_ONE_SRC },
667 { 0xe0198, "I16_TO_I32.X", FMA_ONE_SRC },
668 { 0xe0199, "U16_TO_U32.X", FMA_ONE_SRC },
669 { 0xe019a, "I16_TO_I32.Y", FMA_ONE_SRC },
670 { 0xe019b, "U16_TO_U32.Y", FMA_ONE_SRC },
671 { 0xe019c, "I16_TO_F32.X", FMA_ONE_SRC },
672 { 0xe019d, "U16_TO_F32.X", FMA_ONE_SRC },
673 { 0xe019e, "I16_TO_F32.Y", FMA_ONE_SRC },
674 { 0xe019f, "U16_TO_F32.Y", FMA_ONE_SRC },
675 { 0xe01a2, "F16_TO_F32.X", FMA_ONE_SRC },
676 { 0xe01a3, "F16_TO_F32.Y", FMA_ONE_SRC },
677 { 0xe032c, "NOP", FMA_ONE_SRC },
678 { 0xe032d, "MOV", FMA_ONE_SRC },
679 { 0xe032f, "SWZ.YY.v2i16", FMA_ONE_SRC },
680 // From the ARM patent US20160364209A1:
681 // "Decompose v (the input) into numbers x1 and s such that v = x1 * 2^s,
682 // and x1 is a floating point value in a predetermined range where the
683 // value 1 is within the range and not at one extremity of the range (e.g.
684 // choose a range where 1 is towards middle of range)."
685 //
686 // This computes x1.
687 { 0xe0345, "LOG_FREXPM", FMA_ONE_SRC },
688 // Given a floating point number m * 2^e, returns m * 2^{-1}. This is
689 // exactly the same as the mantissa part of frexp().
690 { 0xe0365, "FRCP_FREXPM", FMA_ONE_SRC },
691 // Given a floating point number m * 2^e, returns m * 2^{-2} if e is even,
692 // and m * 2^{-1} if e is odd. In other words, scales by powers of 4 until
693 // within the range [0.25, 1). Used for square-root and reciprocal
694 // square-root.
695 { 0xe0375, "FSQRT_FREXPM", FMA_ONE_SRC },
696 // Given a floating point number m * 2^e, computes -e - 1 as an integer.
697 // Zero and infinity/NaN return 0.
698 { 0xe038d, "FRCP_FREXPE", FMA_ONE_SRC },
699 // Computes floor(e/2) + 1.
700 { 0xe03a5, "FSQRT_FREXPE", FMA_ONE_SRC },
701 // Given a floating point number m * 2^e, computes -floor(e/2) - 1 as an
702 // integer.
703 { 0xe03ad, "FRSQ_FREXPE", FMA_ONE_SRC },
704 { 0xe03c5, "LOG_FREXPE", FMA_ONE_SRC },
705 { 0xe03fa, "CLZ", FMA_ONE_SRC },
706 { 0xe0b80, "IMAX3", FMA_THREE_SRC },
707 { 0xe0bc0, "UMAX3", FMA_THREE_SRC },
708 { 0xe0c00, "IMIN3", FMA_THREE_SRC },
709 { 0xe0c40, "UMIN3", FMA_THREE_SRC },
710 { 0xe0ec5, "ROUND", FMA_ONE_SRC },
711 { 0xe0f40, "CSEL", FMA_THREE_SRC }, // src2 != 0 ? src1 : src0
712 { 0xe0fc0, "MUX.i32", FMA_THREE_SRC }, // see ADD comment
713 { 0xe1805, "ROUNDEVEN", FMA_ONE_SRC },
714 { 0xe1845, "CEIL", FMA_ONE_SRC },
715 { 0xe1885, "FLOOR", FMA_ONE_SRC },
716 { 0xe18c5, "TRUNC", FMA_ONE_SRC },
717 { 0xe19b0, "ATAN_LDEXP.Y.f32", FMA_TWO_SRC },
718 { 0xe19b8, "ATAN_LDEXP.X.f32", FMA_TWO_SRC },
719 // These instructions in the FMA slot, together with LSHIFT_ADD_HIGH32.i32
720 // in the ADD slot, allow one to do a 64-bit addition with an extra small
721 // shift on one of the sources. There are three possible scenarios:
722 //
723 // 1) Full 64-bit addition. Do:
724 // out.x = LSHIFT_ADD_LOW32.i64 src1.x, src2.x, shift
725 // out.y = LSHIFT_ADD_HIGH32.i32 src1.y, src2.y
726 //
727 // The shift amount is applied to src2 before adding. The shift amount, and
728 // any extra bits from src2 plus the overflow bit, are sent directly from
729 // FMA to ADD instead of being passed explicitly. Hence, these two must be
730 // bundled together into the same instruction.
731 //
732 // 2) Add a 64-bit value src1 to a zero-extended 32-bit value src2. Do:
733 // out.x = LSHIFT_ADD_LOW32.u32 src1.x, src2, shift
734 // out.y = LSHIFT_ADD_HIGH32.i32 src1.x, 0
735 //
736 // Note that in this case, the second argument to LSHIFT_ADD_HIGH32 is
737 // ignored, so it can actually be anything. As before, the shift is applied
738 // to src2 before adding.
739 //
740 // 3) Add a 64-bit value to a sign-extended 32-bit value src2. Do:
741 // out.x = LSHIFT_ADD_LOW32.i32 src1.x, src2, shift
742 // out.y = LSHIFT_ADD_HIGH32.i32 src1.x, 0
743 //
744 // The only difference is the .i32 instead of .u32. Otherwise, this is
745 // exactly the same as before.
746 //
747 // In all these instructions, the shift amount is stored where the third
748 // source would be, so the shift has to be a small immediate from 0 to 7.
749 // This is fine for the expected use-case of these instructions, which is
750 // manipulating 64-bit pointers.
751 //
752 // These instructions can also be combined with various load/store
753 // instructions which normally take a 64-bit pointer in order to add a
754 // 32-bit or 64-bit offset to the pointer before doing the operation,
755 // optionally shifting the offset. The load/store op implicity does
756 // LSHIFT_ADD_HIGH32.i32 internally. Letting ptr be the pointer, and offset
757 // the desired offset, the cases go as follows:
758 //
759 // 1) Add a 64-bit offset:
760 // LSHIFT_ADD_LOW32.i64 ptr.x, offset.x, shift
761 // ld_st_op ptr.y, offset.y, ...
762 //
763 // Note that the output of LSHIFT_ADD_LOW32.i64 is not used, instead being
764 // implicitly sent to the load/store op to serve as the low 32 bits of the
765 // pointer.
766 //
767 // 2) Add a 32-bit unsigned offset:
768 // temp = LSHIFT_ADD_LOW32.u32 ptr.x, offset, shift
769 // ld_st_op temp, ptr.y, ...
770 //
771 // Now, the low 32 bits of offset << shift + ptr are passed explicitly to
772 // the ld_st_op, to match the case where there is no offset and ld_st_op is
773 // called directly.
774 //
775 // 3) Add a 32-bit signed offset:
776 // temp = LSHIFT_ADD_LOW32.i32 ptr.x, offset, shift
777 // ld_st_op temp, ptr.y, ...
778 //
779 // Again, the same as the unsigned case except for the offset.
780 { 0xe1c80, "LSHIFT_ADD_LOW32.u32", FMA_SHIFT_ADD64 },
781 { 0xe1cc0, "LSHIFT_ADD_LOW32.i64", FMA_SHIFT_ADD64 },
782 { 0xe1d80, "LSHIFT_ADD_LOW32.i32", FMA_SHIFT_ADD64 },
783 { 0xe1e00, "SEL.XX.i16", FMA_TWO_SRC },
784 { 0xe1e08, "SEL.YX.i16", FMA_TWO_SRC },
785 { 0xe1e10, "SEL.XY.i16", FMA_TWO_SRC },
786 { 0xe1e18, "SEL.YY.i16", FMA_TWO_SRC },
787 { 0xe7800, "IMAD", FMA_THREE_SRC },
788 { 0xe78db, "POPCNT", FMA_ONE_SRC },
789 };
790
791 static struct fma_op_info find_fma_op_info(unsigned op)
792 {
793 for (unsigned i = 0; i < ARRAY_SIZE(FMAOpInfos); i++) {
794 unsigned opCmp = ~0;
795 switch (FMAOpInfos[i].src_type) {
796 case FMA_ONE_SRC:
797 opCmp = op;
798 break;
799 case FMA_TWO_SRC:
800 opCmp = op & ~0x7;
801 break;
802 case FMA_FCMP:
803 case FMA_FCMP16:
804 opCmp = op & ~0x1fff;
805 break;
806 case FMA_THREE_SRC:
807 case FMA_SHIFT_ADD64:
808 opCmp = op & ~0x3f;
809 break;
810 case FMA_FADD:
811 case FMA_FMINMAX:
812 case FMA_FADD16:
813 case FMA_FMINMAX16:
814 opCmp = op & ~0x3fff;
815 break;
816 case FMA_FMA:
817 case FMA_FMA16:
818 opCmp = op & ~0x3ffff;
819 break;
820 case FMA_FOUR_SRC:
821 opCmp = op & ~0x1ff;
822 break;
823 case FMA_FMA_MSCALE:
824 opCmp = op & ~0x7fff;
825 break;
826 default:
827 opCmp = ~0;
828 break;
829 }
830 if (FMAOpInfos[i].op == opCmp)
831 return FMAOpInfos[i];
832 }
833
834 struct fma_op_info info;
835 snprintf(info.name, sizeof(info.name), "op%04x", op);
836 info.op = op;
837 info.src_type = FMA_THREE_SRC;
838 return info;
839 }
840
841 static void dump_fcmp(unsigned op)
842 {
843 switch (op) {
844 case 0:
845 printf(".OEQ");
846 break;
847 case 1:
848 printf(".OGT");
849 break;
850 case 2:
851 printf(".OGE");
852 break;
853 case 3:
854 printf(".UNE");
855 break;
856 case 4:
857 printf(".OLT");
858 break;
859 case 5:
860 printf(".OLE");
861 break;
862 default:
863 printf(".unk%d", op);
864 break;
865 }
866 }
867
868 static void dump_16swizzle(unsigned swiz)
869 {
870 if (swiz == 2)
871 return;
872 printf(".%c%c", "xy"[swiz & 1], "xy"[(swiz >> 1) & 1]);
873 }
874
875 static void dump_fma_expand_src0(unsigned ctrl)
876 {
877 switch (ctrl) {
878 case 3:
879 case 4:
880 case 6:
881 printf(".x");
882 break;
883 case 5:
884 case 7:
885 printf(".y");
886 break;
887 case 0:
888 case 1:
889 case 2:
890 break;
891 default:
892 printf(".unk");
893 break;
894 }
895 }
896
897 static void dump_fma_expand_src1(unsigned ctrl)
898 {
899 switch (ctrl) {
900 case 1:
901 case 3:
902 printf(".x");
903 break;
904 case 2:
905 case 4:
906 case 5:
907 printf(".y");
908 break;
909 case 0:
910 case 6:
911 case 7:
912 break;
913 default:
914 printf(".unk");
915 break;
916 }
917 }
918
919 static void dump_fma(uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts, bool verbose)
920 {
921 if (verbose) {
922 printf("# FMA: %016" PRIx64 "\n", word);
923 }
924 struct bifrost_fma_inst FMA;
925 memcpy((char *) &FMA, (char *) &word, sizeof(struct bifrost_fma_inst));
926 struct fma_op_info info = find_fma_op_info(FMA.op);
927
928 printf("%s", info.name);
929 if (info.src_type == FMA_FADD ||
930 info.src_type == FMA_FMINMAX ||
931 info.src_type == FMA_FMA ||
932 info.src_type == FMA_FADD16 ||
933 info.src_type == FMA_FMINMAX16 ||
934 info.src_type == FMA_FMA16) {
935 dump_output_mod(bits(FMA.op, 12, 14));
936 switch (info.src_type) {
937 case FMA_FADD:
938 case FMA_FMA:
939 case FMA_FADD16:
940 case FMA_FMA16:
941 dump_round_mode(bits(FMA.op, 10, 12));
942 break;
943 case FMA_FMINMAX:
944 case FMA_FMINMAX16:
945 dump_minmax_mode(bits(FMA.op, 10, 12));
946 break;
947 default:
948 assert(0);
949 }
950 } else if (info.src_type == FMA_FCMP || info.src_type == FMA_FCMP16) {
951 dump_fcmp(bits(FMA.op, 10, 13));
952 if (info.src_type == FMA_FCMP)
953 printf(".f32");
954 else
955 printf(".v2f16");
956 } else if (info.src_type == FMA_FMA_MSCALE) {
957 if (FMA.op & (1 << 11)) {
958 switch ((FMA.op >> 9) & 0x3) {
959 case 0:
960 /* This mode seems to do a few things:
961 * - Makes 0 * infinity (and incidentally 0 * nan) return 0,
962 * since generating a nan would poison the result of
963 * 1/infinity and 1/0.
964 * - Fiddles with which nan is returned in nan * nan,
965 * presumably to make sure that the same exact nan is
966 * returned for 1/nan.
967 */
968 printf(".rcp_mode");
969 break;
970 case 3:
971 /* Similar to the above, but src0 always wins when multiplying
972 * 0 by infinity.
973 */
974 printf(".sqrt_mode");
975 break;
976 default:
977 printf(".unk%d_mode", (int) (FMA.op >> 9) & 0x3);
978 }
979 } else {
980 dump_output_mod(bits(FMA.op, 9, 11));
981 }
982 }
983
984 printf(" ");
985
986 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(next_regs);
987 if (next_ctrl.fma_write_unit != REG_WRITE_NONE) {
988 printf("{R%d, T0}, ", GetRegToWrite(next_ctrl.fma_write_unit, next_regs));
989 } else {
990 printf("T0, ");
991 }
992
993 switch (info.src_type) {
994 case FMA_ONE_SRC:
995 dump_src(FMA.src0, regs, consts, true);
996 break;
997 case FMA_TWO_SRC:
998 dump_src(FMA.src0, regs, consts, true);
999 printf(", ");
1000 dump_src(FMA.op & 0x7, regs, consts, true);
1001 break;
1002 case FMA_FADD:
1003 case FMA_FMINMAX:
1004 if (FMA.op & 0x10)
1005 printf("-");
1006 if (FMA.op & 0x200)
1007 printf("abs(");
1008 dump_src(FMA.src0, regs, consts, true);
1009 dump_fma_expand_src0((FMA.op >> 6) & 0x7);
1010 if (FMA.op & 0x200)
1011 printf(")");
1012 printf(", ");
1013 if (FMA.op & 0x20)
1014 printf("-");
1015 if (FMA.op & 0x8)
1016 printf("abs(");
1017 dump_src(FMA.op & 0x7, regs, consts, true);
1018 dump_fma_expand_src1((FMA.op >> 6) & 0x7);
1019 if (FMA.op & 0x8)
1020 printf(")");
1021 break;
1022 case FMA_FADD16:
1023 case FMA_FMINMAX16: {
1024 bool abs1 = FMA.op & 0x8;
1025 bool abs2 = (FMA.op & 0x7) < FMA.src0;
1026 if (FMA.op & 0x10)
1027 printf("-");
1028 if (abs1 || abs2)
1029 printf("abs(");
1030 dump_src(FMA.src0, regs, consts, true);
1031 dump_16swizzle((FMA.op >> 6) & 0x3);
1032 if (abs1 || abs2)
1033 printf(")");
1034 printf(", ");
1035 if (FMA.op & 0x20)
1036 printf("-");
1037 if (abs1 && abs2)
1038 printf("abs(");
1039 dump_src(FMA.op & 0x7, regs, consts, true);
1040 dump_16swizzle((FMA.op >> 8) & 0x3);
1041 if (abs1 && abs2)
1042 printf(")");
1043 break;
1044 }
1045 case FMA_FCMP:
1046 if (FMA.op & 0x200)
1047 printf("abs(");
1048 dump_src(FMA.src0, regs, consts, true);
1049 dump_fma_expand_src0((FMA.op >> 6) & 0x7);
1050 if (FMA.op & 0x200)
1051 printf(")");
1052 printf(", ");
1053 if (FMA.op & 0x20)
1054 printf("-");
1055 if (FMA.op & 0x8)
1056 printf("abs(");
1057 dump_src(FMA.op & 0x7, regs, consts, true);
1058 dump_fma_expand_src1((FMA.op >> 6) & 0x7);
1059 if (FMA.op & 0x8)
1060 printf(")");
1061 break;
1062 case FMA_FCMP16:
1063 dump_src(FMA.src0, regs, consts, true);
1064 // Note: this is kinda a guess, I haven't seen the blob set this to
1065 // anything other than the identity, but it matches FMA_TWO_SRCFmod16
1066 dump_16swizzle((FMA.op >> 6) & 0x3);
1067 printf(", ");
1068 dump_src(FMA.op & 0x7, regs, consts, true);
1069 dump_16swizzle((FMA.op >> 8) & 0x3);
1070 break;
1071 case FMA_SHIFT_ADD64:
1072 dump_src(FMA.src0, regs, consts, true);
1073 printf(", ");
1074 dump_src(FMA.op & 0x7, regs, consts, true);
1075 printf(", ");
1076 printf("shift:%u", (FMA.op >> 3) & 0x7);
1077 break;
1078 case FMA_THREE_SRC:
1079 dump_src(FMA.src0, regs, consts, true);
1080 printf(", ");
1081 dump_src(FMA.op & 0x7, regs, consts, true);
1082 printf(", ");
1083 dump_src((FMA.op >> 3) & 0x7, regs, consts, true);
1084 break;
1085 case FMA_FMA:
1086 if (FMA.op & (1 << 14))
1087 printf("-");
1088 if (FMA.op & (1 << 9))
1089 printf("abs(");
1090 dump_src(FMA.src0, regs, consts, true);
1091 dump_fma_expand_src0((FMA.op >> 6) & 0x7);
1092 if (FMA.op & (1 << 9))
1093 printf(")");
1094 printf(", ");
1095 if (FMA.op & (1 << 16))
1096 printf("abs(");
1097 dump_src(FMA.op & 0x7, regs, consts, true);
1098 dump_fma_expand_src1((FMA.op >> 6) & 0x7);
1099 if (FMA.op & (1 << 16))
1100 printf(")");
1101 printf(", ");
1102 if (FMA.op & (1 << 15))
1103 printf("-");
1104 if (FMA.op & (1 << 17))
1105 printf("abs(");
1106 dump_src((FMA.op >> 3) & 0x7, regs, consts, true);
1107 if (FMA.op & (1 << 17))
1108 printf(")");
1109 break;
1110 case FMA_FMA16:
1111 if (FMA.op & (1 << 14))
1112 printf("-");
1113 dump_src(FMA.src0, regs, consts, true);
1114 dump_16swizzle((FMA.op >> 6) & 0x3);
1115 printf(", ");
1116 dump_src(FMA.op & 0x7, regs, consts, true);
1117 dump_16swizzle((FMA.op >> 8) & 0x3);
1118 printf(", ");
1119 if (FMA.op & (1 << 15))
1120 printf("-");
1121 dump_src((FMA.op >> 3) & 0x7, regs, consts, true);
1122 dump_16swizzle((FMA.op >> 16) & 0x3);
1123 break;
1124 case FMA_FOUR_SRC:
1125 dump_src(FMA.src0, regs, consts, true);
1126 printf(", ");
1127 dump_src(FMA.op & 0x7, regs, consts, true);
1128 printf(", ");
1129 dump_src((FMA.op >> 3) & 0x7, regs, consts, true);
1130 printf(", ");
1131 dump_src((FMA.op >> 6) & 0x7, regs, consts, true);
1132 break;
1133 case FMA_FMA_MSCALE:
1134 if (FMA.op & (1 << 12))
1135 printf("abs(");
1136 dump_src(FMA.src0, regs, consts, true);
1137 if (FMA.op & (1 << 12))
1138 printf(")");
1139 printf(", ");
1140 if (FMA.op & (1 << 13))
1141 printf("-");
1142 dump_src(FMA.op & 0x7, regs, consts, true);
1143 printf(", ");
1144 if (FMA.op & (1 << 14))
1145 printf("-");
1146 dump_src((FMA.op >> 3) & 0x7, regs, consts, true);
1147 printf(", ");
1148 dump_src((FMA.op >> 6) & 0x7, regs, consts, true);
1149 break;
1150 }
1151 printf("\n");
1152 }
1153
1154 static const struct add_op_info add_op_infos[] = {
1155 { 0x00000, "MAX.f32", ADD_FMINMAX },
1156 { 0x02000, "MIN.f32", ADD_FMINMAX },
1157 { 0x04000, "ADD.f32", ADD_FADD },
1158 { 0x06000, "FCMP.GL", ADD_FCMP },
1159 { 0x07000, "FCMP.D3D", ADD_FCMP },
1160 { 0x07856, "F16_TO_I16", ADD_ONE_SRC },
1161 { 0x07857, "F16_TO_U16", ADD_ONE_SRC },
1162 { 0x078c0, "I16_TO_F16.XX", ADD_ONE_SRC },
1163 { 0x078c1, "U16_TO_F16.XX", ADD_ONE_SRC },
1164 { 0x078c8, "I16_TO_F16.YX", ADD_ONE_SRC },
1165 { 0x078c9, "U16_TO_F16.YX", ADD_ONE_SRC },
1166 { 0x078d0, "I16_TO_F16.XY", ADD_ONE_SRC },
1167 { 0x078d1, "U16_TO_F16.XY", ADD_ONE_SRC },
1168 { 0x078d8, "I16_TO_F16.YY", ADD_ONE_SRC },
1169 { 0x078d9, "U16_TO_F16.YY", ADD_ONE_SRC },
1170 { 0x07936, "F32_TO_I32", ADD_ONE_SRC },
1171 { 0x07937, "F32_TO_U32", ADD_ONE_SRC },
1172 { 0x07978, "I32_TO_F32", ADD_ONE_SRC },
1173 { 0x07979, "U32_TO_F32", ADD_ONE_SRC },
1174 { 0x07998, "I16_TO_I32.X", ADD_ONE_SRC },
1175 { 0x07999, "U16_TO_U32.X", ADD_ONE_SRC },
1176 { 0x0799a, "I16_TO_I32.Y", ADD_ONE_SRC },
1177 { 0x0799b, "U16_TO_U32.Y", ADD_ONE_SRC },
1178 { 0x0799c, "I16_TO_F32.X", ADD_ONE_SRC },
1179 { 0x0799d, "U16_TO_F32.X", ADD_ONE_SRC },
1180 { 0x0799e, "I16_TO_F32.Y", ADD_ONE_SRC },
1181 { 0x0799f, "U16_TO_F32.Y", ADD_ONE_SRC },
1182 // take the low 16 bits, and expand it to a 32-bit float
1183 { 0x079a2, "F16_TO_F32.X", ADD_ONE_SRC },
1184 // take the high 16 bits, ...
1185 { 0x079a3, "F16_TO_F32.Y", ADD_ONE_SRC },
1186 { 0x07b2b, "SWZ.YX.v2i16", ADD_ONE_SRC },
1187 { 0x07b2c, "NOP", ADD_ONE_SRC },
1188 { 0x07b29, "SWZ.XX.v2i16", ADD_ONE_SRC },
1189 // Logically, this should be SWZ.XY, but that's equivalent to a move, and
1190 // this seems to be the canonical way the blob generates a MOV.
1191 { 0x07b2d, "MOV", ADD_ONE_SRC },
1192 { 0x07b2f, "SWZ.YY.v2i16", ADD_ONE_SRC },
1193 // Given a floating point number m * 2^e, returns m ^ 2^{-1}.
1194 { 0x07b65, "FRCP_FREXPM", ADD_ONE_SRC },
1195 { 0x07b75, "FSQRT_FREXPM", ADD_ONE_SRC },
1196 { 0x07b8d, "FRCP_FREXPE", ADD_ONE_SRC },
1197 { 0x07ba5, "FSQRT_FREXPE", ADD_ONE_SRC },
1198 { 0x07bad, "FRSQ_FREXPE", ADD_ONE_SRC },
1199 // From the ARM patent US20160364209A1:
1200 // "Decompose v (the input) into numbers x1 and s such that v = x1 * 2^s,
1201 // and x1 is a floating point value in a predetermined range where the
1202 // value 1 is within the range and not at one extremity of the range (e.g.
1203 // choose a range where 1 is towards middle of range)."
1204 //
1205 // This computes s.
1206 { 0x07bc5, "FLOG_FREXPE", ADD_ONE_SRC },
1207 { 0x07d45, "CEIL", ADD_ONE_SRC },
1208 { 0x07d85, "FLOOR", ADD_ONE_SRC },
1209 { 0x07dc5, "TRUNC", ADD_ONE_SRC },
1210 { 0x07f18, "LSHIFT_ADD_HIGH32.i32", ADD_TWO_SRC },
1211 { 0x08000, "LD_ATTR.f16", ADD_LOAD_ATTR, true },
1212 { 0x08100, "LD_ATTR.v2f16", ADD_LOAD_ATTR, true },
1213 { 0x08200, "LD_ATTR.v3f16", ADD_LOAD_ATTR, true },
1214 { 0x08300, "LD_ATTR.v4f16", ADD_LOAD_ATTR, true },
1215 { 0x08400, "LD_ATTR.f32", ADD_LOAD_ATTR, true },
1216 { 0x08500, "LD_ATTR.v3f32", ADD_LOAD_ATTR, true },
1217 { 0x08600, "LD_ATTR.v3f32", ADD_LOAD_ATTR, true },
1218 { 0x08700, "LD_ATTR.v4f32", ADD_LOAD_ATTR, true },
1219 { 0x08800, "LD_ATTR.i32", ADD_LOAD_ATTR, true },
1220 { 0x08900, "LD_ATTR.v3i32", ADD_LOAD_ATTR, true },
1221 { 0x08a00, "LD_ATTR.v3i32", ADD_LOAD_ATTR, true },
1222 { 0x08b00, "LD_ATTR.v4i32", ADD_LOAD_ATTR, true },
1223 { 0x08c00, "LD_ATTR.u32", ADD_LOAD_ATTR, true },
1224 { 0x08d00, "LD_ATTR.v3u32", ADD_LOAD_ATTR, true },
1225 { 0x08e00, "LD_ATTR.v3u32", ADD_LOAD_ATTR, true },
1226 { 0x08f00, "LD_ATTR.v4u32", ADD_LOAD_ATTR, true },
1227 { 0x0a000, "LD_VAR.32", ADD_VARYING_INTERP, true },
1228 { 0x0b000, "TEX", ADD_TEX_COMPACT, true },
1229 { 0x0c188, "LOAD.i32", ADD_TWO_SRC, true },
1230 { 0x0c1a0, "LD_UBO.i32", ADD_TWO_SRC, true },
1231 { 0x0c1b8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1232 { 0x0c1c8, "LOAD.v2i32", ADD_TWO_SRC, true },
1233 { 0x0c1e0, "LD_UBO.v2i32", ADD_TWO_SRC, true },
1234 { 0x0c1f8, "LD_SCRATCH.v2i32", ADD_TWO_SRC, true },
1235 { 0x0c208, "LOAD.v4i32", ADD_TWO_SRC, true },
1236 // src0 = offset, src1 = binding
1237 { 0x0c220, "LD_UBO.v4i32", ADD_TWO_SRC, true },
1238 { 0x0c238, "LD_SCRATCH.v4i32", ADD_TWO_SRC, true },
1239 { 0x0c248, "STORE.v4i32", ADD_TWO_SRC, true },
1240 { 0x0c278, "ST_SCRATCH.v4i32", ADD_TWO_SRC, true },
1241 { 0x0c588, "STORE.i32", ADD_TWO_SRC, true },
1242 { 0x0c5b8, "ST_SCRATCH.i32", ADD_TWO_SRC, true },
1243 { 0x0c5c8, "STORE.v2i32", ADD_TWO_SRC, true },
1244 { 0x0c5f8, "ST_SCRATCH.v2i32", ADD_TWO_SRC, true },
1245 { 0x0c648, "LOAD.u16", ADD_TWO_SRC, true }, // zero-extends
1246 { 0x0ca88, "LOAD.v3i32", ADD_TWO_SRC, true },
1247 { 0x0caa0, "LD_UBO.v3i32", ADD_TWO_SRC, true },
1248 { 0x0cab8, "LD_SCRATCH.v3i32", ADD_TWO_SRC, true },
1249 { 0x0cb88, "STORE.v3i32", ADD_TWO_SRC, true },
1250 { 0x0cbb8, "ST_SCRATCH.v3i32", ADD_TWO_SRC, true },
1251 // *_FAST does not exist on G71 (added to G51, G72, and everything after)
1252 { 0x0cc00, "FRCP_FAST.f32", ADD_ONE_SRC },
1253 { 0x0cc20, "FRSQ_FAST.f32", ADD_ONE_SRC },
1254 // Given a floating point number m * 2^e, produces a table-based
1255 // approximation of 2/m using the top 17 bits. Includes special cases for
1256 // infinity, NaN, and zero, and copies the sign bit.
1257 { 0x0ce00, "FRCP_TABLE", ADD_ONE_SRC },
1258 // Exists on G71
1259 { 0x0ce10, "FRCP_FAST.f16.X", ADD_ONE_SRC },
1260 // A similar table for inverse square root, using the high 17 bits of the
1261 // mantissa as well as the low bit of the exponent.
1262 { 0x0ce20, "FRSQ_TABLE", ADD_ONE_SRC },
1263 { 0x0ce30, "FRCP_FAST.f16.Y", ADD_ONE_SRC },
1264 { 0x0ce50, "FRSQ_FAST.f16.X", ADD_ONE_SRC },
1265 // Used in the argument reduction for log. Given a floating-point number
1266 // m * 2^e, uses the top 4 bits of m to produce an approximation to 1/m
1267 // with the exponent forced to 0 and only the top 5 bits are nonzero. 0,
1268 // infinity, and NaN all return 1.0.
1269 // See the ARM patent for more information.
1270 { 0x0ce60, "FRCP_APPROX", ADD_ONE_SRC },
1271 { 0x0ce70, "FRSQ_FAST.f16.Y", ADD_ONE_SRC },
1272 { 0x0cf40, "ATAN_ASSIST", ADD_TWO_SRC },
1273 { 0x0cf48, "ATAN_TABLE", ADD_TWO_SRC },
1274 { 0x0cf50, "SIN_TABLE", ADD_ONE_SRC },
1275 { 0x0cf51, "COS_TABLE", ADD_ONE_SRC },
1276 { 0x0cf58, "EXP_TABLE", ADD_ONE_SRC },
1277 { 0x0cf60, "FLOG2_TABLE", ADD_ONE_SRC },
1278 { 0x0cf64, "FLOGE_TABLE", ADD_ONE_SRC },
1279 { 0x0d000, "BRANCH", ADD_BRANCH },
1280 // For each bit i, return src2[i] ? src0[i] : src1[i]. In other words, this
1281 // is the same as (src2 & src0) | (~src2 & src1).
1282 { 0x0e8c0, "MUX", ADD_THREE_SRC },
1283 { 0x0e9b0, "ATAN_LDEXP.Y.f32", ADD_TWO_SRC },
1284 { 0x0e9b8, "ATAN_LDEXP.X.f32", ADD_TWO_SRC },
1285 { 0x0ea60, "SEL.XX.i16", ADD_TWO_SRC },
1286 { 0x0ea70, "SEL.XY.i16", ADD_TWO_SRC },
1287 { 0x0ea68, "SEL.YX.i16", ADD_TWO_SRC },
1288 { 0x0ea78, "SEL.YY.i16", ADD_TWO_SRC },
1289 { 0x0ec00, "F32_TO_F16", ADD_TWO_SRC },
1290 { 0x0f640, "ICMP.GL.GT", ADD_TWO_SRC }, // src0 > src1 ? 1 : 0
1291 { 0x0f648, "ICMP.GL.GE", ADD_TWO_SRC },
1292 { 0x0f650, "UCMP.GL.GT", ADD_TWO_SRC },
1293 { 0x0f658, "UCMP.GL.GE", ADD_TWO_SRC },
1294 { 0x0f660, "ICMP.GL.EQ", ADD_TWO_SRC },
1295 { 0x0f6c0, "ICMP.D3D.GT", ADD_TWO_SRC }, // src0 > src1 ? ~0 : 0
1296 { 0x0f6c8, "ICMP.D3D.GE", ADD_TWO_SRC },
1297 { 0x0f6d0, "UCMP.D3D.GT", ADD_TWO_SRC },
1298 { 0x0f6d8, "UCMP.D3D.GE", ADD_TWO_SRC },
1299 { 0x0f6e0, "ICMP.D3D.EQ", ADD_TWO_SRC },
1300 { 0x10000, "MAX.v2f16", ADD_FMINMAX16 },
1301 { 0x11000, "ADD_MSCALE.f32", ADD_FADDMscale },
1302 { 0x12000, "MIN.v2f16", ADD_FMINMAX16 },
1303 { 0x14000, "ADD.v2f16", ADD_FADD16 },
1304 { 0x17000, "FCMP.D3D", ADD_FCMP16 },
1305 { 0x178c0, "ADD.i32", ADD_TWO_SRC },
1306 { 0x17900, "ADD.v2i16", ADD_TWO_SRC },
1307 { 0x17ac0, "SUB.i32", ADD_TWO_SRC },
1308 { 0x17c10, "ADDC.i32", ADD_TWO_SRC }, // adds src0 to the bottom bit of src1
1309 { 0x17d80, "ADD.i32.i16.X", ADD_TWO_SRC },
1310 { 0x17d90, "ADD.i32.u16.X", ADD_TWO_SRC },
1311 { 0x17dc0, "ADD.i32.i16.Y", ADD_TWO_SRC },
1312 { 0x17dd0, "ADD.i32.u16.Y", ADD_TWO_SRC },
1313 // Compute varying address and datatype (for storing in the vertex shader),
1314 // and store the vec3 result in the data register. The result is passed as
1315 // the 3 normal arguments to ST_VAR.
1316 { 0x18000, "LD_VAR_ADDR.f16", ADD_VARYING_ADDRESS, true },
1317 { 0x18100, "LD_VAR_ADDR.f32", ADD_VARYING_ADDRESS, true },
1318 { 0x18200, "LD_VAR_ADDR.i32", ADD_VARYING_ADDRESS, true },
1319 { 0x18300, "LD_VAR_ADDR.u32", ADD_VARYING_ADDRESS, true },
1320 // Implements alpha-to-coverage, as well as possibly the late depth and
1321 // stencil tests. The first source is the existing sample mask in R60
1322 // (possibly modified by gl_SampleMask), and the second source is the alpha
1323 // value. The sample mask is written right away based on the
1324 // alpha-to-coverage result using the normal register write mechanism,
1325 // since that doesn't need to read from any memory, and then written again
1326 // later based on the result of the stencil and depth tests using the
1327 // special register.
1328 { 0x191e8, "ATEST.f32", ADD_TWO_SRC, true },
1329 { 0x191f0, "ATEST.X.f16", ADD_TWO_SRC, true },
1330 { 0x191f8, "ATEST.Y.f16", ADD_TWO_SRC, true },
1331 // store a varying given the address and datatype from LD_VAR_ADDR
1332 { 0x19300, "ST_VAR.v1", ADD_THREE_SRC, true },
1333 { 0x19340, "ST_VAR.v2", ADD_THREE_SRC, true },
1334 { 0x19380, "ST_VAR.v3", ADD_THREE_SRC, true },
1335 { 0x193c0, "ST_VAR.v4", ADD_THREE_SRC, true },
1336 // This takes the sample coverage mask (computed by ATEST above) as a
1337 // regular argument, in addition to the vec4 color in the special register.
1338 { 0x1952c, "BLEND", ADD_BLENDING, true },
1339 { 0x1a000, "LD_VAR.16", ADD_VARYING_INTERP, true },
1340 { 0x1ae60, "TEX", ADD_TEX, true },
1341 { 0x1c000, "RSHIFT_NAND.i32", ADD_THREE_SRC },
1342 { 0x1c300, "RSHIFT_OR.i32", ADD_THREE_SRC },
1343 { 0x1c400, "RSHIFT_AND.i32", ADD_THREE_SRC },
1344 { 0x1c700, "RSHIFT_NOR.i32", ADD_THREE_SRC },
1345 { 0x1c800, "LSHIFT_NAND.i32", ADD_THREE_SRC },
1346 { 0x1cb00, "LSHIFT_OR.i32", ADD_THREE_SRC },
1347 { 0x1cc00, "LSHIFT_AND.i32", ADD_THREE_SRC },
1348 { 0x1cf00, "LSHIFT_NOR.i32", ADD_THREE_SRC },
1349 { 0x1d000, "RSHIFT_XOR.i32", ADD_THREE_SRC },
1350 { 0x1d100, "RSHIFT_XNOR.i32", ADD_THREE_SRC },
1351 { 0x1d200, "LSHIFT_XOR.i32", ADD_THREE_SRC },
1352 { 0x1d300, "LSHIFT_XNOR.i32", ADD_THREE_SRC },
1353 { 0x1d400, "LSHIFT_ADD.i32", ADD_THREE_SRC },
1354 { 0x1d500, "LSHIFT_SUB.i32", ADD_THREE_SRC },
1355 { 0x1d500, "LSHIFT_RSUB.i32", ADD_THREE_SRC },
1356 { 0x1d700, "RSHIFT_ADD.i32", ADD_THREE_SRC },
1357 { 0x1d800, "RSHIFT_SUB.i32", ADD_THREE_SRC },
1358 { 0x1d900, "RSHIFT_RSUB.i32", ADD_THREE_SRC },
1359 { 0x1da00, "ARSHIFT_ADD.i32", ADD_THREE_SRC },
1360 { 0x1db00, "ARSHIFT_SUB.i32", ADD_THREE_SRC },
1361 { 0x1dc00, "ARSHIFT_RSUB.i32", ADD_THREE_SRC },
1362 { 0x1dd18, "OR.i32", ADD_TWO_SRC },
1363 { 0x1dd20, "AND.i32", ADD_TWO_SRC },
1364 { 0x1dd60, "LSHIFT.i32", ADD_TWO_SRC },
1365 { 0x1dd50, "XOR.i32", ADD_TWO_SRC },
1366 { 0x1dd80, "RSHIFT.i32", ADD_TWO_SRC },
1367 { 0x1dda0, "ARSHIFT.i32", ADD_TWO_SRC },
1368 };
1369
1370 static struct add_op_info find_add_op_info(unsigned op)
1371 {
1372 for (unsigned i = 0; i < ARRAY_SIZE(add_op_infos); i++) {
1373 unsigned opCmp = ~0;
1374 switch (add_op_infos[i].src_type) {
1375 case ADD_ONE_SRC:
1376 case ADD_BLENDING:
1377 opCmp = op;
1378 break;
1379 case ADD_TWO_SRC:
1380 opCmp = op & ~0x7;
1381 break;
1382 case ADD_THREE_SRC:
1383 opCmp = op & ~0x3f;
1384 break;
1385 case ADD_TEX:
1386 opCmp = op & ~0xf;
1387 break;
1388 case ADD_FADD:
1389 case ADD_FMINMAX:
1390 case ADD_FADD16:
1391 opCmp = op & ~0x1fff;
1392 break;
1393 case ADD_FMINMAX16:
1394 case ADD_FADDMscale:
1395 opCmp = op & ~0xfff;
1396 break;
1397 case ADD_FCMP:
1398 case ADD_FCMP16:
1399 opCmp = op & ~0x7ff;
1400 break;
1401 case ADD_TEX_COMPACT:
1402 opCmp = op & ~0x3ff;
1403 break;
1404 case ADD_VARYING_INTERP:
1405 opCmp = op & ~0x7ff;
1406 break;
1407 case ADD_VARYING_ADDRESS:
1408 opCmp = op & ~0xff;
1409 break;
1410 case ADD_LOAD_ATTR:
1411 opCmp = op & ~0x7f;
1412 break;
1413 case ADD_BRANCH:
1414 opCmp = op & ~0xfff;
1415 break;
1416 default:
1417 opCmp = ~0;
1418 break;
1419 }
1420 if (add_op_infos[i].op == opCmp)
1421 return add_op_infos[i];
1422 }
1423
1424 struct add_op_info info;
1425 snprintf(info.name, sizeof(info.name), "op%04x", op);
1426 info.op = op;
1427 info.src_type = ADD_TWO_SRC;
1428 info.has_data_reg = true;
1429 return info;
1430 }
1431
1432 static void dump_add(uint64_t word, struct bifrost_regs regs, struct bifrost_regs next_regs, uint64_t *consts,
1433 unsigned data_reg, unsigned offset, bool verbose)
1434 {
1435 if (verbose) {
1436 printf("# ADD: %016" PRIx64 "\n", word);
1437 }
1438 struct bifrost_add_inst ADD;
1439 memcpy((char *) &ADD, (char *) &word, sizeof(ADD));
1440 struct add_op_info info = find_add_op_info(ADD.op);
1441
1442 printf("%s", info.name);
1443
1444 // float16 seems like it doesn't support output modifiers
1445 if (info.src_type == ADD_FADD || info.src_type == ADD_FMINMAX) {
1446 // output modifiers
1447 dump_output_mod(bits(ADD.op, 8, 10));
1448 if (info.src_type == ADD_FADD)
1449 dump_round_mode(bits(ADD.op, 10, 12));
1450 else
1451 dump_minmax_mode(bits(ADD.op, 10, 12));
1452 } else if (info.src_type == ADD_FCMP || info.src_type == ADD_FCMP16) {
1453 dump_fcmp(bits(ADD.op, 3, 6));
1454 if (info.src_type == ADD_FCMP)
1455 printf(".f32");
1456 else
1457 printf(".v2f16");
1458 } else if (info.src_type == ADD_FADDMscale) {
1459 switch ((ADD.op >> 6) & 0x7) {
1460 case 0:
1461 break;
1462 // causes GPU hangs on G71
1463 case 1:
1464 printf(".invalid");
1465 break;
1466 // Same as usual outmod value.
1467 case 2:
1468 printf(".clamp_0_1");
1469 break;
1470 // If src0 is infinite or NaN, flush it to zero so that the other
1471 // source is passed through unmodified.
1472 case 3:
1473 printf(".flush_src0_inf_nan");
1474 break;
1475 // Vice versa.
1476 case 4:
1477 printf(".flush_src1_inf_nan");
1478 break;
1479 // Every other case seems to behave the same as the above?
1480 default:
1481 printf(".unk%d", (ADD.op >> 6) & 0x7);
1482 break;
1483 }
1484 } else if (info.src_type == ADD_VARYING_INTERP) {
1485 if (ADD.op & 0x200)
1486 printf(".reuse");
1487 if (ADD.op & 0x400)
1488 printf(".flat");
1489 switch ((ADD.op >> 7) & 0x3) {
1490 case 0:
1491 printf(".per_frag");
1492 break;
1493 case 1:
1494 printf(".centroid");
1495 break;
1496 case 2:
1497 break;
1498 case 3:
1499 printf(".explicit");
1500 break;
1501 }
1502 printf(".v%d", ((ADD.op >> 5) & 0x3) + 1);
1503 } else if (info.src_type == ADD_BRANCH) {
1504 enum branch_code branchCode = (enum branch_code) ((ADD.op >> 6) & 0x3f);
1505 if (branchCode == BR_ALWAYS) {
1506 // unconditional branch
1507 } else {
1508 enum branch_cond cond = (enum branch_cond) ((ADD.op >> 6) & 0x7);
1509 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1510 bool portSwapped = (ADD.op & 0x7) < ADD.src0;
1511 // See the comment in branch_bit_size
1512 if (size == BR_SIZE_16YX0)
1513 portSwapped = true;
1514 if (size == BR_SIZE_16YX1)
1515 portSwapped = false;
1516 // These sizes are only for floating point comparisons, so the
1517 // non-floating-point comparisons are reused to encode the flipped
1518 // versions.
1519 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y)
1520 portSwapped = false;
1521 // There's only one argument, so we reuse the extra argument to
1522 // encode this.
1523 if (size == BR_SIZE_ZERO)
1524 portSwapped = !(ADD.op & 1);
1525
1526 switch (cond) {
1527 case BR_COND_LT:
1528 if (portSwapped)
1529 printf(".LT.u");
1530 else
1531 printf(".LT.i");
1532 break;
1533 case BR_COND_LE:
1534 if (size == BR_SIZE_32_AND_16X || size == BR_SIZE_32_AND_16Y) {
1535 printf(".UNE.f");
1536 } else {
1537 if (portSwapped)
1538 printf(".LE.u");
1539 else
1540 printf(".LE.i");
1541 }
1542 break;
1543 case BR_COND_GT:
1544 if (portSwapped)
1545 printf(".GT.u");
1546 else
1547 printf(".GT.i");
1548 break;
1549 case BR_COND_GE:
1550 if (portSwapped)
1551 printf(".GE.u");
1552 else
1553 printf(".GE.i");
1554 break;
1555 case BR_COND_EQ:
1556 if (portSwapped)
1557 printf(".NE.i");
1558 else
1559 printf(".EQ.i");
1560 break;
1561 case BR_COND_OEQ:
1562 if (portSwapped)
1563 printf(".UNE.f");
1564 else
1565 printf(".OEQ.f");
1566 break;
1567 case BR_COND_OGT:
1568 if (portSwapped)
1569 printf(".OGT.unk.f");
1570 else
1571 printf(".OGT.f");
1572 break;
1573 case BR_COND_OLT:
1574 if (portSwapped)
1575 printf(".OLT.unk.f");
1576 else
1577 printf(".OLT.f");
1578 break;
1579 }
1580 switch (size) {
1581 case BR_SIZE_32:
1582 case BR_SIZE_32_AND_16X:
1583 case BR_SIZE_32_AND_16Y:
1584 printf("32");
1585 break;
1586 case BR_SIZE_16XX:
1587 case BR_SIZE_16YY:
1588 case BR_SIZE_16YX0:
1589 case BR_SIZE_16YX1:
1590 printf("16");
1591 break;
1592 case BR_SIZE_ZERO: {
1593 unsigned ctrl = (ADD.op >> 1) & 0x3;
1594 if (ctrl == 0)
1595 printf("32.Z");
1596 else
1597 printf("16.Z");
1598 break;
1599 }
1600 }
1601 }
1602 }
1603 printf(" ");
1604
1605 struct bifrost_reg_ctrl next_ctrl = DecodeRegCtrl(next_regs);
1606 if (next_ctrl.add_write_unit != REG_WRITE_NONE) {
1607 printf("{R%d, T1}, ", GetRegToWrite(next_ctrl.add_write_unit, next_regs));
1608 } else {
1609 printf("T1, ");
1610 }
1611
1612 switch (info.src_type) {
1613 case ADD_BLENDING:
1614 // Note: in this case, regs.uniform_const == location | 0x8
1615 // This probably means we can't load uniforms or immediates in the
1616 // same instruction. This re-uses the encoding that normally means
1617 // "disabled", where the low 4 bits are ignored. Perhaps the extra
1618 // 0x8 or'd in indicates this is happening.
1619 printf("location:%d, ", regs.uniform_const & 0x7);
1620 // fallthrough
1621 case ADD_ONE_SRC:
1622 dump_src(ADD.src0, regs, consts, false);
1623 break;
1624 case ADD_TEX:
1625 case ADD_TEX_COMPACT: {
1626 int tex_index;
1627 int sampler_index;
1628 bool dualTex = false;
1629 if (info.src_type == ADD_TEX_COMPACT) {
1630 tex_index = (ADD.op >> 3) & 0x7;
1631 sampler_index = (ADD.op >> 7) & 0x7;
1632 bool unknown = (ADD.op & 0x40);
1633 // TODO: figure out if the unknown bit is ever 0
1634 if (!unknown)
1635 printf("unknown ");
1636 } else {
1637 uint64_t constVal = get_const(consts, regs);
1638 uint32_t controlBits = (ADD.op & 0x8) ? (constVal >> 32) : constVal;
1639 struct bifrost_tex_ctrl ctrl;
1640 memcpy((char *) &ctrl, (char *) &controlBits, sizeof(ctrl));
1641
1642 // TODO: figure out what actually triggers dual-tex
1643 if (ctrl.result_type == 9) {
1644 struct bifrost_dual_tex_ctrl dualCtrl;
1645 memcpy((char *) &dualCtrl, (char *) &controlBits, sizeof(ctrl));
1646 printf("(dualtex) tex0:%d samp0:%d tex1:%d samp1:%d ",
1647 dualCtrl.tex_index0, dualCtrl.sampler_index0,
1648 dualCtrl.tex_index1, dualCtrl.sampler_index1);
1649 if (dualCtrl.unk0 != 3)
1650 printf("unk:%d ", dualCtrl.unk0);
1651 dualTex = true;
1652 } else {
1653 if (ctrl.no_merge_index) {
1654 tex_index = ctrl.tex_index;
1655 sampler_index = ctrl.sampler_index;
1656 } else {
1657 tex_index = sampler_index = ctrl.tex_index;
1658 unsigned unk = ctrl.sampler_index >> 2;
1659 if (unk != 3)
1660 printf("unk:%d ", unk);
1661 if (ctrl.sampler_index & 1)
1662 tex_index = -1;
1663 if (ctrl.sampler_index & 2)
1664 sampler_index = -1;
1665 }
1666
1667 if (ctrl.unk0 != 3)
1668 printf("unk0:%d ", ctrl.unk0);
1669 if (ctrl.unk1)
1670 printf("unk1 ");
1671 if (ctrl.unk2 != 0xf)
1672 printf("unk2:%x ", ctrl.unk2);
1673
1674 switch (ctrl.result_type) {
1675 case 0x4:
1676 printf("f32 ");
1677 break;
1678 case 0xe:
1679 printf("i32 ");
1680 break;
1681 case 0xf:
1682 printf("u32 ");
1683 break;
1684 default:
1685 printf("unktype(%x) ", ctrl.result_type);
1686 }
1687
1688 switch (ctrl.tex_type) {
1689 case 0:
1690 printf("cube ");
1691 break;
1692 case 1:
1693 printf("buffer ");
1694 break;
1695 case 2:
1696 printf("2D ");
1697 break;
1698 case 3:
1699 printf("3D ");
1700 break;
1701 }
1702
1703 if (ctrl.is_shadow)
1704 printf("shadow ");
1705 if (ctrl.is_array)
1706 printf("array ");
1707
1708 if (!ctrl.filter) {
1709 if (ctrl.calc_gradients) {
1710 int comp = (controlBits >> 20) & 0x3;
1711 printf("txg comp:%d ", comp);
1712 } else {
1713 printf("txf ");
1714 }
1715 } else {
1716 if (!ctrl.not_supply_lod) {
1717 if (ctrl.compute_lod)
1718 printf("lod_bias ");
1719 else
1720 printf("lod ");
1721 }
1722
1723 if (!ctrl.calc_gradients)
1724 printf("grad ");
1725 }
1726
1727 if (ctrl.texel_offset)
1728 printf("offset ");
1729 }
1730 }
1731
1732 if (!dualTex) {
1733 if (tex_index == -1)
1734 printf("tex:indirect ");
1735 else
1736 printf("tex:%d ", tex_index);
1737
1738 if (sampler_index == -1)
1739 printf("samp:indirect ");
1740 else
1741 printf("samp:%d ", sampler_index);
1742 }
1743 break;
1744 }
1745 case ADD_VARYING_INTERP: {
1746 unsigned addr = ADD.op & 0x1f;
1747 if (addr < 0b10100) {
1748 // direct addr
1749 printf("%d", addr);
1750 } else if (addr < 0b11000) {
1751 if (addr == 22)
1752 printf("fragw");
1753 else if (addr == 23)
1754 printf("fragz");
1755 else
1756 printf("unk%d", addr);
1757 } else {
1758 dump_src(ADD.op & 0x7, regs, consts, false);
1759 }
1760 printf(", ");
1761 dump_src(ADD.src0, regs, consts, false);
1762 break;
1763 }
1764 case ADD_VARYING_ADDRESS: {
1765 dump_src(ADD.src0, regs, consts, false);
1766 printf(", ");
1767 dump_src(ADD.op & 0x7, regs, consts, false);
1768 printf(", ");
1769 unsigned location = (ADD.op >> 3) & 0x1f;
1770 if (location < 16) {
1771 printf("location:%d", location);
1772 } else if (location == 20) {
1773 printf("location:%u", (uint32_t) get_const(consts, regs));
1774 } else if (location == 21) {
1775 printf("location:%u", (uint32_t) (get_const(consts, regs) >> 32));
1776 } else {
1777 printf("location:%d(unk)", location);
1778 }
1779 break;
1780 }
1781 case ADD_LOAD_ATTR:
1782 printf("location:%d, ", (ADD.op >> 3) & 0xf);
1783 case ADD_TWO_SRC:
1784 dump_src(ADD.src0, regs, consts, false);
1785 printf(", ");
1786 dump_src(ADD.op & 0x7, regs, consts, false);
1787 break;
1788 case ADD_THREE_SRC:
1789 dump_src(ADD.src0, regs, consts, false);
1790 printf(", ");
1791 dump_src(ADD.op & 0x7, regs, consts, false);
1792 printf(", ");
1793 dump_src((ADD.op >> 3) & 0x7, regs, consts, false);
1794 break;
1795 case ADD_FADD:
1796 case ADD_FMINMAX:
1797 if (ADD.op & 0x10)
1798 printf("-");
1799 if (ADD.op & 0x1000)
1800 printf("abs(");
1801 dump_src(ADD.src0, regs, consts, false);
1802 switch ((ADD.op >> 6) & 0x3) {
1803 case 3:
1804 printf(".x");
1805 break;
1806 default:
1807 break;
1808 }
1809 if (ADD.op & 0x1000)
1810 printf(")");
1811 printf(", ");
1812 if (ADD.op & 0x20)
1813 printf("-");
1814 if (ADD.op & 0x8)
1815 printf("abs(");
1816 dump_src(ADD.op & 0x7, regs, consts, false);
1817 switch ((ADD.op >> 6) & 0x3) {
1818 case 1:
1819 case 3:
1820 printf(".x");
1821 break;
1822 case 2:
1823 printf(".y");
1824 break;
1825 case 0:
1826 break;
1827 default:
1828 printf(".unk");
1829 break;
1830 }
1831 if (ADD.op & 0x8)
1832 printf(")");
1833 break;
1834 case ADD_FADD16:
1835 if (ADD.op & 0x10)
1836 printf("-");
1837 if (ADD.op & 0x1000)
1838 printf("abs(");
1839 dump_src(ADD.src0, regs, consts, false);
1840 if (ADD.op & 0x1000)
1841 printf(")");
1842 dump_16swizzle((ADD.op >> 6) & 0x3);
1843 printf(", ");
1844 if (ADD.op & 0x20)
1845 printf("-");
1846 if (ADD.op & 0x8)
1847 printf("abs(");
1848 dump_src(ADD.op & 0x7, regs, consts, false);
1849 dump_16swizzle((ADD.op >> 8) & 0x3);
1850 if (ADD.op & 0x8)
1851 printf(")");
1852 break;
1853 case ADD_FMINMAX16: {
1854 bool abs1 = ADD.op & 0x8;
1855 bool abs2 = (ADD.op & 0x7) < ADD.src0;
1856 if (ADD.op & 0x10)
1857 printf("-");
1858 if (abs1 || abs2)
1859 printf("abs(");
1860 dump_src(ADD.src0, regs, consts, false);
1861 dump_16swizzle((ADD.op >> 6) & 0x3);
1862 if (abs1 || abs2)
1863 printf(")");
1864 printf(", ");
1865 if (ADD.op & 0x20)
1866 printf("-");
1867 if (abs1 && abs2)
1868 printf("abs(");
1869 dump_src(ADD.op & 0x7, regs, consts, false);
1870 dump_16swizzle((ADD.op >> 8) & 0x3);
1871 if (abs1 && abs2)
1872 printf(")");
1873 break;
1874 }
1875 case ADD_FADDMscale: {
1876 if (ADD.op & 0x400)
1877 printf("-");
1878 if (ADD.op & 0x200)
1879 printf("abs(");
1880 dump_src(ADD.src0, regs, consts, false);
1881 if (ADD.op & 0x200)
1882 printf(")");
1883
1884 printf(", ");
1885
1886 if (ADD.op & 0x800)
1887 printf("-");
1888 dump_src(ADD.op & 0x7, regs, consts, false);
1889
1890 printf(", ");
1891
1892 dump_src((ADD.op >> 3) & 0x7, regs, consts, false);
1893 break;
1894 }
1895 case ADD_FCMP:
1896 if (ADD.op & 0x400) {
1897 printf("-");
1898 }
1899 if (ADD.op & 0x100) {
1900 printf("abs(");
1901 }
1902 dump_src(ADD.src0, regs, consts, false);
1903 switch ((ADD.op >> 6) & 0x3) {
1904 case 3:
1905 printf(".x");
1906 break;
1907 default:
1908 break;
1909 }
1910 if (ADD.op & 0x100) {
1911 printf(")");
1912 }
1913 printf(", ");
1914 if (ADD.op & 0x200) {
1915 printf("abs(");
1916 }
1917 dump_src(ADD.op & 0x7, regs, consts, false);
1918 switch ((ADD.op >> 6) & 0x3) {
1919 case 1:
1920 case 3:
1921 printf(".x");
1922 break;
1923 case 2:
1924 printf(".y");
1925 break;
1926 case 0:
1927 break;
1928 default:
1929 printf(".unk");
1930 break;
1931 }
1932 if (ADD.op & 0x200) {
1933 printf(")");
1934 }
1935 break;
1936 case ADD_FCMP16:
1937 dump_src(ADD.src0, regs, consts, false);
1938 dump_16swizzle((ADD.op >> 6) & 0x3);
1939 printf(", ");
1940 dump_src(ADD.op & 0x7, regs, consts, false);
1941 dump_16swizzle((ADD.op >> 8) & 0x3);
1942 break;
1943 case ADD_BRANCH: {
1944 enum branch_code code = (enum branch_code) ((ADD.op >> 6) & 0x3f);
1945 enum branch_bit_size size = (enum branch_bit_size) ((ADD.op >> 9) & 0x7);
1946 if (code != BR_ALWAYS) {
1947 dump_src(ADD.src0, regs, consts, false);
1948 switch (size) {
1949 case BR_SIZE_16XX:
1950 printf(".x");
1951 break;
1952 case BR_SIZE_16YY:
1953 case BR_SIZE_16YX0:
1954 case BR_SIZE_16YX1:
1955 printf(".y");
1956 break;
1957 case BR_SIZE_ZERO: {
1958 unsigned ctrl = (ADD.op >> 1) & 0x3;
1959 switch (ctrl) {
1960 case 1:
1961 printf(".y");
1962 break;
1963 case 2:
1964 printf(".x");
1965 break;
1966 default:
1967 break;
1968 }
1969 }
1970 default:
1971 break;
1972 }
1973 printf(", ");
1974 }
1975 if (code != BR_ALWAYS && size != BR_SIZE_ZERO) {
1976 dump_src(ADD.op & 0x7, regs, consts, false);
1977 switch (size) {
1978 case BR_SIZE_16XX:
1979 case BR_SIZE_16YX0:
1980 case BR_SIZE_16YX1:
1981 case BR_SIZE_32_AND_16X:
1982 printf(".x");
1983 break;
1984 case BR_SIZE_16YY:
1985 case BR_SIZE_32_AND_16Y:
1986 printf(".y");
1987 break;
1988 default:
1989 break;
1990 }
1991 printf(", ");
1992 }
1993 // I haven't had the chance to test if this actually specifies the
1994 // branch offset, since I couldn't get it to produce values other
1995 // than 5 (uniform/const high), but these three bits are always
1996 // consistent across branch instructions, so it makes sense...
1997 int offsetSrc = (ADD.op >> 3) & 0x7;
1998 if (offsetSrc == 4 || offsetSrc == 5) {
1999 // If the offset is known/constant, we can decode it
2000 uint32_t raw_offset;
2001 if (offsetSrc == 4)
2002 raw_offset = get_const(consts, regs);
2003 else
2004 raw_offset = get_const(consts, regs) >> 32;
2005 // The high 4 bits are flags, while the rest is the
2006 // twos-complement offset in bytes (here we convert to
2007 // clauses).
2008 int32_t branch_offset = ((int32_t) raw_offset << 4) >> 8;
2009
2010 // If high4 is the high 4 bits of the last 64-bit constant,
2011 // this is calculated as (high4 + 4) & 0xf, or 0 if the branch
2012 // offset itself is the last constant. Not sure if this is
2013 // actually used, or just garbage in unused bits, but in any
2014 // case, we can just ignore it here since it's redundant. Note
2015 // that if there is any padding, this will be 4 since the
2016 // padding counts as the last constant.
2017 unsigned flags = raw_offset >> 28;
2018 (void) flags;
2019
2020 // Note: the offset is in bytes, relative to the beginning of the
2021 // current clause, so a zero offset would be a loop back to the
2022 // same clause (annoyingly different from Midgard).
2023 printf("clause_%d", offset + branch_offset);
2024 } else {
2025 dump_src(offsetSrc, regs, consts, false);
2026 }
2027 }
2028 }
2029 if (info.has_data_reg) {
2030 printf(", R%d", data_reg);
2031 }
2032 printf("\n");
2033 }
2034
2035 void dump_instr(const struct bifrost_alu_inst *instr, struct bifrost_regs next_regs, uint64_t *consts,
2036 unsigned data_reg, unsigned offset, bool verbose)
2037 {
2038 struct bifrost_regs regs;
2039 memcpy((char *) &regs, (char *) &instr->reg_bits, sizeof(regs));
2040
2041 if (verbose) {
2042 printf("# regs: %016" PRIx64 "\n", instr->reg_bits);
2043 dump_regs(regs);
2044 }
2045 dump_fma(instr->fma_bits, regs, next_regs, consts, verbose);
2046 dump_add(instr->add_bits, regs, next_regs, consts, data_reg, offset, verbose);
2047 }
2048
2049 bool dump_clause(uint32_t *words, unsigned *size, unsigned offset, bool verbose)
2050 {
2051 // State for a decoded clause
2052 struct bifrost_alu_inst instrs[8] = {};
2053 uint64_t consts[6] = {};
2054 unsigned num_instrs = 0;
2055 unsigned num_consts = 0;
2056 uint64_t header_bits = 0;
2057 bool stopbit = false;
2058
2059 unsigned i;
2060 for (i = 0; ; i++, words += 4) {
2061 if (verbose) {
2062 printf("# ");
2063 for (int j = 0; j < 4; j++)
2064 printf("%08x ", words[3 - j]); // low bit on the right
2065 printf("\n");
2066 }
2067 unsigned tag = bits(words[0], 0, 8);
2068
2069 // speculatively decode some things that are common between many formats, so we can share some code
2070 struct bifrost_alu_inst main_instr = {};
2071 // 20 bits
2072 main_instr.add_bits = bits(words[2], 2, 32 - 13);
2073 // 23 bits
2074 main_instr.fma_bits = bits(words[1], 11, 32) | bits(words[2], 0, 2) << (32 - 11);
2075 // 35 bits
2076 main_instr.reg_bits = ((uint64_t) bits(words[1], 0, 11)) << 24 | (uint64_t) bits(words[0], 8, 32);
2077
2078 uint64_t const0 = bits(words[0], 8, 32) << 4 | (uint64_t) words[1] << 28 | bits(words[2], 0, 4) << 60;
2079 uint64_t const1 = bits(words[2], 4, 32) << 4 | (uint64_t) words[3] << 32;
2080
2081 bool stop = tag & 0x40;
2082
2083 if (verbose) {
2084 printf("# tag: 0x%02x\n", tag);
2085 }
2086 if (tag & 0x80) {
2087 unsigned idx = stop ? 5 : 2;
2088 main_instr.add_bits |= ((tag >> 3) & 0x7) << 17;
2089 instrs[idx + 1] = main_instr;
2090 instrs[idx].add_bits = bits(words[3], 0, 17) | ((tag & 0x7) << 17);
2091 instrs[idx].fma_bits |= bits(words[2], 19, 32) << 10;
2092 consts[0] = bits(words[3], 17, 32) << 4;
2093 } else {
2094 bool done = false;
2095 switch ((tag >> 3) & 0x7) {
2096 case 0x0:
2097 switch (tag & 0x7) {
2098 case 0x3:
2099 main_instr.add_bits |= bits(words[3], 29, 32) << 17;
2100 instrs[1] = main_instr;
2101 num_instrs = 2;
2102 done = stop;
2103 break;
2104 case 0x4:
2105 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2106 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
2107 consts[0] = const0;
2108 num_instrs = 3;
2109 num_consts = 1;
2110 done = stop;
2111 break;
2112 case 0x1:
2113 case 0x5:
2114 instrs[2].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2115 instrs[2].fma_bits |= bits(words[2], 19, 32) << 10;
2116 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
2117 instrs[3] = main_instr;
2118 if ((tag & 0x7) == 0x5) {
2119 num_instrs = 4;
2120 done = stop;
2121 }
2122 break;
2123 case 0x6:
2124 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2125 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
2126 consts[0] = const0;
2127 num_instrs = 6;
2128 num_consts = 1;
2129 done = stop;
2130 break;
2131 case 0x7:
2132 instrs[5].add_bits = bits(words[3], 0, 17) | bits(words[3], 29, 32) << 17;
2133 instrs[5].fma_bits |= bits(words[2], 19, 32) << 10;
2134 main_instr.add_bits |= bits(words[3], 26, 29) << 17;
2135 instrs[6] = main_instr;
2136 num_instrs = 7;
2137 done = stop;
2138 break;
2139 default:
2140 printf("unknown tag bits 0x%02x\n", tag);
2141 }
2142 break;
2143 case 0x2:
2144 case 0x3: {
2145 unsigned idx = ((tag >> 3) & 0x7) == 2 ? 4 : 7;
2146 main_instr.add_bits |= (tag & 0x7) << 17;
2147 instrs[idx] = main_instr;
2148 consts[0] |= (bits(words[2], 19, 32) | ((uint64_t) words[3] << 13)) << 19;
2149 num_consts = 1;
2150 num_instrs = idx + 1;
2151 done = stop;
2152 break;
2153 }
2154 case 0x4: {
2155 unsigned idx = stop ? 4 : 1;
2156 main_instr.add_bits |= (tag & 0x7) << 17;
2157 instrs[idx] = main_instr;
2158 instrs[idx + 1].fma_bits |= bits(words[3], 22, 32);
2159 instrs[idx + 1].reg_bits = bits(words[2], 19, 32) | (bits(words[3], 0, 22) << (32 - 19));
2160 break;
2161 }
2162 case 0x1:
2163 // only constants can come after this
2164 num_instrs = 1;
2165 done = stop;
2166 case 0x5:
2167 header_bits = bits(words[2], 19, 32) | ((uint64_t) words[3] << (32 - 19));
2168 main_instr.add_bits |= (tag & 0x7) << 17;
2169 instrs[0] = main_instr;
2170 break;
2171 case 0x6:
2172 case 0x7: {
2173 unsigned pos = tag & 0xf;
2174 // note that `pos' encodes both the total number of
2175 // instructions and the position in the constant stream,
2176 // presumably because decoded constants and instructions
2177 // share a buffer in the decoder, but we only care about
2178 // the position in the constant stream; the total number of
2179 // instructions is redundant.
2180 unsigned const_idx = 7;
2181 switch (pos) {
2182 case 0:
2183 case 1:
2184 case 2:
2185 case 6:
2186 const_idx = 0;
2187 break;
2188 case 3:
2189 case 4:
2190 case 7:
2191 case 9:
2192 const_idx = 1;
2193 break;
2194 case 5:
2195 case 0xa:
2196 const_idx = 2;
2197 break;
2198 case 8:
2199 case 0xb:
2200 case 0xc:
2201 const_idx = 3;
2202 break;
2203 case 0xd:
2204 const_idx = 4;
2205 break;
2206 default:
2207 printf("# unknown pos 0x%x\n", pos);
2208 }
2209 if (num_consts < const_idx + 2)
2210 num_consts = const_idx + 2;
2211 consts[const_idx] = const0;
2212 consts[const_idx + 1] = const1;
2213 done = stop;
2214 break;
2215 }
2216 default:
2217 break;
2218 }
2219
2220 if (done)
2221 break;
2222 }
2223 }
2224
2225 *size = i + 1;
2226
2227 if (verbose) {
2228 printf("# header: %012" PRIx64 "\n", header_bits);
2229 }
2230
2231 struct bifrost_header header;
2232 memcpy((char *) &header, (char *) &header_bits, sizeof(struct bifrost_header));
2233 dump_header(header, verbose);
2234 if (!header.no_end_of_shader)
2235 stopbit = true;
2236
2237 printf("{\n");
2238 for (i = 0; i < num_instrs; i++) {
2239 struct bifrost_regs next_regs;
2240 if (i + 1 == num_instrs) {
2241 memcpy((char *) &next_regs, (char *) &instrs[0].reg_bits,
2242 sizeof(next_regs));
2243 } else {
2244 memcpy((char *) &next_regs, (char *) &instrs[i + 1].reg_bits,
2245 sizeof(next_regs));
2246 }
2247
2248 dump_instr(&instrs[i], next_regs, consts, header.datareg, offset, verbose);
2249 }
2250 printf("}\n");
2251
2252 if (verbose) {
2253 for (unsigned i = 0; i < num_consts; i++) {
2254 printf("# const%d: %08" PRIx64 "\n", 2 * i, consts[i] & 0xffffffff);
2255 printf("# const%d: %08" PRIx64 "\n", 2 * i + 1, consts[i] >> 32);
2256 }
2257 }
2258 return stopbit;
2259 }
2260
2261 void disassemble_bifrost(uint8_t *code, size_t size, bool verbose)
2262 {
2263 uint32_t *words = (uint32_t *) code;
2264 uint32_t *words_end = words + (size / 4);
2265 // used for displaying branch targets
2266 unsigned offset = 0;
2267 while (words != words_end) {
2268 // we don't know what the program-end bit is quite yet, so for now just
2269 // assume that an all-0 quadword is padding
2270 uint32_t zero[4] = {};
2271 if (memcmp(words, zero, 4 * sizeof(uint32_t)) == 0)
2272 break;
2273 printf("clause_%d:\n", offset);
2274 unsigned size;
2275 if (dump_clause(words, &size, offset, verbose) == true) {
2276 break;
2277 }
2278 words += size * 4;
2279 offset += size;
2280 }
2281 }
2282