2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
39 typedef uint64_t mali_ptr
;
45 MALI_LINE_STRIP
= 0x4,
48 MALI_TRIANGLE_STRIP
= 0xA,
49 MALI_TRIANGLE_FAN
= 0xC,
52 MALI_QUAD_STRIP
= 0xF,
54 /* All other modes invalid */
57 /* Applies to tiler_gl_enables */
59 #define MALI_OCCLUSION_QUERY (1 << 3)
60 #define MALI_OCCLUSION_PRECISE (1 << 4)
62 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
63 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
64 * disagree about how to do viewport flipping, so the blob actually sets this
65 * for GL_CW but then has a negative viewport stride */
67 #define MALI_FRONT_CCW_TOP (1 << 5)
69 #define MALI_CULL_FACE_FRONT (1 << 6)
70 #define MALI_CULL_FACE_BACK (1 << 7)
72 /* Used in stencil and depth tests */
79 MALI_FUNC_GREATER
= 4,
80 MALI_FUNC_NOTEQUAL
= 5,
85 /* Flags apply to unknown2_3? */
87 #define MALI_HAS_MSAA (1 << 0)
89 /* Execute fragment shader per-sample if set (e.g. to implement gl_SampleID
91 #define MALI_PER_SAMPLE (1 << 2)
92 #define MALI_CAN_DISCARD (1 << 5)
94 /* Applies on SFBD systems, specifying that programmable blending is in use */
95 #define MALI_HAS_BLEND_SHADER (1 << 6)
97 /* func is mali_func */
98 #define MALI_DEPTH_FUNC(func) (func << 8)
99 #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7)
100 #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7)
102 #define MALI_DEPTH_WRITEMASK (1 << 11)
104 #define MALI_DEPTH_CLIP_NEAR (1 << 12)
105 #define MALI_DEPTH_CLIP_FAR (1 << 13)
107 /* Next flags to unknown2_4 */
108 #define MALI_STENCIL_TEST (1 << 0)
110 #define MALI_ALPHA_TO_COVERAGE (1 << 1)
112 #define MALI_NO_DITHER (1 << 9)
113 #define MALI_DEPTH_RANGE_A (1 << 12)
114 #define MALI_DEPTH_RANGE_B (1 << 13)
115 #define MALI_NO_MSAA (1 << 14)
117 /* Stencil test state is all encoded in a single u32, just with a lot of
120 enum mali_stencil_op
{
121 MALI_STENCIL_KEEP
= 0,
122 MALI_STENCIL_REPLACE
= 1,
123 MALI_STENCIL_ZERO
= 2,
124 MALI_STENCIL_INVERT
= 3,
125 MALI_STENCIL_INCR_WRAP
= 4,
126 MALI_STENCIL_DECR_WRAP
= 5,
127 MALI_STENCIL_INCR
= 6,
128 MALI_STENCIL_DECR
= 7
131 struct mali_stencil_test
{
134 enum mali_func func
: 3;
135 enum mali_stencil_op sfail
: 3;
136 enum mali_stencil_op dpfail
: 3;
137 enum mali_stencil_op dppass
: 3;
139 } __attribute__((packed
));
141 #define MALI_MASK_R (1 << 0)
142 #define MALI_MASK_G (1 << 1)
143 #define MALI_MASK_B (1 << 2)
144 #define MALI_MASK_A (1 << 3)
146 enum mali_nondominant_mode
{
147 MALI_BLEND_NON_MIRROR
= 0,
148 MALI_BLEND_NON_ZERO
= 1
151 enum mali_dominant_blend
{
152 MALI_BLEND_DOM_SOURCE
= 0,
153 MALI_BLEND_DOM_DESTINATION
= 1
156 enum mali_dominant_factor
{
157 MALI_DOMINANT_UNK0
= 0,
158 MALI_DOMINANT_ZERO
= 1,
159 MALI_DOMINANT_SRC_COLOR
= 2,
160 MALI_DOMINANT_DST_COLOR
= 3,
161 MALI_DOMINANT_UNK4
= 4,
162 MALI_DOMINANT_SRC_ALPHA
= 5,
163 MALI_DOMINANT_DST_ALPHA
= 6,
164 MALI_DOMINANT_CONSTANT
= 7,
167 enum mali_blend_modifier
{
168 MALI_BLEND_MOD_UNK0
= 0,
169 MALI_BLEND_MOD_NORMAL
= 1,
170 MALI_BLEND_MOD_SOURCE_ONE
= 2,
171 MALI_BLEND_MOD_DEST_ONE
= 3,
174 struct mali_blend_mode
{
175 enum mali_blend_modifier clip_modifier
: 2;
176 unsigned unused_0
: 1;
177 unsigned negate_source
: 1;
179 enum mali_dominant_blend dominant
: 1;
181 enum mali_nondominant_mode nondominant_mode
: 1;
183 unsigned unused_1
: 1;
185 unsigned negate_dest
: 1;
187 enum mali_dominant_factor dominant_factor
: 3;
188 unsigned complement_dominant
: 1;
189 } __attribute__((packed
));
191 struct mali_blend_equation
{
192 /* Of type mali_blend_mode */
193 unsigned rgb_mode
: 12;
194 unsigned alpha_mode
: 12;
198 /* Corresponds to MALI_MASK_* above and glColorMask arguments */
200 unsigned color_mask
: 4;
201 } __attribute__((packed
));
203 /* Used with channel swizzling */
205 MALI_CHANNEL_RED
= 0,
206 MALI_CHANNEL_GREEN
= 1,
207 MALI_CHANNEL_BLUE
= 2,
208 MALI_CHANNEL_ALPHA
= 3,
209 MALI_CHANNEL_ZERO
= 4,
210 MALI_CHANNEL_ONE
= 5,
211 MALI_CHANNEL_RESERVED_0
= 6,
212 MALI_CHANNEL_RESERVED_1
= 7,
215 struct mali_channel_swizzle
{
216 enum mali_channel r
: 3;
217 enum mali_channel g
: 3;
218 enum mali_channel b
: 3;
219 enum mali_channel a
: 3;
220 } __attribute__((packed
));
222 /* Compressed per-pixel formats. Each of these formats expands to one to four
223 * floating-point or integer numbers, as defined by the OpenGL specification.
224 * There are various places in OpenGL where the user can specify a compressed
225 * format in memory, which all use the same 8-bit enum in the various
226 * descriptors, although different hardware units support different formats.
229 /* The top 3 bits specify how the bits of each component are interpreted. */
232 #define MALI_FORMAT_COMPRESSED (0 << 5)
234 /* e.g. R11F_G11F_B10F */
235 #define MALI_FORMAT_SPECIAL (2 << 5)
237 /* signed normalized, e.g. RGBA8_SNORM */
238 #define MALI_FORMAT_SNORM (3 << 5)
241 #define MALI_FORMAT_UINT (4 << 5)
243 /* e.g. RGBA8 and RGBA32F */
244 #define MALI_FORMAT_UNORM (5 << 5)
246 /* e.g. RGBA8I and RGBA16F */
247 #define MALI_FORMAT_SINT (6 << 5)
249 /* These formats seem to largely duplicate the others. They're used at least
250 * for Bifrost framebuffer output.
252 #define MALI_FORMAT_SPECIAL2 (7 << 5)
253 #define MALI_EXTRACT_TYPE(fmt) ((fmt) & 0xe0)
255 /* If the high 3 bits are 3 to 6 these two bits say how many components
258 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
259 #define MALI_EXTRACT_CHANNELS(fmt) ((((fmt) >> 3) & 3) + 1)
261 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
262 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
266 #define MALI_CHANNEL_4 2
268 #define MALI_CHANNEL_8 3
270 #define MALI_CHANNEL_16 4
272 #define MALI_CHANNEL_32 5
274 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
275 * MALI_FORMAT_UNORM, it means a 32-bit float.
277 #define MALI_CHANNEL_FLOAT 7
278 #define MALI_EXTRACT_BITS(fmt) (fmt & 0x7)
281 /* Not all formats are in fact available, need to query dynamically to
282 * check. Factory settings for Juno enables only ETC2 and ASTC, no
287 MALI_ETC2_RGB8
= MALI_FORMAT_COMPRESSED
| 0x1,
288 MALI_ETC2_R11_UNORM
= MALI_FORMAT_COMPRESSED
| 0x2,
289 MALI_ETC2_RGBA8
= MALI_FORMAT_COMPRESSED
| 0x3,
290 MALI_ETC2_RG11_UNORM
= MALI_FORMAT_COMPRESSED
| 0x4,
292 MALI_NXR
= MALI_FORMAT_COMPRESSED
| 0x6, /* Nokia eXtended Range */
293 MALI_BC1_UNORM
= MALI_FORMAT_COMPRESSED
| 0x7, /* DXT1 */
294 MALI_BC2_UNORM
= MALI_FORMAT_COMPRESSED
| 0x8, /* DXT3 */
295 MALI_BC3_UNORM
= MALI_FORMAT_COMPRESSED
| 0x9, /* DXT5 */
296 MALI_BC4_UNORM
= MALI_FORMAT_COMPRESSED
| 0xA, /* RGTC1_UNORM */
297 MALI_BC4_SNORM
= MALI_FORMAT_COMPRESSED
| 0xB, /* RGTC1_SNORM */
298 MALI_BC5_UNORM
= MALI_FORMAT_COMPRESSED
| 0xC, /* RGTC2_UNORM */
299 MALI_BC5_SNORM
= MALI_FORMAT_COMPRESSED
| 0xD, /* RGTC2_SNORM */
300 MALI_BC6H_UF16
= MALI_FORMAT_COMPRESSED
| 0xE,
301 MALI_BC6H_SF16
= MALI_FORMAT_COMPRESSED
| 0xF,
302 MALI_BC7_UNORM
= MALI_FORMAT_COMPRESSED
| 0x10,
303 MALI_ETC2_R11_SNORM
= MALI_FORMAT_COMPRESSED
| 0x11, /* EAC_SNORM */
304 MALI_ETC2_RG11_SNORM
= MALI_FORMAT_COMPRESSED
| 0x12, /* EAC_SNORM */
305 MALI_ETC2_RGB8A1
= MALI_FORMAT_COMPRESSED
| 0x13,
306 MALI_ASTC_3D_LDR
= MALI_FORMAT_COMPRESSED
| 0x14,
307 MALI_ASTC_3D_HDR
= MALI_FORMAT_COMPRESSED
| 0x15,
308 MALI_ASTC_2D_LDR
= MALI_FORMAT_COMPRESSED
| 0x16,
309 MALI_ASTC_2D_HDR
= MALI_FORMAT_COMPRESSED
| 0x17,
311 MALI_RGB565
= MALI_FORMAT_SPECIAL
| 0x0,
312 MALI_RGB5_X1_UNORM
= MALI_FORMAT_SPECIAL
| 0x1,
313 MALI_RGB5_A1_UNORM
= MALI_FORMAT_SPECIAL
| 0x2,
314 MALI_RGB10_A2_UNORM
= MALI_FORMAT_SPECIAL
| 0x3,
315 MALI_RGB10_A2_SNORM
= MALI_FORMAT_SPECIAL
| 0x5,
316 MALI_RGB10_A2UI
= MALI_FORMAT_SPECIAL
| 0x7,
317 MALI_RGB10_A2I
= MALI_FORMAT_SPECIAL
| 0x9,
319 MALI_RGB332_UNORM
= MALI_FORMAT_SPECIAL
| 0xb,
320 MALI_RGB233_UNORM
= MALI_FORMAT_SPECIAL
| 0xc,
322 MALI_Z24X8_UNORM
= MALI_FORMAT_SPECIAL
| 0xd,
323 MALI_R32_FIXED
= MALI_FORMAT_SPECIAL
| 0x11,
324 MALI_RG32_FIXED
= MALI_FORMAT_SPECIAL
| 0x12,
325 MALI_RGB32_FIXED
= MALI_FORMAT_SPECIAL
| 0x13,
326 MALI_RGBA32_FIXED
= MALI_FORMAT_SPECIAL
| 0x14,
327 MALI_R11F_G11F_B10F
= MALI_FORMAT_SPECIAL
| 0x19,
328 MALI_R9F_G9F_B9F_E5F
= MALI_FORMAT_SPECIAL
| 0x1b,
329 /* Only used for varyings, to indicate the transformed gl_Position */
330 MALI_VARYING_POS
= MALI_FORMAT_SPECIAL
| 0x1e,
331 /* Only used for varyings, to indicate that the write should be
334 MALI_VARYING_DISCARD
= MALI_FORMAT_SPECIAL
| 0x1f,
336 MALI_R8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
337 MALI_R16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
338 MALI_R32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
339 MALI_RG8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
340 MALI_RG16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
341 MALI_RG32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
342 MALI_RGB8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
343 MALI_RGB16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
344 MALI_RGB32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
345 MALI_RGBA8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
346 MALI_RGBA16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
347 MALI_RGBA32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
349 MALI_R8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
350 MALI_R16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
351 MALI_R32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
352 MALI_RG8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
353 MALI_RG16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
354 MALI_RG32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
355 MALI_RGB8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
356 MALI_RGB16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
357 MALI_RGB32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
358 MALI_RGBA8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
359 MALI_RGBA16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
360 MALI_RGBA32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
362 MALI_R8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
363 MALI_R16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
364 MALI_R32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
365 MALI_R32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
366 MALI_RG8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
367 MALI_RG16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
368 MALI_RG32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
369 MALI_RG32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
370 MALI_RGB8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
371 MALI_RGB16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
372 MALI_RGB32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
373 MALI_RGB32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
374 MALI_RGBA4_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_4
,
375 MALI_RGBA8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
376 MALI_RGBA16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
377 MALI_RGBA32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
378 MALI_RGBA32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
380 MALI_R8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
381 MALI_R16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
382 MALI_R32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
383 MALI_R16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
384 MALI_RG8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
385 MALI_RG16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
386 MALI_RG32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
387 MALI_RG16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
388 MALI_RGB8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
389 MALI_RGB16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
390 MALI_RGB32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
391 MALI_RGB16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
392 MALI_RGBA8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
393 MALI_RGBA16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
394 MALI_RGBA32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
395 MALI_RGBA16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
397 MALI_RGBA4
= MALI_FORMAT_SPECIAL2
| 0x8,
398 MALI_RGBA8_2
= MALI_FORMAT_SPECIAL2
| 0xd,
399 MALI_RGB10_A2_2
= MALI_FORMAT_SPECIAL2
| 0xe,
403 /* Applies to midgard1.flags_lo */
405 /* Should be set when the fragment shader updates the depth value. */
406 #define MALI_WRITES_Z (1 << 4)
408 /* Should the hardware perform early-Z testing? Set if the shader does not use
409 * discard, alpha-to-coverage, shader depth writes, and if the shader has no
410 * side effects (writes to global memory or images) unless early-z testing is
411 * forced in the shader.
414 #define MALI_EARLY_Z (1 << 6)
416 /* Should the hardware calculate derivatives (via helper invocations)? Set in a
417 * fragment shader that uses texturing or derivative functions */
419 #define MALI_HELPER_INVOCATIONS (1 << 7)
421 /* Flags denoting the fragment shader's use of tilebuffer readback. If the
422 * shader might read any part of the tilebuffer, set MALI_READS_TILEBUFFER. If
423 * it might read depth/stencil in particular, also set MALI_READS_ZS */
425 #define MALI_READS_ZS (1 << 8)
427 /* The shader might write to global memory (via OpenCL, SSBOs, or images).
428 * Reading is okay, as are ordinary writes to the tilebuffer/varyings. Setting
429 * incurs a performance penalty. On a fragment shader, this bit implies there
430 * are side effects, hence it interacts with early-z. */
431 #define MALI_WRITES_GLOBAL (1 << 9)
433 #define MALI_READS_TILEBUFFER (1 << 10)
435 /* Applies to midgard1.flags_hi */
437 /* Should be set when the fragment shader updates the stencil value. */
438 #define MALI_WRITES_S (1 << 2)
440 /* Mode to suppress generation of Infinity and NaN values by clamping inf
441 * (-inf) to MAX_FLOAT (-MIN_FLOAT) and flushing NaN to 0.0
443 * Compare suppress_inf/suppress_nan flags on the Bifrost clause header for the
444 * same functionality.
446 * This is not conformant on GLES3 or OpenCL, but is optional on GLES2, where
447 * it works around app bugs (e.g. in glmark2-es2 -bterrain with FP16).
449 #define MALI_SUPPRESS_INF_NAN (1 << 3)
451 /* Flags for bifrost1.unk1 */
453 /* Shader uses less than 32 registers, partitioned as [R0, R15] U [R48, R63],
454 * allowing for full thread count. If clear, the full [R0, R63] register set is
455 * available at half thread count */
456 #define MALI_BIFROST_FULL_THREAD (1 << 9)
458 /* Enable early-z testing (presumably). This flag may not be set if the shader:
462 * - Writes gl_FragDepth
464 * This differs from Midgard which sets the MALI_EARLY_Z flag even with
465 * blending, although I've begun to suspect that flag does not in fact enable
467 #define MALI_BIFROST_EARLY_Z (1 << 15)
469 /* First clause type is ATEST */
470 #define MALI_BIFROST_FIRST_ATEST (1 << 26)
472 /* The raw Midgard blend payload can either be an equation or a shader
473 * address, depending on the context */
475 union midgard_blend
{
479 struct mali_blend_equation equation
;
484 /* We need to load the tilebuffer to blend (i.e. the destination factor is not
487 #define MALI_BLEND_LOAD_TIB (0x1)
489 /* A blend shader is used to blend this render target */
490 #define MALI_BLEND_MRT_SHADER (0x2)
492 /* On MRT Midgard systems (using an MFBD), each render target gets its own
493 * blend descriptor */
495 #define MALI_BLEND_SRGB (0x400)
497 /* Dithering is specified here for MFBD, otherwise NO_DITHER for SFBD */
498 #define MALI_BLEND_NO_DITHER (0x800)
500 struct midgard_blend_rt
{
501 /* Flags base value of 0x200 to enable the render target.
502 * OR with 0x1 for blending (anything other than REPLACE).
503 * OR with 0x2 for programmable blending
504 * OR with MALI_BLEND_SRGB for implicit sRGB
508 union midgard_blend blend
;
509 } __attribute__((packed
));
511 /* On Bifrost systems (all MRT), each render target gets one of these
514 enum bifrost_shader_type
{
515 BIFROST_BLEND_F16
= 0,
516 BIFROST_BLEND_F32
= 1,
517 BIFROST_BLEND_I32
= 2,
518 BIFROST_BLEND_U32
= 3,
519 BIFROST_BLEND_I16
= 4,
520 BIFROST_BLEND_U16
= 5,
523 #define BIFROST_MAX_RENDER_TARGET_COUNT 8
525 struct bifrost_blend_rt
{
526 /* This is likely an analogue of the flags on
527 * midgard_blend_rt */
529 u16 flags
; // = 0x200
531 /* Single-channel blend constants are encoded in a sort of
532 * fixed-point. Basically, the float is mapped to a byte, becoming
533 * a high byte, and then the lower-byte is added for precision.
534 * For the original float f:
536 * f = (constant_hi / 255) + (constant_lo / 65535)
538 * constant_hi = int(f / 255)
539 * constant_lo = 65535*f - (65535/255) * constant_hi
543 struct mali_blend_equation equation
;
547 * - 0x3 when this slot is unused (everything else is 0 except the index)
548 * - 0x11 when this is the fourth slot (and it's used)
549 * - 0 when there is a blend shader
553 /* increments from 0 to 3 */
558 /* So far, I've only seen:
559 * - R001 for 1-component formats
560 * - RG01 for 2-component formats
561 * - RGB1 for 3-component formats
562 * - RGBA for 4-component formats
565 enum mali_format format
: 8;
567 /* Type of the shader output variable. Note, this can
568 * be different from the format.
569 * enum bifrost_shader_type
576 /* Only the low 32 bits of the blend shader are stored, the
577 * high 32 bits are implicitly the same as the original shader.
578 * According to the kernel driver, the program counter for
579 * shaders is actually only 24 bits, so shaders cannot cross
580 * the 2^24-byte boundary, and neither can the blend shader.
581 * The blob handles this by allocating a 2^24 byte pool for
582 * shaders, and making sure that any blend shaders are stored
583 * in the same pool as the original shader. The kernel will
584 * make sure this allocation is aligned to 2^24 bytes.
588 } __attribute__((packed
));
590 /* Descriptor for the shader. Following this is at least one, up to four blend
591 * descriptors for each active render target */
593 struct mali_shader_meta
{
602 u32 uniform_buffer_count
: 4;
603 u32 unk1
: 28; // = 0x800000 for vertex, 0x958020 for tiler
606 unsigned uniform_buffer_count
: 4;
607 unsigned flags_lo
: 12;
610 unsigned work_count
: 5;
611 unsigned uniform_count
: 5;
612 unsigned flags_hi
: 6;
616 /* Same as glPolygoOffset() arguments */
622 /* Generated from SAMPLE_COVERAGE_VALUE and SAMPLE_COVERAGE_INVERT. See
623 * 13.8.3 ("Multisample Fragment Operations") in the OpenGL ES 3.2
624 * specification. Only matters when multisampling is enabled. */
629 u8 stencil_mask_front
;
630 u8 stencil_mask_back
;
633 struct mali_stencil_test stencil_front
;
634 struct mali_stencil_test stencil_back
;
639 /* On Bifrost, some system values are preloaded in
640 * registers R55-R62 by the thread dispatcher prior to
641 * the start of shader execution. This is a bitfield
642 * with one entry for each register saying which
643 * registers need to be preloaded. Right now, the known
647 * - R55 : gl_LocalInvocationID.xy
648 * - R56 : gl_LocalInvocationID.z + unknown in high 16 bits
649 * - R57 : gl_WorkGroupID.x
650 * - R58 : gl_WorkGroupID.y
651 * - R59 : gl_WorkGroupID.z
652 * - R60 : gl_GlobalInvocationID.x
653 * - R61 : gl_GlobalInvocationID.y/gl_VertexID (without base)
654 * - R62 : gl_GlobalInvocationID.z/gl_InstanceID (without base)
657 * - R55 : unknown, never seen (but the bit for this is
659 * - R56 : unknown (bit always unset)
660 * - R57 : gl_PrimitiveID
661 * - R58 : gl_FrontFacing in low bit, potentially other stuff
662 * - R59 : u16 fragment coordinates (used to compute
663 * gl_FragCoord.xy, together with sample positions)
664 * - R60 : gl_SampleMask (used in epilog, so pretty
665 * much always used, but the bit is always 0 -- is
666 * this just always pushed?)
667 * - R61 : gl_SampleMaskIn and gl_SampleID, used by
668 * varying interpolation.
669 * - R62 : unknown (bit always unset).
671 * Later GPUs (starting with Mali-G52?) support
672 * preloading float varyings into r0-r7. This is
673 * indicated by setting 0x40. There is no distinction
674 * here between 1 varying and 2.
676 u32 preload_regs
: 8;
677 /* In units of 8 bytes or 64 bits, since the
678 * uniform/const port loads 64 bits at a time.
680 u32 uniform_count
: 7;
681 u32 unk4
: 10; // = 2
690 /* Blending information for the older non-MRT Midgard HW. Check for
691 * MALI_HAS_BLEND_SHADER to decide how to interpret.
694 union midgard_blend blend
;
695 } __attribute__((packed
));
697 /* This only concerns hardware jobs */
699 /* Possible values for job_descriptor_size */
701 #define MALI_JOB_32 0
702 #define MALI_JOB_64 1
704 struct mali_job_descriptor_header
{
705 u32 exception_status
;
706 u32 first_incomplete_task
;
708 u8 job_descriptor_size
: 1;
709 enum mali_job_type job_type
: 7;
711 u8 unknown_flags
: 7;
713 u16 job_dependency_index_1
;
714 u16 job_dependency_index_2
;
716 } __attribute__((packed
));
718 /* These concern exception_status */
720 /* Access type causing a fault, paralleling AS_FAULTSTATUS_* entries in the
723 enum mali_exception_access
{
724 /* Atomic in the kernel for MMU, but that doesn't make sense for a job
725 * fault so it's just unused */
726 MALI_EXCEPTION_ACCESS_NONE
= 0,
728 MALI_EXCEPTION_ACCESS_EXECUTE
= 1,
729 MALI_EXCEPTION_ACCESS_READ
= 2,
730 MALI_EXCEPTION_ACCESS_WRITE
= 3
733 /* Details about write_value from panfrost igt tests which use it as a generic
734 * dword write primitive */
736 #define MALI_WRITE_VALUE_ZERO 3
738 struct mali_payload_write_value
{
740 u32 value_descriptor
;
743 } __attribute__((packed
));
748 * This structure lets the attribute unit compute the address of an attribute
749 * given the vertex and instance ID. Unfortunately, the way this works is
750 * rather complicated when instancing is enabled.
752 * To explain this, first we need to explain how compute and vertex threads are
753 * dispatched. This is a guess (although a pretty firm guess!) since the
754 * details are mostly hidden from the driver, except for attribute instancing.
755 * When a quad is dispatched, it receives a single, linear index. However, we
756 * need to translate that index into a (vertex id, instance id) pair, or a
757 * (local id x, local id y, local id z) triple for compute shaders (although
758 * vertex shaders and compute shaders are handled almost identically).
759 * Focusing on vertex shaders, one option would be to do:
761 * vertex_id = linear_id % num_vertices
762 * instance_id = linear_id / num_vertices
764 * but this involves a costly division and modulus by an arbitrary number.
765 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
766 * num_instances threads instead of num_vertices * num_instances, which results
767 * in some "extra" threads with vertex_id >= num_vertices, which we have to
768 * discard. The more we pad num_vertices, the more "wasted" threads we
769 * dispatch, but the division is potentially easier.
771 * One straightforward choice is to pad num_vertices to the next power of two,
772 * which means that the division and modulus are just simple bit shifts and
773 * masking. But the actual algorithm is a bit more complicated. The thread
774 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
775 * to dividing by a power of two. This is possibly using the technique
776 * described in patent US20170010862A1. As a result, padded_num_vertices can be
777 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
778 * since we need less padding.
780 * padded_num_vertices is picked by the hardware. The driver just specifies the
781 * actual number of vertices. At least for Mali G71, the first few cases are
784 * num_vertices | padded_num_vertices
791 * Note that padded_num_vertices is a multiple of four (presumably because
792 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
793 * at least one more than num_vertices, which seems like a quirk of the
794 * hardware. For larger num_vertices, the hardware uses the following
795 * algorithm: using the binary representation of num_vertices, we look at the
796 * most significant set bit as well as the following 3 bits. Let n be the
797 * number of bits after those 4 bits. Then we set padded_num_vertices according
798 * to the following table:
800 * high bits | padded_num_vertices
807 * For example, if num_vertices = 70 is passed to glDraw(), its binary
808 * representation is 1000110, so n = 3 and the high bits are 1000, and
809 * therefore padded_num_vertices = 9 * 2^3 = 72.
811 * The attribute unit works in terms of the original linear_id. if
812 * num_instances = 1, then they are the same, and everything is simple.
813 * However, with instancing things get more complicated. There are four
814 * possible modes, two of them we can group together:
816 * 1. Use the linear_id directly. Only used when there is no instancing.
818 * 2. Use the linear_id modulo a constant. This is used for per-vertex
819 * attributes with instancing enabled by making the constant equal
820 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
821 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
822 * The shift field specifies the power of two, while the extra_flags field
823 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
824 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
825 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
826 * shift = 3. Note that we must exactly follow the hardware algorithm used to
827 * get padded_num_vertices in order to correctly implement per-vertex
830 * 3. Divide the linear_id by a constant. In order to correctly implement
831 * instance divisors, we have to divide linear_id by padded_num_vertices times
832 * to user-specified divisor. So first we compute padded_num_vertices, again
833 * following the exact same algorithm that the hardware uses, then multiply it
834 * by the GL-level divisor to get the hardware-level divisor. This case is
835 * further divided into two more cases. If the hardware-level divisor is a
836 * power of two, then we just need to shift. The shift amount is specified by
837 * the shift field, so that the hardware-level divisor is just 2^shift.
839 * If it isn't a power of two, then we have to divide by an arbitrary integer.
840 * For that, we use the well-known technique of multiplying by an approximation
841 * of the inverse. The driver must compute the magic multiplier and shift
842 * amount, and then the hardware does the multiplication and shift. The
843 * hardware and driver also use the "round-down" optimization as described in
844 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
845 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
846 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
847 * presumably this simplifies the hardware multiplier a little. The hardware
848 * first multiplies linear_id by the multiplier and takes the high 32 bits,
849 * then applies the round-down correction if extra_flags = 1, then finally
850 * shifts right by the shift field.
852 * There are some differences between ridiculousfish's algorithm and the Mali
853 * hardware algorithm, which means that the reference code from ridiculousfish
854 * doesn't always produce the right constants. Mali does not use the pre-shift
855 * optimization, since that would make a hardware implementation slower (it
856 * would have to always do the pre-shift, multiply, and post-shift operations).
857 * It also forces the multplier to be at least 2^31, which means that the
858 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
859 * given the divisor d, the algorithm the driver must follow is:
861 * 1. Set shift = floor(log2(d)).
862 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
863 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
864 * magic_divisor = m - 1 and extra_flags = 1.
865 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
867 * Unrelated to instancing/actual attributes, images (the OpenCL kind) are
868 * implemented as special attributes, denoted by MALI_ATTR_IMAGE. For images,
869 * let shift=extra_flags=0. Stride is set to the image format's bytes-per-pixel
870 * (*NOT the row stride*). Size is set to the size of the image itself.
872 * Special internal attribtues and varyings (gl_VertexID, gl_FrontFacing, etc)
873 * use particular fixed addresses with modified structures.
876 enum mali_attr_mode
{
877 MALI_ATTR_UNUSED
= 0,
878 MALI_ATTR_LINEAR
= 1,
879 MALI_ATTR_POT_DIVIDE
= 2,
880 MALI_ATTR_MODULO
= 3,
881 MALI_ATTR_NPOT_DIVIDE
= 4,
885 /* Pseudo-address for gl_VertexID, gl_FragCoord, gl_FrontFacing */
887 #define MALI_ATTR_VERTEXID (0x22)
888 #define MALI_ATTR_INSTANCEID (0x24)
889 #define MALI_VARYING_FRAG_COORD (0x25)
890 #define MALI_VARYING_FRONT_FACING (0x26)
892 /* This magic "pseudo-address" is used as `elements` to implement
893 * gl_PointCoord. When read from a fragment shader, it generates a point
894 * coordinate per the OpenGL ES 2.0 specification. Flipped coordinate spaces
895 * require an affine transformation in the shader. */
897 #define MALI_VARYING_POINT_COORD (0x61)
899 /* Used for comparison to check if an address is special. Mostly a guess, but
900 * it doesn't really matter. */
902 #define MALI_RECORD_SPECIAL (0x100)
905 /* This is used for actual attributes. */
907 /* The bottom 3 bits are the mode */
908 mali_ptr elements
: 64 - 8;
914 /* The entry after an NPOT_DIVIDE entry has this format. It stores
915 * extra information that wouldn't fit in a normal entry.
918 u32 unk
; /* = 0x20 */
921 /* This is the original, GL-level divisor. */
924 } __attribute__((packed
));
926 struct mali_attr_meta
{
927 /* Vertex buffer index */
930 unsigned unknown1
: 2;
931 unsigned swizzle
: 12;
932 enum mali_format format
: 8;
934 /* Always observed to be zero at the moment */
935 unsigned unknown3
: 2;
937 /* When packing multiple attributes in a buffer, offset addresses by
938 * this value. Obscurely, this is signed. */
940 } __attribute__((packed
));
942 #define FBD_MASK (~0x3f)
944 /* MFBD, rather than SFBD */
945 #define MALI_MFBD (0x1)
947 /* ORed into an MFBD address to specify the fbx section is included */
948 #define MALI_MFBD_TAG_EXTRA (0x2)
950 /* Uniform buffer objects are 64-bit fields divided as:
953 * mali_ptr ptr : 64 - 10;
955 * The size is actually the size minus 1 (MALI_POSITIVE), in units of 16 bytes.
956 * This gives a maximum of 2^14 bytes, which just so happens to be the GL
957 * minimum-maximum for GL_MAX_UNIFORM_BLOCK_SIZE.
959 * The pointer is missing the bottom 2 bits and top 8 bits. The top 8 bits
960 * should be 0 for userspace pointers, according to
961 * https://lwn.net/Articles/718895/. By reusing these bits, we can make each
962 * entry in the table only 64 bits.
965 #define MALI_MAKE_UBO(elements, ptr) \
966 (MALI_POSITIVE((elements)) | (((ptr) >> 2) << 10))
968 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
969 * They also seem to be the same between Bifrost and Midgard. They're shared in
973 /* Applies to unknown_draw */
975 #define MALI_DRAW_INDEXED_UINT8 (0x10)
976 #define MALI_DRAW_INDEXED_UINT16 (0x20)
977 #define MALI_DRAW_INDEXED_UINT32 (0x30)
978 #define MALI_DRAW_INDEXED_SIZE (0x30)
979 #define MALI_DRAW_INDEXED_SHIFT (4)
981 #define MALI_DRAW_VARYING_SIZE (0x100)
983 /* Set to use first vertex as the provoking vertex for flatshading. Clear to
984 * use the last vertex. This is the default in DX and VK, but not in GL. */
986 #define MALI_DRAW_FLATSHADE_FIRST (0x800)
988 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
990 struct mali_vertex_tiler_prefix
{
991 /* This is a dynamic bitfield containing the following things in this order:
993 * - gl_WorkGroupSize.x
994 * - gl_WorkGroupSize.y
995 * - gl_WorkGroupSize.z
996 * - gl_NumWorkGroups.x
997 * - gl_NumWorkGroups.y
998 * - gl_NumWorkGroups.z
1000 * The number of bits allocated for each number is based on the *_shift
1001 * fields below. For example, workgroups_y_shift gives the bit that
1002 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
1003 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
1004 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
1005 * value is one more than the stored value, since if any of the values
1006 * are zero, then there would be no invocations (and hence no job). If
1007 * there were 0 bits allocated to a given field, then it must be zero,
1008 * and hence the real value is one.
1010 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
1011 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
1012 * where vertex count is the number of vertices.
1014 u32 invocation_count
;
1016 /* Bitfield for shifts:
1020 * workgroups_x_shift : 6
1021 * workgroups_y_shift : 6
1022 * workgroups_z_shift : 6
1023 * workgroups_x_shift_2 : 4
1025 u32 invocation_shifts
;
1028 u32 unknown_draw
: 22;
1030 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
1031 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
1032 * something to do with how many quads get put in the same execution
1033 * engine, which is a balance (you don't want to starve the engine, but
1034 * you also want to distribute work evenly).
1036 u32 workgroups_x_shift_3
: 6;
1039 /* Negative of min_index. This is used to compute
1040 * the unbiased index in tiler/fragment shader runs.
1042 * The hardware adds offset_bias_correction in each run,
1043 * so that absent an index bias, the first vertex processed is
1044 * genuinely the first vertex (0). But with an index bias,
1045 * the first vertex process is numbered the same as the bias.
1047 * To represent this more conviniently:
1048 * unbiased_index = lower_bound_index +
1050 * offset_bias_correction
1052 * This is done since the hardware doesn't accept a index_bias
1053 * and this allows it to recover the unbiased index.
1055 int32_t offset_bias_correction
;
1058 /* Like many other strictly nonzero quantities, index_count is
1059 * subtracted by one. For an indexed cube, this is equal to 35 = 6
1060 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
1061 * for an indexed draw, index_count is the number of actual vertices
1062 * rendered whereas invocation_count is the number of unique vertices
1063 * rendered (the number of times the vertex shader must be invoked).
1064 * For non-indexed draws, this is just equal to invocation_count. */
1068 /* No hidden structure; literally just a pointer to an array of uint
1069 * indices (width depends on flags). Thanks, guys, for not making my
1070 * life insane for once! NULL for non-indexed draws. */
1073 } __attribute__((packed
));
1075 /* Point size / line width can either be specified as a 32-bit float (for
1076 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
1077 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
1078 * payload, the contents of varying_pointer will be intepreted as an array of
1079 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
1080 * creating a special MALI_R16F varying writing to varying_pointer. */
1082 union midgard_primitive_size
{
1087 struct bifrost_tiler_heap_meta
{
1090 /* note: these are just guesses! */
1091 mali_ptr tiler_heap_start
;
1092 mali_ptr tiler_heap_free
;
1093 mali_ptr tiler_heap_end
;
1095 /* hierarchy weights? but they're still 0 after the job has run... */
1099 } __attribute__((packed
));
1101 struct bifrost_tiler_meta
{
1102 u32 tiler_heap_next_start
; /* To be written by the GPU */
1103 u32 used_hierarchy_mask
; /* To be written by the GPU */
1104 u16 hierarchy_mask
; /* Five values observed: 0xa, 0x14, 0x28, 0x50, 0xa0 */
1109 mali_ptr tiler_heap_meta
;
1110 /* TODO what is this used for? */
1112 } __attribute__((packed
));
1114 struct bifrost_tiler_only
{
1116 union midgard_primitive_size primitive_size
;
1118 mali_ptr tiler_meta
;
1120 u64 zero1
, zero2
, zero3
, zero4
, zero5
, zero6
;
1121 } __attribute__((packed
));
1123 struct mali_vertex_tiler_postfix
{
1124 u16 gl_enables
; // 0x6 on Midgard, 0x2 on Bifrost
1126 /* Both zero for non-instanced draws. For instanced draws, a
1127 * decomposition of padded_num_vertices. See the comments about the
1128 * corresponding fields in mali_attr for context. */
1130 unsigned instance_shift
: 5;
1131 unsigned instance_odd
: 3;
1135 /* Offset for first vertex in buffer */
1140 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
1141 * output from the vertex shader for tiler jobs.
1144 u64 position_varying
;
1146 /* An array of mali_uniform_buffer_meta's. The size is given by the
1149 u64 uniform_buffers
;
1151 /* On Bifrost, this is a pointer to an array of bifrost_texture_descriptor.
1152 * On Midgard, this is a pointer to an array of pointers to the texture
1153 * descriptors, number of pointers bounded by number of textures. The
1154 * indirection is needed to accomodate varying numbers and sizes of
1155 * texture descriptors */
1158 /* For OpenGL, from what I've seen, this is intimately connected to
1159 * texture_meta. cwabbott says this is not the case under Vulkan, hence
1160 * why this field is seperate (Midgard is Vulkan capable). Pointer to
1161 * array of sampler descriptors (which are uniform in size) */
1162 u64 sampler_descriptor
;
1166 u64 attributes
; /* struct attribute_buffer[] */
1167 u64 attribute_meta
; /* attribute_meta[] */
1168 u64 varyings
; /* struct attr */
1169 u64 varying_meta
; /* pointer */
1171 u64 occlusion_counter
; /* A single bit as far as I can tell */
1173 /* On Bifrost, this points directly to a mali_shared_memory structure.
1174 * On Midgard, this points to a framebuffer (either SFBD or MFBD as
1175 * tagged), which embeds a mali_shared_memory structure */
1176 mali_ptr shared_memory
;
1177 } __attribute__((packed
));
1179 struct midgard_payload_vertex_tiler
{
1180 struct mali_vertex_tiler_prefix prefix
;
1181 struct mali_vertex_tiler_postfix postfix
;
1183 union midgard_primitive_size primitive_size
;
1184 } __attribute__((packed
));
1186 struct bifrost_payload_vertex
{
1187 struct mali_vertex_tiler_prefix prefix
;
1188 struct mali_vertex_tiler_postfix postfix
;
1189 } __attribute__((packed
));
1191 struct bifrost_payload_tiler
{
1192 struct mali_vertex_tiler_prefix prefix
;
1193 struct bifrost_tiler_only tiler
;
1194 struct mali_vertex_tiler_postfix postfix
;
1195 } __attribute__((packed
));
1197 struct bifrost_payload_fused
{
1198 struct mali_vertex_tiler_prefix prefix
;
1199 struct bifrost_tiler_only tiler
;
1200 struct mali_vertex_tiler_postfix tiler_postfix
;
1201 u64 padding
; /* zero */
1202 struct mali_vertex_tiler_postfix vertex_postfix
;
1203 } __attribute__((packed
));
1205 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
1206 * texture is stored as (63, 63) in these fields. This adjusts for that.
1207 * There's an identical pattern in the framebuffer descriptor. Even vertex
1208 * count fields work this way, hence the generic name -- integral fields that
1209 * are strictly positive generally need this adjustment. */
1211 #define MALI_POSITIVE(dim) (dim - 1)
1213 /* Used with wrapping. Unclear what top bit conveys */
1215 enum mali_wrap_mode
{
1216 MALI_WRAP_REPEAT
= 0x8 | 0x0,
1217 MALI_WRAP_CLAMP_TO_EDGE
= 0x8 | 0x1,
1218 MALI_WRAP_CLAMP
= 0x8 | 0x2,
1219 MALI_WRAP_CLAMP_TO_BORDER
= 0x8 | 0x3,
1220 MALI_WRAP_MIRRORED_REPEAT
= 0x8 | 0x4 | 0x0,
1221 MALI_WRAP_MIRRORED_CLAMP_TO_EDGE
= 0x8 | 0x4 | 0x1,
1222 MALI_WRAP_MIRRORED_CLAMP
= 0x8 | 0x4 | 0x2,
1223 MALI_WRAP_MIRRORED_CLAMP_TO_BORDER
= 0x8 | 0x4 | 0x3,
1226 /* Shared across both command stream and Midgard, and even with Bifrost */
1228 enum mali_texture_type
{
1229 MALI_TEX_CUBE
= 0x0,
1236 #define MAX_MIP_LEVELS (13)
1238 /* Cubemap bloats everything up */
1239 #define MAX_CUBE_FACES (6)
1241 /* For each pointer, there is an address and optionally also a stride */
1242 #define MAX_ELEMENTS (2)
1244 /* It's not known why there are 4-bits allocated -- this enum is almost
1245 * certainly incomplete */
1247 enum mali_texture_layout
{
1248 /* For a Z/S texture, this is linear */
1249 MALI_TEXTURE_TILED
= 0x1,
1251 /* Z/S textures cannot be tiled */
1252 MALI_TEXTURE_LINEAR
= 0x2,
1255 MALI_TEXTURE_AFBC
= 0xC
1258 /* Corresponds to the type passed to glTexImage2D and so forth */
1260 struct mali_texture_format
{
1261 unsigned swizzle
: 12;
1262 enum mali_format format
: 8;
1265 unsigned unknown1
: 1;
1267 enum mali_texture_type type
: 2;
1268 enum mali_texture_layout layout
: 4;
1271 unsigned unknown2
: 1;
1273 /* Set to allow packing an explicit stride */
1274 unsigned manual_stride
: 1;
1277 } __attribute__((packed
));
1279 struct mali_texture_descriptor
{
1283 uint16_t array_size
;
1285 struct mali_texture_format format
;
1289 /* One for non-mipmapped, zero for mipmapped */
1292 /* Zero for non-mipmapped, (number of levels - 1) for mipmapped */
1295 /* Swizzling is a single 32-bit word, broken up here for convenience.
1296 * Here, swizzling refers to the ES 3.0 texture parameters for channel
1297 * level swizzling, not the internal pixel-level swizzling which is
1298 * below OpenGL's reach */
1300 unsigned swizzle
: 12;
1301 unsigned swizzle_zero
: 20;
1306 } __attribute__((packed
));
1308 /* While Midgard texture descriptors are variable length, Bifrost descriptors
1309 * are fixed like samplers with more pointers to expand if necessary */
1311 struct bifrost_texture_descriptor
{
1312 unsigned format_unk
: 4; /* 2 */
1313 enum mali_texture_type type
: 2;
1315 unsigned format_swizzle
: 12;
1316 enum mali_format format
: 8;
1318 unsigned format_unk3
: 1; /* 0 */
1320 uint16_t width
; /* MALI_POSITIVE */
1321 uint16_t height
; /* MALI_POSITIVE */
1323 /* OpenGL swizzle */
1324 unsigned swizzle
: 12;
1325 enum mali_texture_layout layout
: 4;
1326 uint8_t levels
: 8; /* Number of levels-1 if mipmapped, 0 if not */
1329 unsigned levels_unk
: 24; /* 0 */
1330 unsigned level_2
: 8; /* Number of levels, again? */
1334 uint16_t array_size
;
1339 } __attribute__((packed
));
1343 #define MALI_SAMP_MAG_NEAREST (1 << 0)
1344 #define MALI_SAMP_MIN_NEAREST (1 << 1)
1346 /* TODO: What do these bits mean individually? Only seen set together */
1348 #define MALI_SAMP_MIP_LINEAR_1 (1 << 3)
1349 #define MALI_SAMP_MIP_LINEAR_2 (1 << 4)
1351 /* Flag in filter_mode, corresponding to OpenCL's NORMALIZED_COORDS_TRUE
1352 * sampler_t flag. For typical OpenGL textures, this is always set. */
1354 #define MALI_SAMP_NORM_COORDS (1 << 5)
1356 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
1357 * be cleaned up a lot. */
1359 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
1361 static inline int16_t
1362 FIXED_16(float x
, bool allow_negative
)
1364 /* Clamp inputs, accounting for float error */
1365 float max_lod
= (32.0 - (1.0 / 512.0));
1366 float min_lod
= allow_negative
? -max_lod
: 0.0;
1368 x
= ((x
> max_lod
) ? max_lod
: ((x
< min_lod
) ? min_lod
: x
));
1370 return (int) (x
* 256.0);
1373 struct mali_sampler_descriptor
{
1374 uint16_t filter_mode
;
1376 /* Fixed point, signed.
1377 * Upper 7 bits before the decimal point, although it caps [0-31].
1378 * Lower 8 bits after the decimal point: int(round(x * 256)) */
1384 /* All one word in reality, but packed a bit. Comparisons are flipped
1387 enum mali_wrap_mode wrap_s
: 4;
1388 enum mali_wrap_mode wrap_t
: 4;
1389 enum mali_wrap_mode wrap_r
: 4;
1390 enum mali_func compare_func
: 3;
1392 /* No effect on 2D textures. For cubemaps, set for ES3 and clear for
1393 * ES2, controlling seamless cubemapping */
1394 unsigned seamless_cube_map
: 1;
1399 float border_color
[4];
1400 } __attribute__((packed
));
1402 /* Bifrost sampler descriptors look pretty similar */
1404 #define BIFROST_SAMP_MIN_NEAREST (1)
1405 #define BIFROST_SAMP_MAG_LINEAR (1)
1407 struct bifrost_sampler_descriptor
{
1410 enum mali_wrap_mode wrap_r
: 4;
1411 enum mali_wrap_mode wrap_t
: 4;
1412 enum mali_wrap_mode wrap_s
: 4;
1416 uint8_t norm_coords
: 1;
1418 uint8_t min_filter
: 1;
1420 uint8_t mag_filter
: 1;
1421 uint8_t mip_filter
: 1;
1429 } __attribute__((packed
));
1431 /* viewport0/viewport1 form the arguments to glViewport. viewport1 is
1432 * modified by MALI_POSITIVE; viewport0 is as-is.
1435 struct mali_viewport
{
1436 /* XY clipping planes */
1442 /* Depth clipping planes */
1448 } __attribute__((packed
));
1450 /* From presentations, 16x16 tiles externally. Use shift for fast computation
1451 * of tile numbers. */
1453 #define MALI_TILE_SHIFT 4
1454 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
1456 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
1457 * each component. Notice that this provides a theoretical upper bound of (1 <<
1458 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
1459 * 65536x65536. Multiplying that together, times another four given that Mali
1460 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
1461 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
1462 * alone rendering in real-time to such a buffer.
1466 /* From mali_kbase_10969_workaround.c */
1467 #define MALI_X_COORD_MASK 0x00000FFF
1468 #define MALI_Y_COORD_MASK 0x0FFF0000
1470 /* Extract parts of a tile coordinate */
1472 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
1473 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
1475 /* Helpers to generate tile coordinates based on the boundary coordinates in
1476 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
1477 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
1478 * Intentional "off-by-one"; finding the tile number is a form of fencepost
1481 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
1482 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
1483 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
1484 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
1485 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
1487 struct mali_payload_fragment
{
1490 mali_ptr framebuffer
;
1491 } __attribute__((packed
));
1493 /* Single Framebuffer Descriptor */
1495 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
1496 * configured for 4x. With MSAA_8, it is configured for 8x. */
1498 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
1499 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
1500 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
1501 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
1503 /* Fast/slow based on whether all three buffers are cleared at once */
1505 #define MALI_CLEAR_FAST (1 << 18)
1506 #define MALI_CLEAR_SLOW (1 << 28)
1507 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
1509 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
1510 * within the larget framebuffer descriptor). Analogous to
1511 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
1513 /* See pan_tiler.c for derivation */
1514 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
1516 /* Flag disabling the tiler for clear-only jobs, with
1517 hierarchical tiling */
1518 #define MALI_TILER_DISABLED (1 << 12)
1520 /* Flag selecting userspace-generated polygon list, for clear-only jobs without
1521 * hierarhical tiling. */
1522 #define MALI_TILER_USER 0xFFF
1524 /* Absent any geometry, the minimum size of the polygon list header */
1525 #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
1527 struct midgard_tiler_descriptor
{
1528 /* Size of the entire polygon list; see pan_tiler.c for the
1529 * computation. It's based on hierarchical tiling */
1531 u32 polygon_list_size
;
1533 /* Name known from the replay workaround in the kernel. What exactly is
1534 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
1535 * specifies a mask of hierarchy weights, which explains some of the
1536 * performance mysteries around setting it. We also see the bottom bit
1537 * of tiler_flags set in the kernel, but no comment why.
1539 * hierarchy_mask can have the TILER_DISABLED flag */
1544 /* See mali_tiler.c for an explanation */
1545 mali_ptr polygon_list
;
1546 mali_ptr polygon_list_body
;
1548 /* Names based on we see symmetry with replay jobs which name these
1551 mali_ptr heap_start
; /* tiler heap_free_address */
1554 /* Hierarchy weights. We know these are weights based on the kernel,
1555 * but I've never seen them be anything other than zero */
1559 enum mali_block_format
{
1560 MALI_BLOCK_TILED
= 0x0,
1561 MALI_BLOCK_UNKNOWN
= 0x1,
1562 MALI_BLOCK_LINEAR
= 0x2,
1563 MALI_BLOCK_AFBC
= 0x3,
1566 struct mali_sfbd_format
{
1570 /* mali_channel_swizzle */
1571 unsigned swizzle
: 12;
1574 unsigned nr_channels
: 2;
1579 enum mali_block_format block
: 2;
1585 /* Shared structure at the start of framebuffer descriptors, or used bare for
1586 * compute jobs, configuring stack and shared memory */
1588 struct mali_shared_memory
{
1589 u32 stack_shift
: 4;
1592 /* Configuration for shared memory for compute shaders.
1593 * shared_workgroup_count is logarithmic and may be computed for a
1594 * compute shader using shared memory as:
1596 * shared_workgroup_count = MAX2(ceil(log2(count_x)) + ... + ceil(log2(count_z), 10)
1598 * For compute shaders that don't use shared memory, or non-compute
1599 * shaders, this is set to ~0
1602 u32 shared_workgroup_count
: 5;
1603 u32 shared_unk1
: 3;
1604 u32 shared_shift
: 4;
1605 u32 shared_zero
: 20;
1607 mali_ptr scratchpad
;
1609 /* For compute shaders, the RAM backing of workgroup-shared memory. For
1610 * fragment shaders on Bifrost, apparently multisampling locations */
1612 mali_ptr shared_memory
;
1614 } __attribute__((packed
));
1616 /* Configures multisampling on Bifrost fragment jobs */
1618 struct bifrost_multisampling
{
1621 mali_ptr sample_locations
;
1623 } __attribute__((packed
));
1625 struct mali_single_framebuffer
{
1626 struct mali_shared_memory shared_memory
;
1627 struct mali_sfbd_format format
;
1632 /* Purposeful off-by-one in these fields should be accounted for by the
1633 * MALI_DIMENSION macro */
1640 u32 checksum_stride
;
1643 /* By default, the framebuffer is upside down from OpenGL's
1644 * perspective. Set framebuffer to the end and negate the stride to
1645 * flip in the Y direction */
1647 mali_ptr framebuffer
;
1652 /* Depth and stencil buffers are interleaved, it appears, as they are
1653 * set to the same address in captures. Both fields set to zero if the
1654 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
1655 * get a zero enable despite the buffer being present; that still is
1658 mali_ptr depth_buffer
; // not SAME_VA
1659 u32 depth_stride_zero
: 4;
1660 u32 depth_stride
: 28;
1663 mali_ptr stencil_buffer
; // not SAME_VA
1664 u32 stencil_stride_zero
: 4;
1665 u32 stencil_stride
: 28;
1668 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1669 u32 clear_color_2
; // always equal, but unclear function?
1670 u32 clear_color_3
; // always equal, but unclear function?
1671 u32 clear_color_4
; // always equal, but unclear function?
1673 /* Set to zero if not cleared */
1675 float clear_depth_1
; // float32, ditto
1676 float clear_depth_2
; // float32, ditto
1677 float clear_depth_3
; // float32, ditto
1678 float clear_depth_4
; // float32, ditto
1680 u32 clear_stencil
; // Exactly as it appears in OpenGL
1684 struct midgard_tiler_descriptor tiler
;
1686 /* More below this, maybe */
1687 } __attribute__((packed
));
1690 /* SINGLE to disable multisampling, AVERAGE for
1691 * EXT_multisampled_render_to_texture operation where multiple tilebuffer
1692 * samples are implicitly resolved before writeout, MULTIPLE to write multiple
1693 * samples inline, and LAYERED for ES3-style multisampling with each sample in
1694 * a different buffer.
1697 enum mali_msaa_mode
{
1698 MALI_MSAA_SINGLE
= 0,
1699 MALI_MSAA_AVERAGE
= 1,
1700 MALI_MSAA_MULTIPLE
= 2,
1701 MALI_MSAA_LAYERED
= 3,
1704 #define MALI_MFBD_FORMAT_SRGB (1 << 0)
1706 struct mali_rt_format
{
1710 unsigned nr_channels
: 2; /* MALI_POSITIVE */
1714 enum mali_block_format block
: 2;
1715 enum mali_msaa_mode msaa
: 2;
1718 unsigned swizzle
: 12;
1722 /* Disables MFBD preload. When this bit is set, the render target will
1723 * be cleared every frame. When this bit is clear, the hardware will
1724 * automatically wallpaper the render target back from main memory.
1725 * Unfortunately, MFBD preload is very broken on Midgard, so in
1726 * practice, this is a chicken bit that should always be set.
1727 * Discovered by accident, as all good chicken bits are. */
1729 unsigned no_preload
: 1;
1730 } __attribute__((packed
));
1732 /* Flags for afbc.flags and ds_afbc.flags */
1734 #define MALI_AFBC_FLAGS 0x10009
1736 /* Lossless RGB and RGBA colorspace transform */
1737 #define MALI_AFBC_YTR (1 << 17)
1739 struct mali_render_target
{
1740 struct mali_rt_format format
;
1745 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
1746 * there is an extra metadata buffer that contains 16 bytes per tile.
1747 * The framebuffer needs to be the same size as before, since we don't
1748 * know ahead of time how much space it will take up. The
1749 * framebuffer_stride is set to 0, since the data isn't stored linearly
1752 * When AFBC is disabled, these fields are zero.
1756 u32 stride
; // stride in units of tiles
1757 u32 flags
; // = 0x20000
1760 mali_ptr framebuffer
;
1763 u32 framebuffer_stride
: 28; // in units of bytes, row to next
1764 u32 layer_stride
; /* For multisample rendering */
1766 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1767 u32 clear_color_2
; // always equal, but unclear function?
1768 u32 clear_color_3
; // always equal, but unclear function?
1769 u32 clear_color_4
; // always equal, but unclear function?
1770 } __attribute__((packed
));
1772 /* An optional part of mali_framebuffer. It comes between the main structure
1773 * and the array of render targets. It must be included if any of these are
1776 * - Transaction Elimination
1778 * - TODO: Anything else?
1782 #define MALI_EXTRA_PRESENT (0x1)
1785 #define MALI_EXTRA_ZS (0x4)
1787 struct mali_framebuffer_extra
{
1789 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1790 u32 checksum_stride
;
1792 unsigned flags_lo
: 4;
1793 enum mali_block_format zs_block
: 2;
1795 /* Number of samples in Z/S attachment, MALI_POSITIVE. So zero for
1796 * 1-sample (non-MSAA), 0x3 for MSAA 4x, etc */
1797 unsigned zs_samples
: 4;
1798 unsigned flags_hi
: 22;
1801 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1803 mali_ptr depth_stencil_afbc_metadata
;
1804 u32 depth_stencil_afbc_stride
; // in units of tiles
1807 mali_ptr depth_stencil
;
1813 /* Depth becomes depth/stencil in case of combined D/S */
1815 u32 depth_stride_zero
: 4;
1816 u32 depth_stride
: 28;
1817 u32 depth_layer_stride
;
1820 u32 stencil_stride_zero
: 4;
1821 u32 stencil_stride
: 28;
1822 u32 stencil_layer_stride
;
1830 } __attribute__((packed
));
1832 /* Flags for mfbd_flags */
1834 /* Enables writing depth results back to main memory (rather than keeping them
1835 * on-chip in the tile buffer and then discarding) */
1837 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1839 /* The MFBD contains the extra mali_framebuffer_extra section */
1841 #define MALI_MFBD_EXTRA (1 << 13)
1843 struct mali_framebuffer
{
1845 struct mali_shared_memory shared_memory
;
1846 struct bifrost_multisampling msaa
;
1850 u16 width1
, height1
;
1852 u16 width2
, height2
;
1853 u32 unk1
: 19; // = 0x01000
1854 u32 rt_count_1
: 3; // off-by-one (use MALI_POSITIVE)
1855 u32 unk2
: 2; // = 0
1856 u32 rt_count_2
: 3; // no off-by-one
1859 u32 clear_stencil
: 8;
1860 u32 mfbd_flags
: 24; // = 0x100
1864 struct midgard_tiler_descriptor tiler
;
1866 mali_ptr tiler_meta
;
1871 /* optional: struct mali_framebuffer_extra extra */
1872 /* struct mali_render_target rts[] */
1873 } __attribute__((packed
));
1875 #endif /* __PANFROST_JOB_H__ */