2 * © Copyright 2017-2018 Alyssa Rosenzweig
3 * © Copyright 2017-2018 Connor Abbott
4 * © Copyright 2017-2018 Lyude Paul
5 * © Copyright2019 Collabora, Ltd.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
28 #ifndef __PANFROST_JOB_H__
29 #define __PANFROST_JOB_H__
39 typedef uint64_t mali_ptr
;
41 /* Applies to tiler_gl_enables */
43 #define MALI_OCCLUSION_QUERY (1 << 3)
44 #define MALI_OCCLUSION_PRECISE (1 << 4)
46 /* Set for a glFrontFace(GL_CCW) in a Y=0=TOP coordinate system (like Gallium).
47 * In OpenGL, this would corresponds to glFrontFace(GL_CW). Mesa and the blob
48 * disagree about how to do viewport flipping, so the blob actually sets this
49 * for GL_CW but then has a negative viewport stride */
51 #define MALI_FRONT_CCW_TOP (1 << 5)
53 #define MALI_CULL_FACE_FRONT (1 << 6)
54 #define MALI_CULL_FACE_BACK (1 << 7)
56 /* Flags apply to unknown2_3? */
58 #define MALI_HAS_MSAA (1 << 0)
60 /* Execute fragment shader per-sample if set (e.g. to implement gl_SampleID
62 #define MALI_PER_SAMPLE (1 << 2)
63 #define MALI_CAN_DISCARD (1 << 5)
65 /* Applies on SFBD systems, specifying that programmable blending is in use */
66 #define MALI_HAS_BLEND_SHADER (1 << 6)
68 /* func is mali_func */
69 #define MALI_DEPTH_FUNC(func) (func << 8)
70 #define MALI_GET_DEPTH_FUNC(flags) ((flags >> 8) & 0x7)
71 #define MALI_DEPTH_FUNC_MASK MALI_DEPTH_FUNC(0x7)
73 #define MALI_DEPTH_WRITEMASK (1 << 11)
75 #define MALI_DEPTH_CLIP_NEAR (1 << 12)
76 #define MALI_DEPTH_CLIP_FAR (1 << 13)
78 /* Next flags to unknown2_4 */
79 #define MALI_STENCIL_TEST (1 << 0)
81 #define MALI_ALPHA_TO_COVERAGE (1 << 1)
83 #define MALI_NO_DITHER (1 << 9)
84 #define MALI_DEPTH_RANGE_A (1 << 12)
85 #define MALI_DEPTH_RANGE_B (1 << 13)
86 #define MALI_NO_MSAA (1 << 14)
88 /* Stencil test state is all encoded in a single u32, just with a lot of
91 struct mali_stencil_test
{
94 enum mali_func func
: 3;
95 enum mali_stencil_op sfail
: 3;
96 enum mali_stencil_op dpfail
: 3;
97 enum mali_stencil_op dppass
: 3;
99 } __attribute__((packed
));
101 #define MALI_MASK_R (1 << 0)
102 #define MALI_MASK_G (1 << 1)
103 #define MALI_MASK_B (1 << 2)
104 #define MALI_MASK_A (1 << 3)
106 enum mali_nondominant_mode
{
107 MALI_BLEND_NON_MIRROR
= 0,
108 MALI_BLEND_NON_ZERO
= 1
111 enum mali_dominant_blend
{
112 MALI_BLEND_DOM_SOURCE
= 0,
113 MALI_BLEND_DOM_DESTINATION
= 1
116 enum mali_dominant_factor
{
117 MALI_DOMINANT_UNK0
= 0,
118 MALI_DOMINANT_ZERO
= 1,
119 MALI_DOMINANT_SRC_COLOR
= 2,
120 MALI_DOMINANT_DST_COLOR
= 3,
121 MALI_DOMINANT_UNK4
= 4,
122 MALI_DOMINANT_SRC_ALPHA
= 5,
123 MALI_DOMINANT_DST_ALPHA
= 6,
124 MALI_DOMINANT_CONSTANT
= 7,
127 enum mali_blend_modifier
{
128 MALI_BLEND_MOD_UNK0
= 0,
129 MALI_BLEND_MOD_NORMAL
= 1,
130 MALI_BLEND_MOD_SOURCE_ONE
= 2,
131 MALI_BLEND_MOD_DEST_ONE
= 3,
134 struct mali_blend_mode
{
135 enum mali_blend_modifier clip_modifier
: 2;
136 unsigned unused_0
: 1;
137 unsigned negate_source
: 1;
139 enum mali_dominant_blend dominant
: 1;
141 enum mali_nondominant_mode nondominant_mode
: 1;
143 unsigned unused_1
: 1;
145 unsigned negate_dest
: 1;
147 enum mali_dominant_factor dominant_factor
: 3;
148 unsigned complement_dominant
: 1;
149 } __attribute__((packed
));
151 struct mali_blend_equation
{
152 /* Of type mali_blend_mode */
153 unsigned rgb_mode
: 12;
154 unsigned alpha_mode
: 12;
158 /* Corresponds to MALI_MASK_* above and glColorMask arguments */
160 unsigned color_mask
: 4;
161 } __attribute__((packed
));
163 /* Used with channel swizzling */
165 MALI_CHANNEL_RED
= 0,
166 MALI_CHANNEL_GREEN
= 1,
167 MALI_CHANNEL_BLUE
= 2,
168 MALI_CHANNEL_ALPHA
= 3,
169 MALI_CHANNEL_ZERO
= 4,
170 MALI_CHANNEL_ONE
= 5,
171 MALI_CHANNEL_RESERVED_0
= 6,
172 MALI_CHANNEL_RESERVED_1
= 7,
175 struct mali_channel_swizzle
{
176 enum mali_channel r
: 3;
177 enum mali_channel g
: 3;
178 enum mali_channel b
: 3;
179 enum mali_channel a
: 3;
180 } __attribute__((packed
));
182 /* Compressed per-pixel formats. Each of these formats expands to one to four
183 * floating-point or integer numbers, as defined by the OpenGL specification.
184 * There are various places in OpenGL where the user can specify a compressed
185 * format in memory, which all use the same 8-bit enum in the various
186 * descriptors, although different hardware units support different formats.
189 /* The top 3 bits specify how the bits of each component are interpreted. */
192 #define MALI_FORMAT_COMPRESSED (0 << 5)
194 /* e.g. R11F_G11F_B10F */
195 #define MALI_FORMAT_SPECIAL (2 << 5)
197 /* signed normalized, e.g. RGBA8_SNORM */
198 #define MALI_FORMAT_SNORM (3 << 5)
201 #define MALI_FORMAT_UINT (4 << 5)
203 /* e.g. RGBA8 and RGBA32F */
204 #define MALI_FORMAT_UNORM (5 << 5)
206 /* e.g. RGBA8I and RGBA16F */
207 #define MALI_FORMAT_SINT (6 << 5)
209 /* These formats seem to largely duplicate the others. They're used at least
210 * for Bifrost framebuffer output.
212 #define MALI_FORMAT_SPECIAL2 (7 << 5)
213 #define MALI_EXTRACT_TYPE(fmt) ((fmt) & 0xe0)
215 /* If the high 3 bits are 3 to 6 these two bits say how many components
218 #define MALI_NR_CHANNELS(n) ((n - 1) << 3)
219 #define MALI_EXTRACT_CHANNELS(fmt) ((((fmt) >> 3) & 3) + 1)
221 /* If the high 3 bits are 3 to 6, then the low 3 bits say how big each
222 * component is, except the special MALI_CHANNEL_FLOAT which overrides what the
226 #define MALI_CHANNEL_4 2
228 #define MALI_CHANNEL_8 3
230 #define MALI_CHANNEL_16 4
232 #define MALI_CHANNEL_32 5
234 /* For MALI_FORMAT_SINT it means a half-float (e.g. RG16F). For
235 * MALI_FORMAT_UNORM, it means a 32-bit float.
237 #define MALI_CHANNEL_FLOAT 7
238 #define MALI_EXTRACT_BITS(fmt) (fmt & 0x7)
241 /* Not all formats are in fact available, need to query dynamically to
242 * check. Factory settings for Juno enables only ETC2 and ASTC, no
247 MALI_ETC2_RGB8
= MALI_FORMAT_COMPRESSED
| 0x1,
248 MALI_ETC2_R11_UNORM
= MALI_FORMAT_COMPRESSED
| 0x2,
249 MALI_ETC2_RGBA8
= MALI_FORMAT_COMPRESSED
| 0x3,
250 MALI_ETC2_RG11_UNORM
= MALI_FORMAT_COMPRESSED
| 0x4,
252 MALI_NXR
= MALI_FORMAT_COMPRESSED
| 0x6, /* Nokia eXtended Range */
253 MALI_BC1_UNORM
= MALI_FORMAT_COMPRESSED
| 0x7, /* DXT1 */
254 MALI_BC2_UNORM
= MALI_FORMAT_COMPRESSED
| 0x8, /* DXT3 */
255 MALI_BC3_UNORM
= MALI_FORMAT_COMPRESSED
| 0x9, /* DXT5 */
256 MALI_BC4_UNORM
= MALI_FORMAT_COMPRESSED
| 0xA, /* RGTC1_UNORM */
257 MALI_BC4_SNORM
= MALI_FORMAT_COMPRESSED
| 0xB, /* RGTC1_SNORM */
258 MALI_BC5_UNORM
= MALI_FORMAT_COMPRESSED
| 0xC, /* RGTC2_UNORM */
259 MALI_BC5_SNORM
= MALI_FORMAT_COMPRESSED
| 0xD, /* RGTC2_SNORM */
260 MALI_BC6H_UF16
= MALI_FORMAT_COMPRESSED
| 0xE,
261 MALI_BC6H_SF16
= MALI_FORMAT_COMPRESSED
| 0xF,
262 MALI_BC7_UNORM
= MALI_FORMAT_COMPRESSED
| 0x10,
263 MALI_ETC2_R11_SNORM
= MALI_FORMAT_COMPRESSED
| 0x11, /* EAC_SNORM */
264 MALI_ETC2_RG11_SNORM
= MALI_FORMAT_COMPRESSED
| 0x12, /* EAC_SNORM */
265 MALI_ETC2_RGB8A1
= MALI_FORMAT_COMPRESSED
| 0x13,
266 MALI_ASTC_3D_LDR
= MALI_FORMAT_COMPRESSED
| 0x14,
267 MALI_ASTC_3D_HDR
= MALI_FORMAT_COMPRESSED
| 0x15,
268 MALI_ASTC_2D_LDR
= MALI_FORMAT_COMPRESSED
| 0x16,
269 MALI_ASTC_2D_HDR
= MALI_FORMAT_COMPRESSED
| 0x17,
271 MALI_RGB565
= MALI_FORMAT_SPECIAL
| 0x0,
272 MALI_RGB5_X1_UNORM
= MALI_FORMAT_SPECIAL
| 0x1,
273 MALI_RGB5_A1_UNORM
= MALI_FORMAT_SPECIAL
| 0x2,
274 MALI_RGB10_A2_UNORM
= MALI_FORMAT_SPECIAL
| 0x3,
275 MALI_RGB10_A2_SNORM
= MALI_FORMAT_SPECIAL
| 0x5,
276 MALI_RGB10_A2UI
= MALI_FORMAT_SPECIAL
| 0x7,
277 MALI_RGB10_A2I
= MALI_FORMAT_SPECIAL
| 0x9,
279 MALI_RGB332_UNORM
= MALI_FORMAT_SPECIAL
| 0xb,
280 MALI_RGB233_UNORM
= MALI_FORMAT_SPECIAL
| 0xc,
282 MALI_Z24X8_UNORM
= MALI_FORMAT_SPECIAL
| 0xd,
283 MALI_R32_FIXED
= MALI_FORMAT_SPECIAL
| 0x11,
284 MALI_RG32_FIXED
= MALI_FORMAT_SPECIAL
| 0x12,
285 MALI_RGB32_FIXED
= MALI_FORMAT_SPECIAL
| 0x13,
286 MALI_RGBA32_FIXED
= MALI_FORMAT_SPECIAL
| 0x14,
287 MALI_R11F_G11F_B10F
= MALI_FORMAT_SPECIAL
| 0x19,
288 MALI_R9F_G9F_B9F_E5F
= MALI_FORMAT_SPECIAL
| 0x1b,
289 /* Only used for varyings, to indicate the transformed gl_Position */
290 MALI_VARYING_POS
= MALI_FORMAT_SPECIAL
| 0x1e,
291 /* Only used for varyings, to indicate that the write should be
294 MALI_VARYING_DISCARD
= MALI_FORMAT_SPECIAL
| 0x1f,
296 MALI_R8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
297 MALI_R16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
298 MALI_R32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
299 MALI_RG8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
300 MALI_RG16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
301 MALI_RG32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
302 MALI_RGB8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
303 MALI_RGB16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
304 MALI_RGB32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
305 MALI_RGBA8_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
306 MALI_RGBA16_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
307 MALI_RGBA32_SNORM
= MALI_FORMAT_SNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
309 MALI_R8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
310 MALI_R16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
311 MALI_R32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
312 MALI_RG8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
313 MALI_RG16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
314 MALI_RG32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
315 MALI_RGB8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
316 MALI_RGB16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
317 MALI_RGB32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
318 MALI_RGBA8UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
319 MALI_RGBA16UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
320 MALI_RGBA32UI
= MALI_FORMAT_UINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
322 MALI_R8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
323 MALI_R16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
324 MALI_R32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
325 MALI_R32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
326 MALI_RG8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
327 MALI_RG16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
328 MALI_RG32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
329 MALI_RG32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
330 MALI_RGB8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
331 MALI_RGB16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
332 MALI_RGB32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
333 MALI_RGB32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
334 MALI_RGBA4_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_4
,
335 MALI_RGBA8_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
336 MALI_RGBA16_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
337 MALI_RGBA32_UNORM
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
338 MALI_RGBA32F
= MALI_FORMAT_UNORM
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
340 MALI_R8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_8
,
341 MALI_R16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_16
,
342 MALI_R32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_32
,
343 MALI_R16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(1) | MALI_CHANNEL_FLOAT
,
344 MALI_RG8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_8
,
345 MALI_RG16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_16
,
346 MALI_RG32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_32
,
347 MALI_RG16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(2) | MALI_CHANNEL_FLOAT
,
348 MALI_RGB8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_8
,
349 MALI_RGB16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_16
,
350 MALI_RGB32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_32
,
351 MALI_RGB16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(3) | MALI_CHANNEL_FLOAT
,
352 MALI_RGBA8I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_8
,
353 MALI_RGBA16I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_16
,
354 MALI_RGBA32I
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_32
,
355 MALI_RGBA16F
= MALI_FORMAT_SINT
| MALI_NR_CHANNELS(4) | MALI_CHANNEL_FLOAT
,
357 MALI_RGBA4
= MALI_FORMAT_SPECIAL2
| 0x8,
358 MALI_RGBA8_2
= MALI_FORMAT_SPECIAL2
| 0xd,
359 MALI_RGB10_A2_2
= MALI_FORMAT_SPECIAL2
| 0xe,
363 /* Applies to midgard1.flags_lo */
365 /* Should be set when the fragment shader updates the depth value. */
366 #define MALI_WRITES_Z (1 << 4)
368 /* Should the hardware perform early-Z testing? Set if the shader does not use
369 * discard, alpha-to-coverage, shader depth writes, and if the shader has no
370 * side effects (writes to global memory or images) unless early-z testing is
371 * forced in the shader.
374 #define MALI_EARLY_Z (1 << 6)
376 /* Should the hardware calculate derivatives (via helper invocations)? Set in a
377 * fragment shader that uses texturing or derivative functions */
379 #define MALI_HELPER_INVOCATIONS (1 << 7)
381 /* Flags denoting the fragment shader's use of tilebuffer readback. If the
382 * shader might read any part of the tilebuffer, set MALI_READS_TILEBUFFER. If
383 * it might read depth/stencil in particular, also set MALI_READS_ZS */
385 #define MALI_READS_ZS (1 << 8)
387 /* The shader might write to global memory (via OpenCL, SSBOs, or images).
388 * Reading is okay, as are ordinary writes to the tilebuffer/varyings. Setting
389 * incurs a performance penalty. On a fragment shader, this bit implies there
390 * are side effects, hence it interacts with early-z. */
391 #define MALI_WRITES_GLOBAL (1 << 9)
393 #define MALI_READS_TILEBUFFER (1 << 10)
395 /* Applies to midgard1.flags_hi */
397 /* Should be set when the fragment shader updates the stencil value. */
398 #define MALI_WRITES_S (1 << 2)
400 /* Mode to suppress generation of Infinity and NaN values by clamping inf
401 * (-inf) to MAX_FLOAT (-MIN_FLOAT) and flushing NaN to 0.0
403 * Compare suppress_inf/suppress_nan flags on the Bifrost clause header for the
404 * same functionality.
406 * This is not conformant on GLES3 or OpenCL, but is optional on GLES2, where
407 * it works around app bugs (e.g. in glmark2-es2 -bterrain with FP16).
409 #define MALI_SUPPRESS_INF_NAN (1 << 3)
411 /* Flags for bifrost1.unk1 */
413 /* Shader uses less than 32 registers, partitioned as [R0, R15] U [R48, R63],
414 * allowing for full thread count. If clear, the full [R0, R63] register set is
415 * available at half thread count */
416 #define MALI_BIFROST_FULL_THREAD (1 << 9)
418 /* Enable early-z testing (presumably). This flag may not be set if the shader:
422 * - Writes gl_FragDepth
424 * This differs from Midgard which sets the MALI_EARLY_Z flag even with
425 * blending, although I've begun to suspect that flag does not in fact enable
427 #define MALI_BIFROST_EARLY_Z (1 << 15)
429 /* First clause type is ATEST */
430 #define MALI_BIFROST_FIRST_ATEST (1 << 26)
432 /* The raw Midgard blend payload can either be an equation or a shader
433 * address, depending on the context */
435 union midgard_blend
{
439 struct mali_blend_equation equation
;
444 /* We need to load the tilebuffer to blend (i.e. the destination factor is not
447 #define MALI_BLEND_LOAD_TIB (0x1)
449 /* A blend shader is used to blend this render target */
450 #define MALI_BLEND_MRT_SHADER (0x2)
452 /* On MRT Midgard systems (using an MFBD), each render target gets its own
453 * blend descriptor */
455 #define MALI_BLEND_SRGB (0x400)
457 /* Dithering is specified here for MFBD, otherwise NO_DITHER for SFBD */
458 #define MALI_BLEND_NO_DITHER (0x800)
460 struct midgard_blend_rt
{
461 /* Flags base value of 0x200 to enable the render target.
462 * OR with 0x1 for blending (anything other than REPLACE).
463 * OR with 0x2 for programmable blending
464 * OR with MALI_BLEND_SRGB for implicit sRGB
468 union midgard_blend blend
;
469 } __attribute__((packed
));
471 /* On Bifrost systems (all MRT), each render target gets one of these
474 enum bifrost_shader_type
{
475 BIFROST_BLEND_F16
= 0,
476 BIFROST_BLEND_F32
= 1,
477 BIFROST_BLEND_I32
= 2,
478 BIFROST_BLEND_U32
= 3,
479 BIFROST_BLEND_I16
= 4,
480 BIFROST_BLEND_U16
= 5,
483 #define BIFROST_MAX_RENDER_TARGET_COUNT 8
485 struct bifrost_blend_rt
{
486 /* This is likely an analogue of the flags on
487 * midgard_blend_rt */
489 u16 flags
; // = 0x200
491 /* Single-channel blend constants are encoded in a sort of
492 * fixed-point. Basically, the float is mapped to a byte, becoming
493 * a high byte, and then the lower-byte is added for precision.
494 * For the original float f:
496 * f = (constant_hi / 255) + (constant_lo / 65535)
498 * constant_hi = int(f / 255)
499 * constant_lo = 65535*f - (65535/255) * constant_hi
503 struct mali_blend_equation equation
;
507 * - 0x3 when this slot is unused (everything else is 0 except the index)
508 * - 0x11 when this is the fourth slot (and it's used)
509 * - 0 when there is a blend shader
513 /* increments from 0 to 3 */
518 /* So far, I've only seen:
519 * - R001 for 1-component formats
520 * - RG01 for 2-component formats
521 * - RGB1 for 3-component formats
522 * - RGBA for 4-component formats
525 enum mali_format format
: 8;
527 /* Type of the shader output variable. Note, this can
528 * be different from the format.
529 * enum bifrost_shader_type
536 /* Only the low 32 bits of the blend shader are stored, the
537 * high 32 bits are implicitly the same as the original shader.
538 * According to the kernel driver, the program counter for
539 * shaders is actually only 24 bits, so shaders cannot cross
540 * the 2^24-byte boundary, and neither can the blend shader.
541 * The blob handles this by allocating a 2^24 byte pool for
542 * shaders, and making sure that any blend shaders are stored
543 * in the same pool as the original shader. The kernel will
544 * make sure this allocation is aligned to 2^24 bytes.
548 } __attribute__((packed
));
550 /* Descriptor for the shader. Following this is at least one, up to four blend
551 * descriptors for each active render target */
553 struct mali_shader_meta
{
562 u32 uniform_buffer_count
: 4;
563 u32 unk1
: 28; // = 0x800000 for vertex, 0x958020 for tiler
566 unsigned uniform_buffer_count
: 4;
567 unsigned flags_lo
: 12;
570 unsigned work_count
: 5;
571 unsigned uniform_count
: 5;
572 unsigned flags_hi
: 6;
576 /* Same as glPolygoOffset() arguments */
582 /* Generated from SAMPLE_COVERAGE_VALUE and SAMPLE_COVERAGE_INVERT. See
583 * 13.8.3 ("Multisample Fragment Operations") in the OpenGL ES 3.2
584 * specification. Only matters when multisampling is enabled. */
589 u8 stencil_mask_front
;
590 u8 stencil_mask_back
;
593 struct mali_stencil_test stencil_front
;
594 struct mali_stencil_test stencil_back
;
599 /* On Bifrost, some system values are preloaded in
600 * registers R55-R62 by the thread dispatcher prior to
601 * the start of shader execution. This is a bitfield
602 * with one entry for each register saying which
603 * registers need to be preloaded. Right now, the known
607 * - R55 : gl_LocalInvocationID.xy
608 * - R56 : gl_LocalInvocationID.z + unknown in high 16 bits
609 * - R57 : gl_WorkGroupID.x
610 * - R58 : gl_WorkGroupID.y
611 * - R59 : gl_WorkGroupID.z
612 * - R60 : gl_GlobalInvocationID.x
613 * - R61 : gl_GlobalInvocationID.y/gl_VertexID (without base)
614 * - R62 : gl_GlobalInvocationID.z/gl_InstanceID (without base)
617 * - R55 : unknown, never seen (but the bit for this is
619 * - R56 : unknown (bit always unset)
620 * - R57 : gl_PrimitiveID
621 * - R58 : gl_FrontFacing in low bit, potentially other stuff
622 * - R59 : u16 fragment coordinates (used to compute
623 * gl_FragCoord.xy, together with sample positions)
624 * - R60 : gl_SampleMask (used in epilog, so pretty
625 * much always used, but the bit is always 0 -- is
626 * this just always pushed?)
627 * - R61 : gl_SampleMaskIn and gl_SampleID, used by
628 * varying interpolation.
629 * - R62 : unknown (bit always unset).
631 * Later GPUs (starting with Mali-G52?) support
632 * preloading float varyings into r0-r7. This is
633 * indicated by setting 0x40. There is no distinction
634 * here between 1 varying and 2.
636 u32 preload_regs
: 8;
637 /* In units of 8 bytes or 64 bits, since the
638 * uniform/const port loads 64 bits at a time.
640 u32 uniform_count
: 7;
641 u32 unk4
: 10; // = 2
650 /* Blending information for the older non-MRT Midgard HW. Check for
651 * MALI_HAS_BLEND_SHADER to decide how to interpret.
654 union midgard_blend blend
;
655 } __attribute__((packed
));
657 /* This only concerns hardware jobs */
659 /* Possible values for job_descriptor_size */
661 #define MALI_JOB_32 0
662 #define MALI_JOB_64 1
664 struct mali_job_descriptor_header
{
665 u32 exception_status
;
666 u32 first_incomplete_task
;
668 u8 job_descriptor_size
: 1;
669 enum mali_job_type job_type
: 7;
671 u8 unknown_flags
: 7;
673 u16 job_dependency_index_1
;
674 u16 job_dependency_index_2
;
676 } __attribute__((packed
));
678 /* These concern exception_status */
680 /* Access type causing a fault, paralleling AS_FAULTSTATUS_* entries in the
683 enum mali_exception_access
{
684 /* Atomic in the kernel for MMU, but that doesn't make sense for a job
685 * fault so it's just unused */
686 MALI_EXCEPTION_ACCESS_NONE
= 0,
688 MALI_EXCEPTION_ACCESS_EXECUTE
= 1,
689 MALI_EXCEPTION_ACCESS_READ
= 2,
690 MALI_EXCEPTION_ACCESS_WRITE
= 3
693 /* Details about write_value from panfrost igt tests which use it as a generic
694 * dword write primitive */
696 #define MALI_WRITE_VALUE_ZERO 3
698 struct mali_payload_write_value
{
700 u32 value_descriptor
;
703 } __attribute__((packed
));
708 * This structure lets the attribute unit compute the address of an attribute
709 * given the vertex and instance ID. Unfortunately, the way this works is
710 * rather complicated when instancing is enabled.
712 * To explain this, first we need to explain how compute and vertex threads are
713 * dispatched. This is a guess (although a pretty firm guess!) since the
714 * details are mostly hidden from the driver, except for attribute instancing.
715 * When a quad is dispatched, it receives a single, linear index. However, we
716 * need to translate that index into a (vertex id, instance id) pair, or a
717 * (local id x, local id y, local id z) triple for compute shaders (although
718 * vertex shaders and compute shaders are handled almost identically).
719 * Focusing on vertex shaders, one option would be to do:
721 * vertex_id = linear_id % num_vertices
722 * instance_id = linear_id / num_vertices
724 * but this involves a costly division and modulus by an arbitrary number.
725 * Instead, we could pad num_vertices. We dispatch padded_num_vertices *
726 * num_instances threads instead of num_vertices * num_instances, which results
727 * in some "extra" threads with vertex_id >= num_vertices, which we have to
728 * discard. The more we pad num_vertices, the more "wasted" threads we
729 * dispatch, but the division is potentially easier.
731 * One straightforward choice is to pad num_vertices to the next power of two,
732 * which means that the division and modulus are just simple bit shifts and
733 * masking. But the actual algorithm is a bit more complicated. The thread
734 * dispatcher has special support for dividing by 3, 5, 7, and 9, in addition
735 * to dividing by a power of two. This is possibly using the technique
736 * described in patent US20170010862A1. As a result, padded_num_vertices can be
737 * 1, 3, 5, 7, or 9 times a power of two. This results in less wasted threads,
738 * since we need less padding.
740 * padded_num_vertices is picked by the hardware. The driver just specifies the
741 * actual number of vertices. At least for Mali G71, the first few cases are
744 * num_vertices | padded_num_vertices
751 * Note that padded_num_vertices is a multiple of four (presumably because
752 * threads are dispatched in groups of 4). Also, padded_num_vertices is always
753 * at least one more than num_vertices, which seems like a quirk of the
754 * hardware. For larger num_vertices, the hardware uses the following
755 * algorithm: using the binary representation of num_vertices, we look at the
756 * most significant set bit as well as the following 3 bits. Let n be the
757 * number of bits after those 4 bits. Then we set padded_num_vertices according
758 * to the following table:
760 * high bits | padded_num_vertices
767 * For example, if num_vertices = 70 is passed to glDraw(), its binary
768 * representation is 1000110, so n = 3 and the high bits are 1000, and
769 * therefore padded_num_vertices = 9 * 2^3 = 72.
771 * The attribute unit works in terms of the original linear_id. if
772 * num_instances = 1, then they are the same, and everything is simple.
773 * However, with instancing things get more complicated. There are four
774 * possible modes, two of them we can group together:
776 * 1. Use the linear_id directly. Only used when there is no instancing.
778 * 2. Use the linear_id modulo a constant. This is used for per-vertex
779 * attributes with instancing enabled by making the constant equal
780 * padded_num_vertices. Because the modulus is always padded_num_vertices, this
781 * mode only supports a modulus that is a power of 2 times 1, 3, 5, 7, or 9.
782 * The shift field specifies the power of two, while the extra_flags field
783 * specifies the odd number. If shift = n and extra_flags = m, then the modulus
784 * is (2m + 1) * 2^n. As an example, if num_vertices = 70, then as computed
785 * above, padded_num_vertices = 9 * 2^3, so we should set extra_flags = 4 and
786 * shift = 3. Note that we must exactly follow the hardware algorithm used to
787 * get padded_num_vertices in order to correctly implement per-vertex
790 * 3. Divide the linear_id by a constant. In order to correctly implement
791 * instance divisors, we have to divide linear_id by padded_num_vertices times
792 * to user-specified divisor. So first we compute padded_num_vertices, again
793 * following the exact same algorithm that the hardware uses, then multiply it
794 * by the GL-level divisor to get the hardware-level divisor. This case is
795 * further divided into two more cases. If the hardware-level divisor is a
796 * power of two, then we just need to shift. The shift amount is specified by
797 * the shift field, so that the hardware-level divisor is just 2^shift.
799 * If it isn't a power of two, then we have to divide by an arbitrary integer.
800 * For that, we use the well-known technique of multiplying by an approximation
801 * of the inverse. The driver must compute the magic multiplier and shift
802 * amount, and then the hardware does the multiplication and shift. The
803 * hardware and driver also use the "round-down" optimization as described in
804 * http://ridiculousfish.com/files/faster_unsigned_division_by_constants.pdf.
805 * The hardware further assumes the multiplier is between 2^31 and 2^32, so the
806 * high bit is implicitly set to 1 even though it is set to 0 by the driver --
807 * presumably this simplifies the hardware multiplier a little. The hardware
808 * first multiplies linear_id by the multiplier and takes the high 32 bits,
809 * then applies the round-down correction if extra_flags = 1, then finally
810 * shifts right by the shift field.
812 * There are some differences between ridiculousfish's algorithm and the Mali
813 * hardware algorithm, which means that the reference code from ridiculousfish
814 * doesn't always produce the right constants. Mali does not use the pre-shift
815 * optimization, since that would make a hardware implementation slower (it
816 * would have to always do the pre-shift, multiply, and post-shift operations).
817 * It also forces the multplier to be at least 2^31, which means that the
818 * exponent is entirely fixed, so there is no trial-and-error. Altogether,
819 * given the divisor d, the algorithm the driver must follow is:
821 * 1. Set shift = floor(log2(d)).
822 * 2. Compute m = ceil(2^(shift + 32) / d) and e = 2^(shift + 32) % d.
823 * 3. If e <= 2^shift, then we need to use the round-down algorithm. Set
824 * magic_divisor = m - 1 and extra_flags = 1.
825 * 4. Otherwise, set magic_divisor = m and extra_flags = 0.
827 * Unrelated to instancing/actual attributes, images (the OpenCL kind) are
828 * implemented as special attributes, denoted by MALI_ATTR_IMAGE. For images,
829 * let shift=extra_flags=0. Stride is set to the image format's bytes-per-pixel
830 * (*NOT the row stride*). Size is set to the size of the image itself.
832 * Special internal attribtues and varyings (gl_VertexID, gl_FrontFacing, etc)
833 * use particular fixed addresses with modified structures.
836 enum mali_attr_mode
{
837 MALI_ATTR_UNUSED
= 0,
838 MALI_ATTR_LINEAR
= 1,
839 MALI_ATTR_POT_DIVIDE
= 2,
840 MALI_ATTR_MODULO
= 3,
841 MALI_ATTR_NPOT_DIVIDE
= 4,
845 /* Pseudo-address for gl_VertexID, gl_FragCoord, gl_FrontFacing */
847 #define MALI_ATTR_VERTEXID (0x22)
848 #define MALI_ATTR_INSTANCEID (0x24)
849 #define MALI_VARYING_FRAG_COORD (0x25)
850 #define MALI_VARYING_FRONT_FACING (0x26)
852 /* This magic "pseudo-address" is used as `elements` to implement
853 * gl_PointCoord. When read from a fragment shader, it generates a point
854 * coordinate per the OpenGL ES 2.0 specification. Flipped coordinate spaces
855 * require an affine transformation in the shader. */
857 #define MALI_VARYING_POINT_COORD (0x61)
859 /* Used for comparison to check if an address is special. Mostly a guess, but
860 * it doesn't really matter. */
862 #define MALI_RECORD_SPECIAL (0x100)
865 /* This is used for actual attributes. */
867 /* The bottom 3 bits are the mode */
868 mali_ptr elements
: 64 - 8;
874 /* The entry after an NPOT_DIVIDE entry has this format. It stores
875 * extra information that wouldn't fit in a normal entry.
878 u32 unk
; /* = 0x20 */
881 /* This is the original, GL-level divisor. */
884 } __attribute__((packed
));
886 struct mali_attr_meta
{
887 /* Vertex buffer index */
890 unsigned unknown1
: 2;
891 unsigned swizzle
: 12;
892 enum mali_format format
: 8;
894 /* Always observed to be zero at the moment */
895 unsigned unknown3
: 2;
897 /* When packing multiple attributes in a buffer, offset addresses by
898 * this value. Obscurely, this is signed. */
900 } __attribute__((packed
));
902 #define FBD_MASK (~0x3f)
904 /* MFBD, rather than SFBD */
905 #define MALI_MFBD (0x1)
907 /* ORed into an MFBD address to specify the fbx section is included */
908 #define MALI_MFBD_TAG_EXTRA (0x2)
910 /* Uniform buffer objects are 64-bit fields divided as:
913 * mali_ptr ptr : 64 - 10;
915 * The size is actually the size minus 1 (MALI_POSITIVE), in units of 16 bytes.
916 * This gives a maximum of 2^14 bytes, which just so happens to be the GL
917 * minimum-maximum for GL_MAX_UNIFORM_BLOCK_SIZE.
919 * The pointer is missing the bottom 2 bits and top 8 bits. The top 8 bits
920 * should be 0 for userspace pointers, according to
921 * https://lwn.net/Articles/718895/. By reusing these bits, we can make each
922 * entry in the table only 64 bits.
925 #define MALI_MAKE_UBO(elements, ptr) \
926 (MALI_POSITIVE((elements)) | (((ptr) >> 2) << 10))
928 /* On Bifrost, these fields are the same between the vertex and tiler payloads.
929 * They also seem to be the same between Bifrost and Midgard. They're shared in
933 /* Applies to unknown_draw */
935 #define MALI_DRAW_INDEXED_UINT8 (0x10)
936 #define MALI_DRAW_INDEXED_UINT16 (0x20)
937 #define MALI_DRAW_INDEXED_UINT32 (0x30)
938 #define MALI_DRAW_INDEXED_SIZE (0x30)
939 #define MALI_DRAW_INDEXED_SHIFT (4)
941 #define MALI_DRAW_VARYING_SIZE (0x100)
943 /* Set to use first vertex as the provoking vertex for flatshading. Clear to
944 * use the last vertex. This is the default in DX and VK, but not in GL. */
946 #define MALI_DRAW_FLATSHADE_FIRST (0x800)
948 #define MALI_DRAW_PRIMITIVE_RESTART_FIXED_INDEX (0x10000)
950 struct mali_vertex_tiler_prefix
{
951 /* This is a dynamic bitfield containing the following things in this order:
953 * - gl_WorkGroupSize.x
954 * - gl_WorkGroupSize.y
955 * - gl_WorkGroupSize.z
956 * - gl_NumWorkGroups.x
957 * - gl_NumWorkGroups.y
958 * - gl_NumWorkGroups.z
960 * The number of bits allocated for each number is based on the *_shift
961 * fields below. For example, workgroups_y_shift gives the bit that
962 * gl_NumWorkGroups.y starts at, and workgroups_z_shift gives the bit
963 * that gl_NumWorkGroups.z starts at (and therefore one after the bit
964 * that gl_NumWorkGroups.y ends at). The actual value for each gl_*
965 * value is one more than the stored value, since if any of the values
966 * are zero, then there would be no invocations (and hence no job). If
967 * there were 0 bits allocated to a given field, then it must be zero,
968 * and hence the real value is one.
970 * Vertex jobs reuse the same job dispatch mechanism as compute jobs,
971 * effectively doing glDispatchCompute(1, vertex_count, instance_count)
972 * where vertex count is the number of vertices.
974 u32 invocation_count
;
976 /* Bitfield for shifts:
980 * workgroups_x_shift : 6
981 * workgroups_y_shift : 6
982 * workgroups_z_shift : 6
983 * workgroups_x_shift_2 : 4
985 u32 invocation_shifts
;
988 u32 unknown_draw
: 22;
990 /* This is the the same as workgroups_x_shift_2 in compute shaders, but
991 * always 5 for vertex jobs and 6 for tiler jobs. I suspect this has
992 * something to do with how many quads get put in the same execution
993 * engine, which is a balance (you don't want to starve the engine, but
994 * you also want to distribute work evenly).
996 u32 workgroups_x_shift_3
: 6;
999 /* Negative of min_index. This is used to compute
1000 * the unbiased index in tiler/fragment shader runs.
1002 * The hardware adds offset_bias_correction in each run,
1003 * so that absent an index bias, the first vertex processed is
1004 * genuinely the first vertex (0). But with an index bias,
1005 * the first vertex process is numbered the same as the bias.
1007 * To represent this more conviniently:
1008 * unbiased_index = lower_bound_index +
1010 * offset_bias_correction
1012 * This is done since the hardware doesn't accept a index_bias
1013 * and this allows it to recover the unbiased index.
1015 int32_t offset_bias_correction
;
1018 /* Like many other strictly nonzero quantities, index_count is
1019 * subtracted by one. For an indexed cube, this is equal to 35 = 6
1020 * faces * 2 triangles/per face * 3 vertices/per triangle - 1. That is,
1021 * for an indexed draw, index_count is the number of actual vertices
1022 * rendered whereas invocation_count is the number of unique vertices
1023 * rendered (the number of times the vertex shader must be invoked).
1024 * For non-indexed draws, this is just equal to invocation_count. */
1028 /* No hidden structure; literally just a pointer to an array of uint
1029 * indices (width depends on flags). Thanks, guys, for not making my
1030 * life insane for once! NULL for non-indexed draws. */
1033 } __attribute__((packed
));
1035 /* Point size / line width can either be specified as a 32-bit float (for
1036 * constant size) or as a [machine word size]-bit GPU pointer (for varying size). If a pointer
1037 * is selected, by setting the appropriate MALI_DRAW_VARYING_SIZE bit in the tiler
1038 * payload, the contents of varying_pointer will be intepreted as an array of
1039 * fp16 sizes, one for each vertex. gl_PointSize is therefore implemented by
1040 * creating a special MALI_R16F varying writing to varying_pointer. */
1042 union midgard_primitive_size
{
1047 struct bifrost_tiler_heap_meta
{
1050 /* note: these are just guesses! */
1051 mali_ptr tiler_heap_start
;
1052 mali_ptr tiler_heap_free
;
1053 mali_ptr tiler_heap_end
;
1055 /* hierarchy weights? but they're still 0 after the job has run... */
1059 } __attribute__((packed
));
1061 struct bifrost_tiler_meta
{
1062 u32 tiler_heap_next_start
; /* To be written by the GPU */
1063 u32 used_hierarchy_mask
; /* To be written by the GPU */
1064 u16 hierarchy_mask
; /* Five values observed: 0xa, 0x14, 0x28, 0x50, 0xa0 */
1069 mali_ptr tiler_heap_meta
;
1070 /* TODO what is this used for? */
1072 } __attribute__((packed
));
1074 struct bifrost_tiler_only
{
1076 union midgard_primitive_size primitive_size
;
1078 mali_ptr tiler_meta
;
1080 u64 zero1
, zero2
, zero3
, zero4
, zero5
, zero6
;
1081 } __attribute__((packed
));
1083 struct mali_vertex_tiler_postfix
{
1084 u16 gl_enables
; // 0x6 on Midgard, 0x2 on Bifrost
1086 /* Both zero for non-instanced draws. For instanced draws, a
1087 * decomposition of padded_num_vertices. See the comments about the
1088 * corresponding fields in mali_attr for context. */
1090 unsigned instance_shift
: 5;
1091 unsigned instance_odd
: 3;
1095 /* Offset for first vertex in buffer */
1100 /* Zero for vertex jobs. Pointer to the position (gl_Position) varying
1101 * output from the vertex shader for tiler jobs.
1104 u64 position_varying
;
1106 /* An array of mali_uniform_buffer_meta's. The size is given by the
1109 u64 uniform_buffers
;
1111 /* On Bifrost, this is a pointer to an array of bifrost_texture_descriptor.
1112 * On Midgard, this is a pointer to an array of pointers to the texture
1113 * descriptors, number of pointers bounded by number of textures. The
1114 * indirection is needed to accomodate varying numbers and sizes of
1115 * texture descriptors */
1118 /* For OpenGL, from what I've seen, this is intimately connected to
1119 * texture_meta. cwabbott says this is not the case under Vulkan, hence
1120 * why this field is seperate (Midgard is Vulkan capable). Pointer to
1121 * array of sampler descriptors (which are uniform in size) */
1122 u64 sampler_descriptor
;
1126 u64 attributes
; /* struct attribute_buffer[] */
1127 u64 attribute_meta
; /* attribute_meta[] */
1128 u64 varyings
; /* struct attr */
1129 u64 varying_meta
; /* pointer */
1131 u64 occlusion_counter
; /* A single bit as far as I can tell */
1133 /* On Bifrost, this points directly to a mali_shared_memory structure.
1134 * On Midgard, this points to a framebuffer (either SFBD or MFBD as
1135 * tagged), which embeds a mali_shared_memory structure */
1136 mali_ptr shared_memory
;
1137 } __attribute__((packed
));
1139 struct midgard_payload_vertex_tiler
{
1140 struct mali_vertex_tiler_prefix prefix
;
1141 struct mali_vertex_tiler_postfix postfix
;
1143 union midgard_primitive_size primitive_size
;
1144 } __attribute__((packed
));
1146 struct bifrost_payload_vertex
{
1147 struct mali_vertex_tiler_prefix prefix
;
1148 struct mali_vertex_tiler_postfix postfix
;
1149 } __attribute__((packed
));
1151 struct bifrost_payload_tiler
{
1152 struct mali_vertex_tiler_prefix prefix
;
1153 struct bifrost_tiler_only tiler
;
1154 struct mali_vertex_tiler_postfix postfix
;
1155 } __attribute__((packed
));
1157 struct bifrost_payload_fused
{
1158 struct mali_vertex_tiler_prefix prefix
;
1159 struct bifrost_tiler_only tiler
;
1160 struct mali_vertex_tiler_postfix tiler_postfix
;
1161 u64 padding
; /* zero */
1162 struct mali_vertex_tiler_postfix vertex_postfix
;
1163 } __attribute__((packed
));
1165 /* Purposeful off-by-one in width, height fields. For example, a (64, 64)
1166 * texture is stored as (63, 63) in these fields. This adjusts for that.
1167 * There's an identical pattern in the framebuffer descriptor. Even vertex
1168 * count fields work this way, hence the generic name -- integral fields that
1169 * are strictly positive generally need this adjustment. */
1171 #define MALI_POSITIVE(dim) (dim - 1)
1173 /* Shared across both command stream and Midgard, and even with Bifrost */
1175 enum mali_texture_type
{
1176 MALI_TEX_CUBE
= 0x0,
1183 #define MAX_MIP_LEVELS (13)
1185 /* Cubemap bloats everything up */
1186 #define MAX_CUBE_FACES (6)
1188 /* For each pointer, there is an address and optionally also a stride */
1189 #define MAX_ELEMENTS (2)
1191 /* It's not known why there are 4-bits allocated -- this enum is almost
1192 * certainly incomplete */
1194 enum mali_texture_layout
{
1195 /* For a Z/S texture, this is linear */
1196 MALI_TEXTURE_TILED
= 0x1,
1198 /* Z/S textures cannot be tiled */
1199 MALI_TEXTURE_LINEAR
= 0x2,
1202 MALI_TEXTURE_AFBC
= 0xC
1205 /* Corresponds to the type passed to glTexImage2D and so forth */
1207 struct mali_texture_format
{
1208 unsigned swizzle
: 12;
1209 enum mali_format format
: 8;
1212 unsigned unknown1
: 1;
1214 enum mali_texture_type type
: 2;
1215 enum mali_texture_layout layout
: 4;
1218 unsigned unknown2
: 1;
1220 /* Set to allow packing an explicit stride */
1221 unsigned manual_stride
: 1;
1224 } __attribute__((packed
));
1226 struct mali_texture_descriptor
{
1230 uint16_t array_size
;
1232 struct mali_texture_format format
;
1236 /* One for non-mipmapped, zero for mipmapped */
1239 /* Zero for non-mipmapped, (number of levels - 1) for mipmapped */
1242 /* Swizzling is a single 32-bit word, broken up here for convenience.
1243 * Here, swizzling refers to the ES 3.0 texture parameters for channel
1244 * level swizzling, not the internal pixel-level swizzling which is
1245 * below OpenGL's reach */
1247 unsigned swizzle
: 12;
1248 unsigned swizzle_zero
: 20;
1253 } __attribute__((packed
));
1255 /* While Midgard texture descriptors are variable length, Bifrost descriptors
1256 * are fixed like samplers with more pointers to expand if necessary */
1258 struct bifrost_texture_descriptor
{
1259 unsigned format_unk
: 4; /* 2 */
1260 enum mali_texture_type type
: 2;
1262 unsigned format_swizzle
: 12;
1263 enum mali_format format
: 8;
1265 unsigned format_unk3
: 1; /* 0 */
1267 uint16_t width
; /* MALI_POSITIVE */
1268 uint16_t height
; /* MALI_POSITIVE */
1270 /* OpenGL swizzle */
1271 unsigned swizzle
: 12;
1272 enum mali_texture_layout layout
: 4;
1273 uint8_t levels
: 8; /* Number of levels-1 if mipmapped, 0 if not */
1276 unsigned levels_unk
: 24; /* 0 */
1277 unsigned level_2
: 8; /* Number of levels, again? */
1281 uint16_t array_size
;
1286 } __attribute__((packed
));
1290 #define MALI_SAMP_MAG_NEAREST (1 << 0)
1291 #define MALI_SAMP_MIN_NEAREST (1 << 1)
1293 /* TODO: What do these bits mean individually? Only seen set together */
1295 #define MALI_SAMP_MIP_LINEAR_1 (1 << 3)
1296 #define MALI_SAMP_MIP_LINEAR_2 (1 << 4)
1298 /* Flag in filter_mode, corresponding to OpenCL's NORMALIZED_COORDS_TRUE
1299 * sampler_t flag. For typical OpenGL textures, this is always set. */
1301 #define MALI_SAMP_NORM_COORDS (1 << 5)
1303 /* Used for lod encoding. Thanks @urjaman for pointing out these routines can
1304 * be cleaned up a lot. */
1306 #define DECODE_FIXED_16(x) ((float) (x / 256.0))
1308 static inline int16_t
1309 FIXED_16(float x
, bool allow_negative
)
1311 /* Clamp inputs, accounting for float error */
1312 float max_lod
= (32.0 - (1.0 / 512.0));
1313 float min_lod
= allow_negative
? -max_lod
: 0.0;
1315 x
= ((x
> max_lod
) ? max_lod
: ((x
< min_lod
) ? min_lod
: x
));
1317 return (int) (x
* 256.0);
1320 struct mali_sampler_descriptor
{
1321 uint16_t filter_mode
;
1323 /* Fixed point, signed.
1324 * Upper 7 bits before the decimal point, although it caps [0-31].
1325 * Lower 8 bits after the decimal point: int(round(x * 256)) */
1331 /* All one word in reality, but packed a bit. Comparisons are flipped
1334 enum mali_wrap_mode wrap_s
: 4;
1335 enum mali_wrap_mode wrap_t
: 4;
1336 enum mali_wrap_mode wrap_r
: 4;
1337 enum mali_func compare_func
: 3;
1339 /* No effect on 2D textures. For cubemaps, set for ES3 and clear for
1340 * ES2, controlling seamless cubemapping */
1341 unsigned seamless_cube_map
: 1;
1346 float border_color
[4];
1347 } __attribute__((packed
));
1349 /* Bifrost sampler descriptors look pretty similar */
1351 #define BIFROST_SAMP_MIN_NEAREST (1)
1352 #define BIFROST_SAMP_MAG_LINEAR (1)
1354 struct bifrost_sampler_descriptor
{
1357 enum mali_wrap_mode wrap_r
: 4;
1358 enum mali_wrap_mode wrap_t
: 4;
1359 enum mali_wrap_mode wrap_s
: 4;
1363 uint8_t norm_coords
: 1;
1365 uint8_t min_filter
: 1;
1367 uint8_t mag_filter
: 1;
1368 uint8_t mip_filter
: 1;
1376 } __attribute__((packed
));
1378 /* From presentations, 16x16 tiles externally. Use shift for fast computation
1379 * of tile numbers. */
1381 #define MALI_TILE_SHIFT 4
1382 #define MALI_TILE_LENGTH (1 << MALI_TILE_SHIFT)
1384 /* Tile coordinates are stored as a compact u32, as only 12 bits are needed to
1385 * each component. Notice that this provides a theoretical upper bound of (1 <<
1386 * 12) = 4096 tiles in each direction, addressing a maximum framebuffer of size
1387 * 65536x65536. Multiplying that together, times another four given that Mali
1388 * framebuffers are 32-bit ARGB8888, means that this upper bound would take 16
1389 * gigabytes of RAM just to store the uncompressed framebuffer itself, let
1390 * alone rendering in real-time to such a buffer.
1394 /* From mali_kbase_10969_workaround.c */
1395 #define MALI_X_COORD_MASK 0x00000FFF
1396 #define MALI_Y_COORD_MASK 0x0FFF0000
1398 /* Extract parts of a tile coordinate */
1400 #define MALI_TILE_COORD_X(coord) ((coord) & MALI_X_COORD_MASK)
1401 #define MALI_TILE_COORD_Y(coord) (((coord) & MALI_Y_COORD_MASK) >> 16)
1403 /* Helpers to generate tile coordinates based on the boundary coordinates in
1404 * screen space. So, with the bounds (0, 0) to (128, 128) for the screen, these
1405 * functions would convert it to the bounding tiles (0, 0) to (7, 7).
1406 * Intentional "off-by-one"; finding the tile number is a form of fencepost
1409 #define MALI_MAKE_TILE_COORDS(X, Y) ((X) | ((Y) << 16))
1410 #define MALI_BOUND_TO_TILE(B, bias) ((B - bias) >> MALI_TILE_SHIFT)
1411 #define MALI_COORDINATE_TO_TILE(W, H, bias) MALI_MAKE_TILE_COORDS(MALI_BOUND_TO_TILE(W, bias), MALI_BOUND_TO_TILE(H, bias))
1412 #define MALI_COORDINATE_TO_TILE_MIN(W, H) MALI_COORDINATE_TO_TILE(W, H, 0)
1413 #define MALI_COORDINATE_TO_TILE_MAX(W, H) MALI_COORDINATE_TO_TILE(W, H, 1)
1415 struct mali_payload_fragment
{
1418 mali_ptr framebuffer
;
1419 } __attribute__((packed
));
1421 /* Single Framebuffer Descriptor */
1423 /* Flags apply to format. With just MSAA_A and MSAA_B, the framebuffer is
1424 * configured for 4x. With MSAA_8, it is configured for 8x. */
1426 #define MALI_SFBD_FORMAT_MSAA_8 (1 << 3)
1427 #define MALI_SFBD_FORMAT_MSAA_A (1 << 4)
1428 #define MALI_SFBD_FORMAT_MSAA_B (1 << 4)
1429 #define MALI_SFBD_FORMAT_SRGB (1 << 5)
1431 /* Fast/slow based on whether all three buffers are cleared at once */
1433 #define MALI_CLEAR_FAST (1 << 18)
1434 #define MALI_CLEAR_SLOW (1 << 28)
1435 #define MALI_CLEAR_SLOW_STENCIL (1 << 31)
1437 /* Configures hierarchical tiling on Midgard for both SFBD/MFBD (embedded
1438 * within the larget framebuffer descriptor). Analogous to
1439 * bifrost_tiler_heap_meta and bifrost_tiler_meta*/
1441 /* See pan_tiler.c for derivation */
1442 #define MALI_HIERARCHY_MASK ((1 << 9) - 1)
1444 /* Flag disabling the tiler for clear-only jobs, with
1445 hierarchical tiling */
1446 #define MALI_TILER_DISABLED (1 << 12)
1448 /* Flag selecting userspace-generated polygon list, for clear-only jobs without
1449 * hierarhical tiling. */
1450 #define MALI_TILER_USER 0xFFF
1452 /* Absent any geometry, the minimum size of the polygon list header */
1453 #define MALI_TILER_MINIMUM_HEADER_SIZE 0x200
1455 struct midgard_tiler_descriptor
{
1456 /* Size of the entire polygon list; see pan_tiler.c for the
1457 * computation. It's based on hierarchical tiling */
1459 u32 polygon_list_size
;
1461 /* Name known from the replay workaround in the kernel. What exactly is
1462 * flagged here is less known. We do that (tiler_hierarchy_mask & 0x1ff)
1463 * specifies a mask of hierarchy weights, which explains some of the
1464 * performance mysteries around setting it. We also see the bottom bit
1465 * of tiler_flags set in the kernel, but no comment why.
1467 * hierarchy_mask can have the TILER_DISABLED flag */
1472 /* See mali_tiler.c for an explanation */
1473 mali_ptr polygon_list
;
1474 mali_ptr polygon_list_body
;
1476 /* Names based on we see symmetry with replay jobs which name these
1479 mali_ptr heap_start
; /* tiler heap_free_address */
1482 /* Hierarchy weights. We know these are weights based on the kernel,
1483 * but I've never seen them be anything other than zero */
1487 enum mali_block_format
{
1488 MALI_BLOCK_TILED
= 0x0,
1489 MALI_BLOCK_UNKNOWN
= 0x1,
1490 MALI_BLOCK_LINEAR
= 0x2,
1491 MALI_BLOCK_AFBC
= 0x3,
1494 struct mali_sfbd_format
{
1498 /* mali_channel_swizzle */
1499 unsigned swizzle
: 12;
1502 unsigned nr_channels
: 2;
1507 enum mali_block_format block
: 2;
1513 /* Shared structure at the start of framebuffer descriptors, or used bare for
1514 * compute jobs, configuring stack and shared memory */
1516 struct mali_shared_memory
{
1517 u32 stack_shift
: 4;
1520 /* Configuration for shared memory for compute shaders.
1521 * shared_workgroup_count is logarithmic and may be computed for a
1522 * compute shader using shared memory as:
1524 * shared_workgroup_count = MAX2(ceil(log2(count_x)) + ... + ceil(log2(count_z), 10)
1526 * For compute shaders that don't use shared memory, or non-compute
1527 * shaders, this is set to ~0
1530 u32 shared_workgroup_count
: 5;
1531 u32 shared_unk1
: 3;
1532 u32 shared_shift
: 4;
1533 u32 shared_zero
: 20;
1535 mali_ptr scratchpad
;
1537 /* For compute shaders, the RAM backing of workgroup-shared memory. For
1538 * fragment shaders on Bifrost, apparently multisampling locations */
1540 mali_ptr shared_memory
;
1542 } __attribute__((packed
));
1544 /* Configures multisampling on Bifrost fragment jobs */
1546 struct bifrost_multisampling
{
1549 mali_ptr sample_locations
;
1551 } __attribute__((packed
));
1553 struct mali_single_framebuffer
{
1554 struct mali_shared_memory shared_memory
;
1555 struct mali_sfbd_format format
;
1560 /* Purposeful off-by-one in these fields should be accounted for by the
1561 * MALI_DIMENSION macro */
1568 u32 checksum_stride
;
1571 /* By default, the framebuffer is upside down from OpenGL's
1572 * perspective. Set framebuffer to the end and negate the stride to
1573 * flip in the Y direction */
1575 mali_ptr framebuffer
;
1580 /* Depth and stencil buffers are interleaved, it appears, as they are
1581 * set to the same address in captures. Both fields set to zero if the
1582 * buffer is not being cleared. Depending on GL_ENABLE magic, you might
1583 * get a zero enable despite the buffer being present; that still is
1586 mali_ptr depth_buffer
; // not SAME_VA
1587 u32 depth_stride_zero
: 4;
1588 u32 depth_stride
: 28;
1591 mali_ptr stencil_buffer
; // not SAME_VA
1592 u32 stencil_stride_zero
: 4;
1593 u32 stencil_stride
: 28;
1596 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1597 u32 clear_color_2
; // always equal, but unclear function?
1598 u32 clear_color_3
; // always equal, but unclear function?
1599 u32 clear_color_4
; // always equal, but unclear function?
1601 /* Set to zero if not cleared */
1603 float clear_depth_1
; // float32, ditto
1604 float clear_depth_2
; // float32, ditto
1605 float clear_depth_3
; // float32, ditto
1606 float clear_depth_4
; // float32, ditto
1608 u32 clear_stencil
; // Exactly as it appears in OpenGL
1612 struct midgard_tiler_descriptor tiler
;
1614 /* More below this, maybe */
1615 } __attribute__((packed
));
1618 /* SINGLE to disable multisampling, AVERAGE for
1619 * EXT_multisampled_render_to_texture operation where multiple tilebuffer
1620 * samples are implicitly resolved before writeout, MULTIPLE to write multiple
1621 * samples inline, and LAYERED for ES3-style multisampling with each sample in
1622 * a different buffer.
1625 enum mali_msaa_mode
{
1626 MALI_MSAA_SINGLE
= 0,
1627 MALI_MSAA_AVERAGE
= 1,
1628 MALI_MSAA_MULTIPLE
= 2,
1629 MALI_MSAA_LAYERED
= 3,
1632 #define MALI_MFBD_FORMAT_SRGB (1 << 0)
1634 struct mali_rt_format
{
1638 unsigned nr_channels
: 2; /* MALI_POSITIVE */
1642 enum mali_block_format block
: 2;
1643 enum mali_msaa_mode msaa
: 2;
1646 unsigned swizzle
: 12;
1650 /* Disables MFBD preload. When this bit is set, the render target will
1651 * be cleared every frame. When this bit is clear, the hardware will
1652 * automatically wallpaper the render target back from main memory.
1653 * Unfortunately, MFBD preload is very broken on Midgard, so in
1654 * practice, this is a chicken bit that should always be set.
1655 * Discovered by accident, as all good chicken bits are. */
1657 unsigned no_preload
: 1;
1658 } __attribute__((packed
));
1660 /* Flags for afbc.flags and ds_afbc.flags */
1662 #define MALI_AFBC_FLAGS 0x10009
1664 /* Lossless RGB and RGBA colorspace transform */
1665 #define MALI_AFBC_YTR (1 << 17)
1667 struct mali_render_target
{
1668 struct mali_rt_format format
;
1673 /* Stuff related to ARM Framebuffer Compression. When AFBC is enabled,
1674 * there is an extra metadata buffer that contains 16 bytes per tile.
1675 * The framebuffer needs to be the same size as before, since we don't
1676 * know ahead of time how much space it will take up. The
1677 * framebuffer_stride is set to 0, since the data isn't stored linearly
1680 * When AFBC is disabled, these fields are zero.
1684 u32 stride
; // stride in units of tiles
1685 u32 flags
; // = 0x20000
1688 mali_ptr framebuffer
;
1691 u32 framebuffer_stride
: 28; // in units of bytes, row to next
1692 u32 layer_stride
; /* For multisample rendering */
1694 u32 clear_color_1
; // RGBA8888 from glClear, actually used by hardware
1695 u32 clear_color_2
; // always equal, but unclear function?
1696 u32 clear_color_3
; // always equal, but unclear function?
1697 u32 clear_color_4
; // always equal, but unclear function?
1698 } __attribute__((packed
));
1700 /* An optional part of mali_framebuffer. It comes between the main structure
1701 * and the array of render targets. It must be included if any of these are
1704 * - Transaction Elimination
1706 * - TODO: Anything else?
1710 #define MALI_EXTRA_PRESENT (0x1)
1713 #define MALI_EXTRA_ZS (0x4)
1715 struct mali_framebuffer_extra
{
1717 /* Each tile has an 8 byte checksum, so the stride is "width in tiles * 8" */
1718 u32 checksum_stride
;
1720 unsigned flags_lo
: 4;
1721 enum mali_block_format zs_block
: 2;
1723 /* Number of samples in Z/S attachment, MALI_POSITIVE. So zero for
1724 * 1-sample (non-MSAA), 0x3 for MSAA 4x, etc */
1725 unsigned zs_samples
: 4;
1726 unsigned flags_hi
: 22;
1729 /* Note: AFBC is only allowed for 24/8 combined depth/stencil. */
1731 mali_ptr depth_stencil_afbc_metadata
;
1732 u32 depth_stencil_afbc_stride
; // in units of tiles
1735 mali_ptr depth_stencil
;
1741 /* Depth becomes depth/stencil in case of combined D/S */
1743 u32 depth_stride_zero
: 4;
1744 u32 depth_stride
: 28;
1745 u32 depth_layer_stride
;
1748 u32 stencil_stride_zero
: 4;
1749 u32 stencil_stride
: 28;
1750 u32 stencil_layer_stride
;
1758 } __attribute__((packed
));
1760 /* Flags for mfbd_flags */
1762 /* Enables writing depth results back to main memory (rather than keeping them
1763 * on-chip in the tile buffer and then discarding) */
1765 #define MALI_MFBD_DEPTH_WRITE (1 << 10)
1767 /* The MFBD contains the extra mali_framebuffer_extra section */
1769 #define MALI_MFBD_EXTRA (1 << 13)
1771 struct mali_framebuffer
{
1773 struct mali_shared_memory shared_memory
;
1774 struct bifrost_multisampling msaa
;
1778 u16 width1
, height1
;
1780 u16 width2
, height2
;
1781 u32 unk1
: 19; // = 0x01000
1782 u32 rt_count_1
: 3; // off-by-one (use MALI_POSITIVE)
1783 u32 unk2
: 2; // = 0
1784 u32 rt_count_2
: 3; // no off-by-one
1787 u32 clear_stencil
: 8;
1788 u32 mfbd_flags
: 24; // = 0x100
1792 struct midgard_tiler_descriptor tiler
;
1794 mali_ptr tiler_meta
;
1799 /* optional: struct mali_framebuffer_extra extra */
1800 /* struct mali_render_target rts[] */
1801 } __attribute__((packed
));
1803 #endif /* __PANFROST_JOB_H__ */