2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef _MDG_COMPILER_H
25 #define _MDG_COMPILER_H
29 #include "midgard_compile.h"
30 #include "midgard_ops.h"
32 #include "util/hash_table.h"
33 #include "util/u_dynarray.h"
35 #include "util/list.h"
37 #include "main/mtypes.h"
38 #include "compiler/nir_types.h"
39 #include "compiler/nir/nir.h"
40 #include "panfrost/util/pan_ir.h"
41 #include "panfrost/util/lcra.h"
46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
47 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
48 * instruction is actually a discard op. */
51 #define TARGET_BREAK 1
52 #define TARGET_CONTINUE 2
53 #define TARGET_DISCARD 3
55 typedef struct midgard_branch
{
56 /* If conditional, the condition is specified in r31.w */
59 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
60 bool invert_conditional
;
62 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
65 /* The actual target */
73 /* Generic in-memory data type repesenting a single logical instruction, rather
74 * than a single instruction group. This is the preferred form for code gen.
75 * Multiple midgard_insturctions will later be combined during scheduling,
76 * though this is not represented in this structure. Its format bridges
77 * the low-level binary representation with the higher level semantic meaning.
79 * Notably, it allows registers to be specified as block local SSA, for code
80 * emitted before the register allocation pass.
83 #define MIR_SRC_COUNT 4
84 #define MIR_VEC_COMPONENTS 16
86 typedef struct midgard_instruction
{
87 /* Must be first for casting */
88 struct list_head link
;
90 unsigned type
; /* ALU, load/store, texture */
92 /* Instruction arguments represented as block-local SSA
93 * indices, rather than registers. ~0 means unused. */
94 unsigned src
[MIR_SRC_COUNT
];
97 /* vec16 swizzle, unpacked, per source */
98 unsigned swizzle
[MIR_SRC_COUNT
][MIR_VEC_COMPONENTS
];
101 nir_alu_type src_types
[MIR_SRC_COUNT
];
102 nir_alu_type dest_type
;
104 /* Special fields for an ALU instruction */
105 midgard_reg_info registers
;
107 /* For textures: should helpers execute this instruction (instead of
108 * just helping with derivatives)? Should helpers terminate after? */
109 bool helper_terminate
;
112 /* I.e. (1 << alu_bit) */
116 midgard_constants constants
;
117 uint16_t inline_constant
;
118 bool has_blend_constant
;
119 bool has_inline_constant
;
124 bool writeout_stencil
;
127 /* Masks in a saneish format. One bit per channel, not packed fancy.
128 * Use this instead of the op specific ones, and switch over at emit
133 /* For ALU ops only: set to true to invert (bitwise NOT) the
134 * destination of an integer-out op. Not implemented in hardware but
135 * allows more optimizations */
139 /* Hint for the register allocator not to spill the destination written
140 * from this instruction (because it is a spill/unspill node itself).
141 * Bitmask of spilled classes */
145 /* Generic hint for intra-pass use */
148 /* During scheduling, the backwards dependency graph
149 * (DAG). nr_dependencies is the number of unscheduled
150 * instructions that must still be scheduled after
151 * (before) this instruction. dependents are which
152 * instructions need to be scheduled before (after) this
155 unsigned nr_dependencies
;
156 BITSET_WORD
*dependents
;
158 /* For load/store ops.. force 64-bit destination */
162 midgard_load_store_word load_store
;
163 midgard_vector_alu alu
;
164 midgard_texture_word texture
;
165 midgard_branch_extended branch_extended
;
168 /* General branch, rather than packed br_compact. Higher level
169 * than the other components */
170 midgard_branch branch
;
172 } midgard_instruction
;
174 typedef struct midgard_block
{
179 /* List of midgard_bundles emitted (after the scheduler has run) */
180 struct util_dynarray bundles
;
182 /* Number of quadwords _actually_ emitted, as determined after scheduling */
183 unsigned quadword_count
;
185 /* Indicates this is a fixed-function fragment epilogue block */
188 /* Are helper invocations required by this block? */
192 typedef struct midgard_bundle
{
193 /* Tag for the overall bundle */
196 /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
197 * sadd, vadd, smul, vlut, branch) */
198 int instruction_count
;
199 midgard_instruction
*instructions
[6];
201 /* Bundle-wide ALU configuration */
204 bool has_embedded_constants
;
205 midgard_constants constants
;
206 bool has_blend_constant
;
219 typedef struct compiler_context
{
221 gl_shader_stage stage
;
223 /* Is internally a blend shader? Depends on stage == FRAGMENT */
226 /* Render target number for a keyed blend shader. Depends on is_blend */
229 /* Tracking for blend constant patching */
230 int blend_constant_offset
;
232 /* Number of bytes used for Thread Local Storage */
235 /* Count of spills and fills for shaderdb */
239 /* Current NIR function */
242 /* Allocated compiler temporary counter */
245 /* Unordered list of midgard_blocks */
247 struct list_head blocks
;
249 /* TODO merge with block_count? */
250 unsigned block_source_count
;
252 /* List of midgard_instructions emitted for the current block */
253 midgard_block
*current_block
;
255 /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
256 midgard_block
*after_block
;
258 /* The current "depth" of the loop, for disambiguating breaks/continues
259 * when using nested loops */
260 int current_loop_depth
;
262 /* Total number of loops for shader-db */
265 /* Constants which have been loaded, for later inlining */
266 struct hash_table_u64
*ssa_constants
;
268 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
269 struct hash_table_u64
*hash_to_temp
;
273 /* Set of NIR indices that were already emitted as outmods */
274 BITSET_WORD
*already_emitted
;
276 /* Just the count of the max register used. Higher count => higher
277 * register pressure */
280 /* The number of uniforms allowable for the fast path */
283 /* Count of instructions emitted from NIR overall, across all blocks */
284 int instruction_count
;
286 /* Alpha ref value passed in */
289 unsigned quadword_count
;
291 /* Bitmask of valid metadata */
294 /* Model-specific quirk set */
297 /* Writeout instructions for each render target */
298 midgard_instruction
*writeout_branch
[MIDGARD_NUM_RTS
];
300 struct panfrost_sysvals sysvals
;
303 /* Per-block live_in/live_out */
304 #define MIDGARD_METADATA_LIVENESS (1 << 0)
306 /* Helpers for manipulating the above structures (forming the driver IR) */
308 /* Append instruction to end of current block */
310 static inline midgard_instruction
*
311 mir_upload_ins(struct compiler_context
*ctx
, struct midgard_instruction ins
)
313 midgard_instruction
*heap
= ralloc(ctx
, struct midgard_instruction
);
314 memcpy(heap
, &ins
, sizeof(ins
));
318 static inline midgard_instruction
*
319 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
321 midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
322 list_addtail(&u
->link
, &ctx
->current_block
->base
.instructions
);
326 static inline struct midgard_instruction
*
327 mir_insert_instruction_before(struct compiler_context
*ctx
,
328 struct midgard_instruction
*tag
,
329 struct midgard_instruction ins
)
331 struct midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
332 list_addtail(&u
->link
, &tag
->link
);
337 mir_remove_instruction(struct midgard_instruction
*ins
)
339 list_del(&ins
->link
);
342 static inline midgard_instruction
*
343 mir_prev_op(struct midgard_instruction
*ins
)
345 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
348 static inline midgard_instruction
*
349 mir_next_op(struct midgard_instruction
*ins
)
351 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
354 #define mir_foreach_block(ctx, v) \
355 list_for_each_entry(pan_block, v, &ctx->blocks, link)
357 #define mir_foreach_block_from(ctx, from, v) \
358 list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
360 #define mir_foreach_instr_in_block(block, v) \
361 list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
362 #define mir_foreach_instr_in_block_rev(block, v) \
363 list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
365 #define mir_foreach_instr_in_block_safe(block, v) \
366 list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
368 #define mir_foreach_instr_in_block_safe_rev(block, v) \
369 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
371 #define mir_foreach_instr_in_block_from(block, v, from) \
372 list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
374 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
375 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
377 #define mir_foreach_bundle_in_block(block, v) \
378 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
380 #define mir_foreach_bundle_in_block_rev(block, v) \
381 util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
383 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
384 midgard_instruction* v; \
386 mir_foreach_bundle_in_block_rev(block, _bundle) \
387 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
389 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
391 #define mir_foreach_instr_global(ctx, v) \
392 mir_foreach_block(ctx, v_block) \
393 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
395 #define mir_foreach_instr_global_safe(ctx, v) \
396 mir_foreach_block(ctx, v_block) \
397 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
399 /* Based on set_foreach, expanded with automatic type casts */
401 #define mir_foreach_predecessor(blk, v) \
402 struct set_entry *_entry_##v; \
403 struct midgard_block *v; \
404 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
405 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL); \
406 _entry_##v != NULL; \
407 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
408 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
410 #define mir_foreach_src(ins, v) \
411 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
413 static inline midgard_instruction
*
414 mir_last_in_block(struct midgard_block
*block
)
416 return list_last_entry(&block
->base
.instructions
, struct midgard_instruction
, link
);
419 static inline midgard_block
*
420 mir_get_block(compiler_context
*ctx
, int idx
)
422 struct list_head
*lst
= &ctx
->blocks
;
427 return (struct midgard_block
*) lst
;
431 mir_is_alu_bundle(midgard_bundle
*bundle
)
433 return IS_ALU(bundle
->tag
);
436 static inline unsigned
437 make_compiler_temp(compiler_context
*ctx
)
439 return (ctx
->func
->impl
->ssa_alloc
+ ctx
->temp_alloc
++) << 1;
442 static inline unsigned
443 make_compiler_temp_reg(compiler_context
*ctx
)
445 return ((ctx
->func
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | PAN_IS_REG
;
448 static inline unsigned
449 nir_ssa_index(nir_ssa_def
*ssa
)
451 return (ssa
->index
<< 1) | 0;
454 static inline unsigned
455 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
458 return nir_ssa_index(src
->ssa
);
460 assert(!src
->reg
.indirect
);
461 return (src
->reg
.reg
->index
<< 1) | PAN_IS_REG
;
465 static inline unsigned
466 nir_dest_index(nir_dest
*dst
)
469 return (dst
->ssa
.index
<< 1) | 0;
471 assert(!dst
->reg
.indirect
);
472 return (dst
->reg
.reg
->index
<< 1) | PAN_IS_REG
;
478 /* MIR manipulation */
480 void mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new);
481 void mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new);
482 void mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new);
483 void mir_rewrite_index_dst_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
484 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
485 void mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned *swizzle
);
486 bool mir_single_use(compiler_context
*ctx
, unsigned value
);
487 bool mir_special_index(compiler_context
*ctx
, unsigned idx
);
488 unsigned mir_use_count(compiler_context
*ctx
, unsigned value
);
489 bool mir_is_written_before(compiler_context
*ctx
, midgard_instruction
*ins
, unsigned node
);
490 uint16_t mir_bytemask_of_read_components(midgard_instruction
*ins
, unsigned node
);
491 uint16_t mir_bytemask_of_read_components_index(midgard_instruction
*ins
, unsigned i
);
492 midgard_reg_mode
mir_typesize(midgard_instruction
*ins
);
493 midgard_reg_mode
mir_srcsize(midgard_instruction
*ins
, unsigned i
);
494 unsigned mir_bytes_for_mode(midgard_reg_mode mode
);
495 midgard_reg_mode
mir_mode_for_destsize(unsigned size
);
496 uint16_t mir_from_bytemask(uint16_t bytemask
, midgard_reg_mode mode
);
497 uint16_t mir_bytemask(midgard_instruction
*ins
);
498 uint16_t mir_round_bytemask_up(uint16_t mask
, midgard_reg_mode mode
);
499 void mir_set_bytemask(midgard_instruction
*ins
, uint16_t bytemask
);
500 unsigned mir_upper_override(midgard_instruction
*ins
);
504 void mir_print_instruction(midgard_instruction
*ins
);
505 void mir_print_bundle(midgard_bundle
*ctx
);
506 void mir_print_block(midgard_block
*block
);
507 void mir_print_shader(compiler_context
*ctx
);
508 bool mir_nontrivial_source2_mod(midgard_instruction
*ins
);
509 bool mir_nontrivial_source2_mod_simple(midgard_instruction
*ins
);
510 bool mir_nontrivial_outmod(midgard_instruction
*ins
);
512 void mir_insert_instruction_before_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
513 void mir_insert_instruction_after_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
514 void mir_flip(midgard_instruction
*ins
);
515 void mir_compute_temp_count(compiler_context
*ctx
);
517 void mir_set_offset(compiler_context
*ctx
, midgard_instruction
*ins
, nir_src
*offset
, bool is_shared
);
519 /* 'Intrinsic' move for aliasing */
521 static inline midgard_instruction
522 v_mov(unsigned src
, unsigned dest
)
524 midgard_instruction ins
= {
527 .src
= { ~0, src
, ~0, ~0 },
528 .src_types
= { 0, nir_type_uint32
},
529 .swizzle
= SWIZZLE_IDENTITY
,
531 .dest_type
= nir_type_uint32
,
533 .op
= midgard_alu_op_imov
,
534 .reg_mode
= midgard_reg_mode_32
,
535 .dest_override
= midgard_dest_override_none
,
536 .outmod
= midgard_outmod_int_wrap
543 /* Broad types of register classes so we can handle special
546 #define REG_CLASS_WORK 0
547 #define REG_CLASS_LDST 1
548 #define REG_CLASS_TEXR 3
549 #define REG_CLASS_TEXW 4
551 /* Like a move, but to thread local storage! */
553 static inline midgard_instruction
554 v_load_store_scratch(
560 /* We index by 32-bit vec4s */
561 unsigned byte
= (index
* 4 * 4);
563 midgard_instruction ins
= {
564 .type
= TAG_LOAD_STORE_4
,
567 .src
= { ~0, ~0, ~0, ~0 },
568 .swizzle
= SWIZZLE_IDENTITY_4
,
570 .op
= is_store
? midgard_op_st_int4
: midgard_op_ld_int4
,
572 /* For register spilling - to thread local storage */
577 /* If we spill an unspill, RA goes into an infinite loop */
578 .no_spill
= (1 << REG_CLASS_WORK
)
581 ins
.constants
.u32
[0] = byte
;
584 ins
.src
[0] = srcdest
;
586 /* Ensure we are tightly swizzled so liveness analysis is
589 for (unsigned i
= 0; i
< 4; ++i
) {
590 if (!(mask
& (1 << i
)))
591 ins
.swizzle
[0][i
] = COMPONENT_X
;
600 mir_has_arg(midgard_instruction
*ins
, unsigned arg
)
605 mir_foreach_src(ins
, i
) {
606 if (ins
->src
[i
] == arg
)
615 void midgard_schedule_program(compiler_context
*ctx
);
617 void mir_ra(compiler_context
*ctx
);
618 void mir_squeeze_index(compiler_context
*ctx
);
619 void mir_lower_special_reads(compiler_context
*ctx
);
620 void mir_liveness_ins_update(uint16_t *live
, midgard_instruction
*ins
, unsigned max
);
621 void mir_compute_liveness(compiler_context
*ctx
);
622 void mir_invalidate_liveness(compiler_context
*ctx
);
623 bool mir_is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
);
625 void mir_create_pipeline_registers(compiler_context
*ctx
);
626 void midgard_promote_uniforms(compiler_context
*ctx
);
629 midgard_emit_derivatives(compiler_context
*ctx
, nir_alu_instr
*instr
);
632 midgard_lower_derivatives(compiler_context
*ctx
, midgard_block
*block
);
634 bool mir_op_computes_derivatives(gl_shader_stage stage
, unsigned op
);
636 void mir_analyze_helper_terminate(compiler_context
*ctx
);
637 void mir_analyze_helper_requirements(compiler_context
*ctx
);
641 void emit_binary_bundle(
642 compiler_context
*ctx
,
643 midgard_bundle
*bundle
,
644 struct util_dynarray
*emission
,
648 nir_undef_to_zero(nir_shader
*shader
);
650 void midgard_nir_lod_errata(nir_shader
*shader
);
654 bool midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
);
655 bool midgard_opt_combine_projection(compiler_context
*ctx
, midgard_block
*block
);
656 bool midgard_opt_varying_projection(compiler_context
*ctx
, midgard_block
*block
);
657 bool midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
);
658 bool midgard_opt_dead_move_eliminate(compiler_context
*ctx
, midgard_block
*block
);
660 void midgard_lower_invert(compiler_context
*ctx
, midgard_block
*block
);
661 bool midgard_opt_not_propagate(compiler_context
*ctx
, midgard_block
*block
);
662 bool midgard_opt_fuse_src_invert(compiler_context
*ctx
, midgard_block
*block
);
663 bool midgard_opt_fuse_dest_invert(compiler_context
*ctx
, midgard_block
*block
);
664 bool midgard_opt_csel_invert(compiler_context
*ctx
, midgard_block
*block
);
665 bool midgard_opt_promote_fmov(compiler_context
*ctx
, midgard_block
*block
);
666 bool midgard_opt_drop_cmp_invert(compiler_context
*ctx
, midgard_block
*block
);
667 bool midgard_opt_invert_branch(compiler_context
*ctx
, midgard_block
*block
);