2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef _MDG_COMPILER_H
25 #define _MDG_COMPILER_H
29 #include "midgard_compile.h"
31 #include "util/hash_table.h"
32 #include "util/u_dynarray.h"
34 #include "util/list.h"
36 #include "main/mtypes.h"
37 #include "compiler/nir_types.h"
38 #include "compiler/nir/nir.h"
43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
44 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
45 * instruction is actually a discard op. */
48 #define TARGET_BREAK 1
49 #define TARGET_CONTINUE 2
50 #define TARGET_DISCARD 3
52 typedef struct midgard_branch
{
53 /* If conditional, the condition is specified in r31.w */
56 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
57 bool invert_conditional
;
59 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
62 /* The actual target */
70 /* Instruction arguments represented as block-local SSA indices, rather than
71 * registers. Negative values mean unused. */
80 /* Generic in-memory data type repesenting a single logical instruction, rather
81 * than a single instruction group. This is the preferred form for code gen.
82 * Multiple midgard_insturctions will later be combined during scheduling,
83 * though this is not represented in this structure. Its format bridges
84 * the low-level binary representation with the higher level semantic meaning.
86 * Notably, it allows registers to be specified as block local SSA, for code
87 * emitted before the register allocation pass.
90 typedef struct midgard_instruction
{
91 /* Must be first for casting */
92 struct list_head link
;
94 unsigned type
; /* ALU, load/store, texture */
96 /* If the register allocator has not run yet... */
99 /* Special fields for an ALU instruction */
100 midgard_reg_info registers
;
102 /* I.e. (1 << alu_bit) */
105 /* When emitting bundle, should this instruction have a break forced
106 * before it? Used for r31 writes which are valid only within a single
107 * bundle and *need* to happen as early as possible... this is a hack,
108 * TODO remove when we have a scheduler */
113 uint16_t inline_constant
;
114 bool has_blend_constant
;
118 bool prepacked_branch
;
120 /* Kind of a hack, but hint against aggressive DCE */
123 /* Masks in a saneish format. One bit per channel, not packed fancy.
124 * Use this instead of the op specific ones, and switch over at emit
129 /* For ALU ops only: set to true to invert (bitwise NOT) the
130 * destination of an integer-out op. Not imeplemented in hardware but
131 * allows more optimizations */
135 /* Hint for the register allocator not to spill the destination written
136 * from this instruction (because it is a spill/unspill node itself) */
140 /* Generic hint for intra-pass use */
144 midgard_load_store_word load_store
;
145 midgard_vector_alu alu
;
146 midgard_texture_word texture
;
147 midgard_branch_extended branch_extended
;
150 /* General branch, rather than packed br_compact. Higher level
151 * than the other components */
152 midgard_branch branch
;
154 } midgard_instruction
;
156 typedef struct midgard_block
{
157 /* Link to next block. Must be first for mir_get_block */
158 struct list_head link
;
160 /* List of midgard_instructions emitted for the current block */
161 struct list_head instructions
;
165 /* List of midgard_bundles emitted (after the scheduler has run) */
166 struct util_dynarray bundles
;
168 /* Number of quadwords _actually_ emitted, as determined after scheduling */
169 unsigned quadword_count
;
171 /* Succeeding blocks. The compiler should not necessarily rely on
172 * source-order traversal */
173 struct midgard_block
*successors
[2];
174 unsigned nr_successors
;
176 struct set
*predecessors
;
178 /* The successors pointer form a graph, and in the case of
179 * complex control flow, this graph has a cycles. To aid
180 * traversal during liveness analysis, we have a visited?
181 * boolean for passes to use as they see fit, provided they
186 typedef struct midgard_bundle
{
187 /* Tag for the overall bundle */
190 /* Instructions contained by the bundle */
191 int instruction_count
;
192 midgard_instruction
*instructions
[5];
194 /* Bundle-wide ALU configuration */
197 bool has_embedded_constants
;
199 bool has_blend_constant
;
202 typedef struct compiler_context
{
204 gl_shader_stage stage
;
206 /* The screen we correspond to */
207 struct midgard_screen
*screen
;
209 /* Is internally a blend shader? Depends on stage == FRAGMENT */
212 /* Tracking for blend constant patching */
213 int blend_constant_offset
;
215 /* Number of bytes used for Thread Local Storage */
218 /* Count of spills and fills for shaderdb */
222 /* Current NIR function */
225 /* Allocated compiler temporary counter */
228 /* Unordered list of midgard_blocks */
230 struct list_head blocks
;
232 /* List of midgard_instructions emitted for the current block */
233 midgard_block
*current_block
;
235 /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
236 midgard_block
*after_block
;
238 /* The current "depth" of the loop, for disambiguating breaks/continues
239 * when using nested loops */
240 int current_loop_depth
;
242 /* Total number of loops for shader-db */
245 /* Constants which have been loaded, for later inlining */
246 struct hash_table_u64
*ssa_constants
;
248 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
249 struct hash_table_u64
*hash_to_temp
;
253 /* Just the count of the max register used. Higher count => higher
254 * register pressure */
257 /* Used for cont/last hinting. Increase when a tex op is added.
258 * Decrease when a tex op is removed. */
259 int texture_op_count
;
261 /* Mapping of texture register -> SSA index for unaliasing */
262 int texture_index
[2];
264 /* The number of uniforms allowable for the fast path */
267 /* Count of instructions emitted from NIR overall, across all blocks */
268 int instruction_count
;
270 /* Alpha ref value passed in */
273 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
274 unsigned sysvals
[MAX_SYSVAL_COUNT
];
275 unsigned sysval_count
;
276 struct hash_table_u64
*sysval_to_id
;
279 /* Helpers for manipulating the above structures (forming the driver IR) */
281 /* Append instruction to end of current block */
283 static inline midgard_instruction
*
284 mir_upload_ins(struct midgard_instruction ins
)
286 midgard_instruction
*heap
= malloc(sizeof(ins
));
287 memcpy(heap
, &ins
, sizeof(ins
));
291 static inline midgard_instruction
*
292 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
294 midgard_instruction
*u
= mir_upload_ins(ins
);
295 list_addtail(&u
->link
, &ctx
->current_block
->instructions
);
299 static inline struct midgard_instruction
*
300 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
302 struct midgard_instruction
*u
= mir_upload_ins(ins
);
303 list_addtail(&u
->link
, &tag
->link
);
308 mir_remove_instruction(struct midgard_instruction
*ins
)
310 list_del(&ins
->link
);
313 static inline midgard_instruction
*
314 mir_prev_op(struct midgard_instruction
*ins
)
316 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
319 static inline midgard_instruction
*
320 mir_next_op(struct midgard_instruction
*ins
)
322 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
325 #define mir_foreach_block(ctx, v) \
326 list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
328 #define mir_foreach_block_from(ctx, from, v) \
329 list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
331 #define mir_foreach_instr(ctx, v) \
332 list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
334 #define mir_foreach_instr_safe(ctx, v) \
335 list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
337 #define mir_foreach_instr_in_block(block, v) \
338 list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
339 #define mir_foreach_instr_in_block_rev(block, v) \
340 list_for_each_entry_rev(struct midgard_instruction, v, &block->instructions, link)
342 #define mir_foreach_instr_in_block_safe(block, v) \
343 list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
345 #define mir_foreach_instr_in_block_safe_rev(block, v) \
346 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
348 #define mir_foreach_instr_in_block_from(block, v, from) \
349 list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
351 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
352 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
354 #define mir_foreach_bundle_in_block(block, v) \
355 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
357 #define mir_foreach_instr_global(ctx, v) \
358 mir_foreach_block(ctx, v_block) \
359 mir_foreach_instr_in_block(v_block, v)
361 #define mir_foreach_instr_global_safe(ctx, v) \
362 mir_foreach_block(ctx, v_block) \
363 mir_foreach_instr_in_block_safe(v_block, v)
365 #define mir_foreach_successor(blk, v) \
366 struct midgard_block *v; \
367 struct midgard_block **_v; \
368 for (_v = &blk->successors[0], \
370 v != NULL && _v < &blk->successors[2]; \
373 /* Based on set_foreach, expanded with automatic type casts */
375 #define mir_foreach_predecessor(blk, v) \
376 struct set_entry *_entry_##v; \
377 struct midgard_block *v; \
378 for (_entry_##v = _mesa_set_next_entry(blk->predecessors, NULL), \
379 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL); \
380 _entry_##v != NULL; \
381 _entry_##v = _mesa_set_next_entry(blk->predecessors, _entry_##v), \
382 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
384 #define mir_foreach_src(ins, v) \
385 for (unsigned v = 0; v < ARRAY_SIZE(ins->ssa_args.src); ++v)
387 static inline midgard_instruction
*
388 mir_last_in_block(struct midgard_block
*block
)
390 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
393 static inline midgard_block
*
394 mir_get_block(compiler_context
*ctx
, int idx
)
396 struct list_head
*lst
= &ctx
->blocks
;
401 return (struct midgard_block
*) lst
;
404 static inline midgard_block
*
405 mir_exit_block(struct compiler_context
*ctx
)
407 midgard_block
*last
= list_last_entry(&ctx
->blocks
,
408 struct midgard_block
, link
);
410 /* The last block must be empty (the exit block) */
411 assert(list_empty(&last
->instructions
));
412 assert(last
->nr_successors
== 0);
418 mir_is_alu_bundle(midgard_bundle
*bundle
)
420 return IS_ALU(bundle
->tag
);
423 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
427 static inline unsigned
428 make_compiler_temp(compiler_context
*ctx
)
430 return (ctx
->func
->impl
->ssa_alloc
+ ctx
->temp_alloc
++) << 1;
433 static inline unsigned
434 make_compiler_temp_reg(compiler_context
*ctx
)
436 return ((ctx
->func
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | IS_REG
;
439 static inline unsigned
440 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
443 return (src
->ssa
->index
<< 1) | 0;
445 assert(!src
->reg
.indirect
);
446 return (src
->reg
.reg
->index
<< 1) | IS_REG
;
450 static inline unsigned
451 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
453 return nir_src_index(ctx
, &src
->src
);
456 static inline unsigned
457 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
460 return (dst
->ssa
.index
<< 1) | 0;
462 assert(!dst
->reg
.indirect
);
463 return (dst
->reg
.reg
->index
<< 1) | IS_REG
;
469 /* MIR manipulation */
471 void mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new);
472 void mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new);
473 void mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new);
474 void mir_rewrite_index_dst_tag(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned tag
);
475 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
476 void mir_rewrite_index_src_tag(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned tag
);
477 void mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned swizzle
);
478 bool mir_single_use(compiler_context
*ctx
, unsigned value
);
479 bool mir_special_index(compiler_context
*ctx
, unsigned idx
);
480 unsigned mir_use_count(compiler_context
*ctx
, unsigned value
);
481 bool mir_is_written_before(compiler_context
*ctx
, midgard_instruction
*ins
, unsigned node
);
482 unsigned mir_mask_of_read_components(midgard_instruction
*ins
, unsigned node
);
483 unsigned mir_ubo_shift(midgard_load_store_op op
);
487 void mir_print_instruction(midgard_instruction
*ins
);
488 void mir_print_bundle(midgard_bundle
*ctx
);
489 void mir_print_block(midgard_block
*block
);
490 void mir_print_shader(compiler_context
*ctx
);
491 bool mir_nontrivial_source2_mod(midgard_instruction
*ins
);
492 bool mir_nontrivial_source2_mod_simple(midgard_instruction
*ins
);
493 bool mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
);
494 bool mir_nontrivial_outmod(midgard_instruction
*ins
);
498 static const midgard_vector_alu_src blank_alu_src
= {
499 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
502 static const midgard_vector_alu_src blank_alu_src_xxxx
= {
503 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
506 static const midgard_scalar_alu_src blank_scalar_alu_src
= {
510 /* Used for encoding the unused source of 1-op instructions */
511 static const midgard_vector_alu_src zero_alu_src
= { 0 };
513 /* 'Intrinsic' move for aliasing */
515 static inline midgard_instruction
516 v_mov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
518 midgard_instruction ins
= {
522 .src
= { SSA_UNUSED_1
, src
, -1 },
526 .op
= midgard_alu_op_imov
,
527 .reg_mode
= midgard_reg_mode_32
,
528 .dest_override
= midgard_dest_override_none
,
529 .outmod
= midgard_outmod_int_wrap
,
530 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
531 .src2
= vector_alu_srco_unsigned(mod
)
539 mir_has_arg(midgard_instruction
*ins
, unsigned arg
)
541 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
->ssa_args
.src
); ++i
) {
542 if (ins
->ssa_args
.src
[i
] == arg
)
551 void schedule_program(compiler_context
*ctx
);
553 /* Register allocation */
557 /* Broad types of register classes so we can handle special
560 #define NR_REG_CLASSES 5
562 #define REG_CLASS_WORK 0
563 #define REG_CLASS_LDST 1
564 #define REG_CLASS_LDST27 2
565 #define REG_CLASS_TEXR 3
566 #define REG_CLASS_TEXW 4
568 void mir_lower_special_reads(compiler_context
*ctx
);
569 struct ra_graph
* allocate_registers(compiler_context
*ctx
, bool *spilled
);
570 void install_registers(compiler_context
*ctx
, struct ra_graph
*g
);
571 bool mir_is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
);
572 bool mir_has_multiple_writes(compiler_context
*ctx
, int src
);
574 void mir_create_pipeline_registers(compiler_context
*ctx
);
577 midgard_promote_uniforms(compiler_context
*ctx
, unsigned promoted_count
);
579 midgard_instruction
*
581 compiler_context
*ctx
,
585 nir_src
*indirect_offset
,
589 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
, unsigned nr_components
);
592 midgard_emit_derivatives(compiler_context
*ctx
, nir_alu_instr
*instr
);
595 midgard_lower_derivatives(compiler_context
*ctx
, midgard_block
*block
);
597 bool mir_op_computes_derivatives(unsigned op
);
601 void emit_binary_bundle(
602 compiler_context
*ctx
,
603 midgard_bundle
*bundle
,
604 struct util_dynarray
*emission
,
607 /* NIR stuff. TODO: Move? Share? Something? */
610 nir_undef_to_zero(nir_shader
*shader
);
613 nir_clamp_psiz(nir_shader
*shader
, float min_size
, float max_size
);
617 bool midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
);
618 bool midgard_opt_combine_projection(compiler_context
*ctx
, midgard_block
*block
);
619 bool midgard_opt_varying_projection(compiler_context
*ctx
, midgard_block
*block
);
620 bool midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
);
621 bool midgard_opt_dead_move_eliminate(compiler_context
*ctx
, midgard_block
*block
);
622 void midgard_opt_post_move_eliminate(compiler_context
*ctx
, midgard_block
*block
, struct ra_graph
*g
);
624 void midgard_lower_invert(compiler_context
*ctx
, midgard_block
*block
);
625 bool midgard_opt_not_propagate(compiler_context
*ctx
, midgard_block
*block
);
626 bool midgard_opt_fuse_src_invert(compiler_context
*ctx
, midgard_block
*block
);
627 bool midgard_opt_fuse_dest_invert(compiler_context
*ctx
, midgard_block
*block
);