src/panfrost/midgard/compiler.h

   1 /*
   2  * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  */
  23
  24 #ifndef _MDG_COMPILER_H
  25 #define _MDG_COMPILER_H
  26
  27 #include "midgard.h"
  28 #include "helpers.h"
  29 #include "midgard_compile.h"
  30
  31 #include "util/hash_table.h"
  32 #include "util/u_dynarray.h"
  33 #include "util/set.h"
  34 #include "util/list.h"
  35
  36 #include "main/mtypes.h"
  37 #include "compiler/nir_types.h"
  38 #include "compiler/nir/nir.h"
  39
  40 /* Forward declare */
  41 struct midgard_block;
  42
  43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
  44  * the hardware), hence why that must be zero. TARGET_DISCARD signals this
  45  * instruction is actually a discard op. */
  46
  47 #define TARGET_GOTO 0
  48 #define TARGET_BREAK 1
  49 #define TARGET_CONTINUE 2
  50 #define TARGET_DISCARD 3
  51
  52 typedef struct midgard_branch {
  53         /* If conditional, the condition is specified in r31.w */
  54         bool conditional;
  55
  56         /* For conditionals, if this is true, we branch on FALSE. If false, we  branch on TRUE. */
  57         bool invert_conditional;
  58
  59         /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
  60         unsigned target_type;
  61
  62         /* The actual target */
  63         union {
  64                 int target_block;
  65                 int target_break;
  66                 int target_continue;
  67         };
  68 } midgard_branch;
  69
  70 /* Instruction arguments represented as block-local SSA indices, rather than
  71  * registers. Negative values mean unused. */
  72
  73 typedef struct {
  74         int src0;
  75         int src1;
  76         int dest;
  77
  78         /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
  79          * in. Only valid for ALU ops. */
  80         bool inline_constant;
  81 } ssa_args;
  82
  83 /* Generic in-memory data type repesenting a single logical instruction, rather
  84  * than a single instruction group. This is the preferred form for code gen.
  85  * Multiple midgard_insturctions will later be combined during scheduling,
  86  * though this is not represented in this structure.  Its format bridges
  87  * the low-level binary representation with the higher level semantic meaning.
  88  *
  89  * Notably, it allows registers to be specified as block local SSA, for code
  90  * emitted before the register allocation pass.
  91  */
  92
  93 typedef struct midgard_instruction {
  94         /* Must be first for casting */
  95         struct list_head link;
  96
  97         unsigned type; /* ALU, load/store, texture */
  98
  99         /* If the register allocator has not run yet... */
 100         ssa_args ssa_args;
 101
 102         /* Special fields for an ALU instruction */
 103         midgard_reg_info registers;
 104
 105         /* I.e. (1 << alu_bit) */
 106         int unit;
 107
 108         /* When emitting bundle, should this instruction have a break forced
 109          * before it? Used for r31 writes which are valid only within a single
 110          * bundle and *need* to happen as early as possible... this is a hack,
 111          * TODO remove when we have a scheduler */
 112         bool precede_break;
 113
 114         bool has_constants;
 115         float constants[4];
 116         uint16_t inline_constant;
 117         bool has_blend_constant;
 118
 119         bool compact_branch;
 120         bool writeout;
 121         bool prepacked_branch;
 122
 123         /* Masks in a saneish format. One bit per channel, not packed fancy.
 124          * Use this instead of the op specific ones, and switch over at emit
 125          * time */
 126
 127         uint16_t mask;
 128
 129         /* For ALU ops only: set to true to invert (bitwise NOT) the
 130          * destination of an integer-out op. Not imeplemented in hardware but
 131          * allows more optimizations */
 132
 133         bool invert;
 134
 135         union {
 136                 midgard_load_store_word load_store;
 137                 midgard_vector_alu alu;
 138                 midgard_texture_word texture;
 139                 midgard_branch_extended branch_extended;
 140                 uint16_t br_compact;
 141
 142                 /* General branch, rather than packed br_compact. Higher level
 143                  * than the other components */
 144                 midgard_branch branch;
 145         };
 146 } midgard_instruction;
 147
 148 typedef struct midgard_block {
 149         /* Link to next block. Must be first for mir_get_block */
 150         struct list_head link;
 151
 152         /* List of midgard_instructions emitted for the current block */
 153         struct list_head instructions;
 154
 155         bool is_scheduled;
 156
 157         /* List of midgard_bundles emitted (after the scheduler has run) */
 158         struct util_dynarray bundles;
 159
 160         /* Number of quadwords _actually_ emitted, as determined after scheduling */
 161         unsigned quadword_count;
 162
 163         /* Successors: always one forward (the block after us), maybe
 164          * one backwards (for a backward branch). No need for a second
 165          * forward, since graph traversal would get there eventually
 166          * anyway */
 167         struct midgard_block *successors[2];
 168         unsigned nr_successors;
 169
 170         /* The successors pointer form a graph, and in the case of
 171          * complex control flow, this graph has a cycles. To aid
 172          * traversal during liveness analysis, we have a visited?
 173          * boolean for passes to use as they see fit, provided they
 174          * clean up later */
 175         bool visited;
 176 } midgard_block;
 177
 178 typedef struct midgard_bundle {
 179         /* Tag for the overall bundle */
 180         int tag;
 181
 182         /* Instructions contained by the bundle */
 183         int instruction_count;
 184         midgard_instruction *instructions[5];
 185
 186         /* Bundle-wide ALU configuration */
 187         int padding;
 188         int control;
 189         bool has_embedded_constants;
 190         float constants[4];
 191         bool has_blend_constant;
 192 } midgard_bundle;
 193
 194 typedef struct compiler_context {
 195         nir_shader *nir;
 196         gl_shader_stage stage;
 197
 198         /* The screen we correspond to */
 199         struct midgard_screen *screen;
 200
 201         /* Is internally a blend shader? Depends on stage == FRAGMENT */
 202         bool is_blend;
 203
 204         /* Tracking for blend constant patching */
 205         int blend_constant_offset;
 206
 207         /* Number of bytes used for Thread Local Storage */
 208         unsigned tls_size;
 209
 210         /* Count of spills and fills for shaderdb */
 211         unsigned spills;
 212         unsigned fills;
 213
 214         /* Current NIR function */
 215         nir_function *func;
 216
 217         /* Allocated compiler temporary counter */
 218         unsigned temp_alloc;
 219
 220         /* Unordered list of midgard_blocks */
 221         int block_count;
 222         struct list_head blocks;
 223
 224         midgard_block *initial_block;
 225         midgard_block *previous_source_block;
 226         midgard_block *final_block;
 227
 228         /* List of midgard_instructions emitted for the current block */
 229         midgard_block *current_block;
 230
 231         /* The current "depth" of the loop, for disambiguating breaks/continues
 232          * when using nested loops */
 233         int current_loop_depth;
 234
 235         /* Total number of loops for shader-db */
 236         unsigned loop_count;
 237
 238         /* Constants which have been loaded, for later inlining */
 239         struct hash_table_u64 *ssa_constants;
 240
 241         /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
 242         struct hash_table_u64 *hash_to_temp;
 243         int temp_count;
 244         int max_hash;
 245
 246         /* Just the count of the max register used. Higher count => higher
 247          * register pressure */
 248         int work_registers;
 249
 250         /* Used for cont/last hinting. Increase when a tex op is added.
 251          * Decrease when a tex op is removed. */
 252         int texture_op_count;
 253
 254         /* Mapping of texture register -> SSA index for unaliasing */
 255         int texture_index[2];
 256
 257         /* The number of uniforms allowable for the fast path */
 258         int uniform_cutoff;
 259
 260         /* Count of instructions emitted from NIR overall, across all blocks */
 261         int instruction_count;
 262
 263         /* Alpha ref value passed in */
 264         float alpha_ref;
 265
 266         /* The index corresponding to the fragment output */
 267         unsigned fragment_output;
 268
 269         /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
 270         unsigned sysvals[MAX_SYSVAL_COUNT];
 271         unsigned sysval_count;
 272         struct hash_table_u64 *sysval_to_id;
 273 } compiler_context;
 274
 275 /* Helpers for manipulating the above structures (forming the driver IR) */
 276
 277 /* Append instruction to end of current block */
 278
 279 static inline midgard_instruction *
 280 mir_upload_ins(struct midgard_instruction ins)
 281 {
 282         midgard_instruction *heap = malloc(sizeof(ins));
 283         memcpy(heap, &ins, sizeof(ins));
 284         return heap;
 285 }
 286
 287 static inline void
 288 emit_mir_instruction(struct compiler_context *ctx, struct midgard_instruction ins)
 289 {
 290         list_addtail(&(mir_upload_ins(ins))->link, &ctx->current_block->instructions);
 291 }
 292
 293 static inline struct midgard_instruction *
 294 mir_insert_instruction_before(struct midgard_instruction *tag, struct midgard_instruction ins)
 295 {
 296         struct midgard_instruction *u = mir_upload_ins(ins);
 297         list_addtail(&u->link, &tag->link);
 298         return u;
 299 }
 300
 301 static inline void
 302 mir_remove_instruction(struct midgard_instruction *ins)
 303 {
 304         list_del(&ins->link);
 305 }
 306
 307 static inline midgard_instruction*
 308 mir_prev_op(struct midgard_instruction *ins)
 309 {
 310         return list_last_entry(&(ins->link), midgard_instruction, link);
 311 }
 312
 313 static inline midgard_instruction*
 314 mir_next_op(struct midgard_instruction *ins)
 315 {
 316         return list_first_entry(&(ins->link), midgard_instruction, link);
 317 }
 318
 319 #define mir_foreach_block(ctx, v) \
 320         list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
 321
 322 #define mir_foreach_block_from(ctx, from, v) \
 323         list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
 324
 325 #define mir_foreach_instr(ctx, v) \
 326         list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 327
 328 #define mir_foreach_instr_safe(ctx, v) \
 329         list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
 330
 331 #define mir_foreach_instr_in_block(block, v) \
 332         list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
 333
 334 #define mir_foreach_instr_in_block_safe(block, v) \
 335         list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
 336
 337 #define mir_foreach_instr_in_block_safe_rev(block, v) \
 338         list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
 339
 340 #define mir_foreach_instr_in_block_from(block, v, from) \
 341         list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
 342
 343 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
 344         list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
 345
 346 #define mir_foreach_bundle_in_block(block, v) \
 347         util_dynarray_foreach(&block->bundles, midgard_bundle, v)
 348
 349 #define mir_foreach_instr_global(ctx, v) \
 350         mir_foreach_block(ctx, v_block) \
 351                 mir_foreach_instr_in_block(v_block, v)
 352
 353 #define mir_foreach_instr_global_safe(ctx, v) \
 354         mir_foreach_block(ctx, v_block) \
 355                 mir_foreach_instr_in_block_safe(v_block, v)
 356
 357 static inline midgard_instruction *
 358 mir_last_in_block(struct midgard_block *block)
 359 {
 360         return list_last_entry(&block->instructions, struct midgard_instruction, link);
 361 }
 362
 363 static inline midgard_block *
 364 mir_get_block(compiler_context *ctx, int idx)
 365 {
 366         struct list_head *lst = &ctx->blocks;
 367
 368         while ((idx--) + 1)
 369                 lst = lst->next;
 370
 371         return (struct midgard_block *) lst;
 372 }
 373
 374 static inline bool
 375 mir_is_alu_bundle(midgard_bundle *bundle)
 376 {
 377         return IS_ALU(bundle->tag);
 378 }
 379
 380 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
 381
 382 #define IS_REG (1)
 383
 384 static inline unsigned
 385 make_compiler_temp(compiler_context *ctx)
 386 {
 387         return (ctx->func->impl->ssa_alloc + ctx->temp_alloc++) << 1;
 388 }
 389
 390 static inline unsigned
 391 make_compiler_temp_reg(compiler_context *ctx)
 392 {
 393         return ((ctx->func->impl->reg_alloc + ctx->temp_alloc++) << 1) | IS_REG;
 394 }
 395
 396 static inline unsigned
 397 nir_src_index(compiler_context *ctx, nir_src *src)
 398 {
 399         if (src->is_ssa)
 400                 return (src->ssa->index << 1) | 0;
 401         else {
 402                 assert(!src->reg.indirect);
 403                 return (src->reg.reg->index << 1) | IS_REG;
 404         }
 405 }
 406
 407 static inline unsigned
 408 nir_alu_src_index(compiler_context *ctx, nir_alu_src *src)
 409 {
 410         return nir_src_index(ctx, &src->src);
 411 }
 412
 413 static inline unsigned
 414 nir_dest_index(compiler_context *ctx, nir_dest *dst)
 415 {
 416         if (dst->is_ssa)
 417                 return (dst->ssa.index << 1) | 0;
 418         else {
 419                 assert(!dst->reg.indirect);
 420                 return (dst->reg.reg->index << 1) | IS_REG;
 421         }
 422 }
 423
 424
 425
 426 /* MIR manipulation */
 427
 428 void mir_rewrite_index(compiler_context *ctx, unsigned old, unsigned new);
 429 void mir_rewrite_index_src(compiler_context *ctx, unsigned old, unsigned new);
 430 void mir_rewrite_index_dst(compiler_context *ctx, unsigned old, unsigned new);
 431 void mir_rewrite_index_dst_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 432 void mir_rewrite_index_src_single(midgard_instruction *ins, unsigned old, unsigned new);
 433 void mir_rewrite_index_src_tag(compiler_context *ctx, unsigned old, unsigned new, unsigned tag);
 434 void mir_rewrite_index_src_swizzle(compiler_context *ctx, unsigned old, unsigned new, unsigned swizzle);
 435 bool mir_single_use(compiler_context *ctx, unsigned value);
 436 bool mir_special_index(compiler_context *ctx, unsigned idx);
 437 unsigned mir_use_count(compiler_context *ctx, unsigned value);
 438 bool mir_is_written_before(compiler_context *ctx, midgard_instruction *ins, unsigned node);
 439 unsigned mir_mask_of_read_components(midgard_instruction *ins, unsigned node);
 440
 441 /* MIR printing */
 442
 443 void mir_print_instruction(midgard_instruction *ins);
 444 void mir_print_bundle(midgard_bundle *ctx);
 445 void mir_print_block(midgard_block *block);
 446 void mir_print_shader(compiler_context *ctx);
 447 bool mir_nontrivial_source2_mod(midgard_instruction *ins);
 448 bool mir_nontrivial_source2_mod_simple(midgard_instruction *ins);
 449 bool mir_nontrivial_mod(midgard_vector_alu_src src, bool is_int, unsigned mask);
 450 bool mir_nontrivial_outmod(midgard_instruction *ins);
 451
 452 /* MIR goodies */
 453
 454 static const midgard_vector_alu_src blank_alu_src = {
 455         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_Y, COMPONENT_Z, COMPONENT_W),
 456 };
 457
 458 static const midgard_vector_alu_src blank_alu_src_xxxx = {
 459         .swizzle = SWIZZLE(COMPONENT_X, COMPONENT_X, COMPONENT_X, COMPONENT_X),
 460 };
 461
 462 static const midgard_scalar_alu_src blank_scalar_alu_src = {
 463         .full = true
 464 };
 465
 466 /* Used for encoding the unused source of 1-op instructions */
 467 static const midgard_vector_alu_src zero_alu_src = { 0 };
 468
 469 /* 'Intrinsic' move for aliasing */
 470
 471 static inline midgard_instruction
 472 v_mov(unsigned src, midgard_vector_alu_src mod, unsigned dest)
 473 {
 474         midgard_instruction ins = {
 475                 .type = TAG_ALU_4,
 476                 .mask = 0xF,
 477                 .ssa_args = {
 478                         .src0 = SSA_UNUSED_1,
 479                         .src1 = src,
 480                         .dest = dest,
 481                 },
 482                 .alu = {
 483                         .op = midgard_alu_op_imov,
 484                         .reg_mode = midgard_reg_mode_32,
 485                         .dest_override = midgard_dest_override_none,
 486                         .outmod = midgard_outmod_int_wrap,
 487                         .src1 = vector_alu_srco_unsigned(zero_alu_src),
 488                         .src2 = vector_alu_srco_unsigned(mod)
 489                 },
 490         };
 491
 492         return ins;
 493 }
 494
 495 static inline bool
 496 mir_has_arg(midgard_instruction *ins, unsigned arg)
 497 {
 498         if (ins->ssa_args.src0 == arg)
 499                 return true;
 500
 501         if (ins->ssa_args.src1 == arg && !ins->ssa_args.inline_constant)
 502                 return true;
 503
 504         return false;
 505 }
 506
 507 /* Scheduling */
 508
 509 void schedule_program(compiler_context *ctx);
 510
 511 /* Register allocation */
 512
 513 struct ra_graph;
 514
 515 /* Broad types of register classes so we can handle special
 516  * registers */
 517
 518 #define NR_REG_CLASSES 5
 519
 520 #define REG_CLASS_WORK          0
 521 #define REG_CLASS_LDST          1
 522 #define REG_CLASS_LDST27        2
 523 #define REG_CLASS_TEXR          3
 524 #define REG_CLASS_TEXW          4
 525
 526 void mir_lower_special_reads(compiler_context *ctx);
 527 struct ra_graph* allocate_registers(compiler_context *ctx, bool *spilled);
 528 void install_registers(compiler_context *ctx, struct ra_graph *g);
 529 bool mir_is_live_after(compiler_context *ctx, midgard_block *block, midgard_instruction *start, int src);
 530 bool mir_has_multiple_writes(compiler_context *ctx, int src);
 531
 532 void mir_create_pipeline_registers(compiler_context *ctx);
 533
 534 void
 535 midgard_promote_uniforms(compiler_context *ctx, unsigned pressure);
 536
 537 void
 538 emit_ubo_read(
 539         compiler_context *ctx,
 540         unsigned dest,
 541         unsigned offset,
 542         nir_src *indirect_offset,
 543         unsigned index);
 544
 545 void
 546 midgard_emit_derivatives(compiler_context *ctx, nir_alu_instr *instr);
 547
 548 void
 549 midgard_lower_derivatives(compiler_context *ctx, midgard_block *block);
 550
 551 bool mir_op_computes_derivatives(unsigned op);
 552
 553 /* Final emission */
 554
 555 void emit_binary_bundle(
 556         compiler_context *ctx,
 557         midgard_bundle *bundle,
 558         struct util_dynarray *emission,
 559         int next_tag);
 560
 561 /* NIR stuff. TODO: Move? Share? Something? */
 562
 563 bool
 564 nir_undef_to_zero(nir_shader *shader);
 565
 566 void
 567 nir_clamp_psiz(nir_shader *shader, float min_size, float max_size);
 568
 569 /* Optimizations */
 570
 571 bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
 572 bool midgard_opt_combine_projection(compiler_context *ctx, midgard_block *block);
 573 bool midgard_opt_varying_projection(compiler_context *ctx, midgard_block *block);
 574 bool midgard_opt_dead_code_eliminate(compiler_context *ctx, midgard_block *block);
 575 bool midgard_opt_dead_move_eliminate(compiler_context *ctx, midgard_block *block);
 576 void midgard_opt_post_move_eliminate(compiler_context *ctx, midgard_block *block, struct ra_graph *g);
 577
 578 void midgard_lower_invert(compiler_context *ctx, midgard_block *block);
 579 bool midgard_opt_not_propagate(compiler_context *ctx, midgard_block *block);
 580 bool midgard_opt_fuse_src_invert(compiler_context *ctx, midgard_block *block);
 581 bool midgard_opt_fuse_dest_invert(compiler_context *ctx, midgard_block *block);
 582
 583 #endif