2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef _MDG_COMPILER_H
25 #define _MDG_COMPILER_H
29 #include "midgard_compile.h"
31 #include "util/hash_table.h"
32 #include "util/u_dynarray.h"
34 #include "util/list.h"
36 #include "main/mtypes.h"
37 #include "compiler/nir_types.h"
38 #include "compiler/nir/nir.h"
43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
44 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
45 * instruction is actually a discard op. */
48 #define TARGET_BREAK 1
49 #define TARGET_CONTINUE 2
50 #define TARGET_DISCARD 3
52 typedef struct midgard_branch
{
53 /* If conditional, the condition is specified in r31.w */
56 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
57 bool invert_conditional
;
59 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
62 /* The actual target */
70 /* Instruction arguments represented as block-local SSA indices, rather than
71 * registers. Negative values mean unused. */
78 /* src1 is -not- SSA but instead a 16-bit inline constant to be smudged
79 * in. Only valid for ALU ops. */
83 /* Generic in-memory data type repesenting a single logical instruction, rather
84 * than a single instruction group. This is the preferred form for code gen.
85 * Multiple midgard_insturctions will later be combined during scheduling,
86 * though this is not represented in this structure. Its format bridges
87 * the low-level binary representation with the higher level semantic meaning.
89 * Notably, it allows registers to be specified as block local SSA, for code
90 * emitted before the register allocation pass.
93 typedef struct midgard_instruction
{
94 /* Must be first for casting */
95 struct list_head link
;
97 unsigned type
; /* ALU, load/store, texture */
99 /* If the register allocator has not run yet... */
102 /* Special fields for an ALU instruction */
103 midgard_reg_info registers
;
105 /* I.e. (1 << alu_bit) */
108 /* When emitting bundle, should this instruction have a break forced
109 * before it? Used for r31 writes which are valid only within a single
110 * bundle and *need* to happen as early as possible... this is a hack,
111 * TODO remove when we have a scheduler */
116 uint16_t inline_constant
;
117 bool has_blend_constant
;
121 bool prepacked_branch
;
123 /* Masks in a saneish format. One bit per channel, not packed fancy.
124 * Use this instead of the op specific ones, and switch over at emit
129 midgard_load_store_word load_store
;
130 midgard_vector_alu alu
;
131 midgard_texture_word texture
;
132 midgard_branch_extended branch_extended
;
135 /* General branch, rather than packed br_compact. Higher level
136 * than the other components */
137 midgard_branch branch
;
139 } midgard_instruction
;
141 typedef struct midgard_block
{
142 /* Link to next block. Must be first for mir_get_block */
143 struct list_head link
;
145 /* List of midgard_instructions emitted for the current block */
146 struct list_head instructions
;
150 /* List of midgard_bundles emitted (after the scheduler has run) */
151 struct util_dynarray bundles
;
153 /* Number of quadwords _actually_ emitted, as determined after scheduling */
154 unsigned quadword_count
;
156 /* Successors: always one forward (the block after us), maybe
157 * one backwards (for a backward branch). No need for a second
158 * forward, since graph traversal would get there eventually
160 struct midgard_block
*successors
[2];
161 unsigned nr_successors
;
163 /* The successors pointer form a graph, and in the case of
164 * complex control flow, this graph has a cycles. To aid
165 * traversal during liveness analysis, we have a visited?
166 * boolean for passes to use as they see fit, provided they
171 typedef struct midgard_bundle
{
172 /* Tag for the overall bundle */
175 /* Instructions contained by the bundle */
176 int instruction_count
;
177 midgard_instruction
*instructions
[5];
179 /* Bundle-wide ALU configuration */
182 bool has_embedded_constants
;
184 bool has_blend_constant
;
187 typedef struct compiler_context
{
189 gl_shader_stage stage
;
191 /* Is internally a blend shader? Depends on stage == FRAGMENT */
194 /* Tracking for blend constant patching */
195 int blend_constant_offset
;
197 /* Number of bytes used for Thread Local Storage */
200 /* Current NIR function */
203 /* Unordered list of midgard_blocks */
205 struct list_head blocks
;
207 midgard_block
*initial_block
;
208 midgard_block
*previous_source_block
;
209 midgard_block
*final_block
;
211 /* List of midgard_instructions emitted for the current block */
212 midgard_block
*current_block
;
214 /* The current "depth" of the loop, for disambiguating breaks/continues
215 * when using nested loops */
216 int current_loop_depth
;
218 /* Total number of loops for shader-db */
221 /* Constants which have been loaded, for later inlining */
222 struct hash_table_u64
*ssa_constants
;
224 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
225 struct hash_table_u64
*hash_to_temp
;
229 /* Just the count of the max register used. Higher count => higher
230 * register pressure */
233 /* Used for cont/last hinting. Increase when a tex op is added.
234 * Decrease when a tex op is removed. */
235 int texture_op_count
;
237 /* Mapping of texture register -> SSA index for unaliasing */
238 int texture_index
[2];
240 /* If any path hits a discard instruction */
243 /* The number of uniforms allowable for the fast path */
246 /* Count of instructions emitted from NIR overall, across all blocks */
247 int instruction_count
;
249 /* Alpha ref value passed in */
252 /* The index corresponding to the fragment output */
253 unsigned fragment_output
;
255 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
256 unsigned sysvals
[MAX_SYSVAL_COUNT
];
257 unsigned sysval_count
;
258 struct hash_table_u64
*sysval_to_id
;
261 /* Helpers for manipulating the above structures (forming the driver IR) */
263 /* Append instruction to end of current block */
265 static inline midgard_instruction
*
266 mir_upload_ins(struct midgard_instruction ins
)
268 midgard_instruction
*heap
= malloc(sizeof(ins
));
269 memcpy(heap
, &ins
, sizeof(ins
));
274 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
276 list_addtail(&(mir_upload_ins(ins
))->link
, &ctx
->current_block
->instructions
);
280 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
282 list_addtail(&(mir_upload_ins(ins
))->link
, &tag
->link
);
286 mir_remove_instruction(struct midgard_instruction
*ins
)
288 list_del(&ins
->link
);
291 static inline midgard_instruction
*
292 mir_prev_op(struct midgard_instruction
*ins
)
294 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
297 static inline midgard_instruction
*
298 mir_next_op(struct midgard_instruction
*ins
)
300 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
303 #define mir_foreach_block(ctx, v) \
304 list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
306 #define mir_foreach_block_from(ctx, from, v) \
307 list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
309 #define mir_foreach_instr(ctx, v) \
310 list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
312 #define mir_foreach_instr_safe(ctx, v) \
313 list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
315 #define mir_foreach_instr_in_block(block, v) \
316 list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
318 #define mir_foreach_instr_in_block_safe(block, v) \
319 list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
321 #define mir_foreach_instr_in_block_safe_rev(block, v) \
322 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
324 #define mir_foreach_instr_in_block_from(block, v, from) \
325 list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
327 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
328 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
330 #define mir_foreach_bundle_in_block(block, v) \
331 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
333 #define mir_foreach_instr_global(ctx, v) \
334 mir_foreach_block(ctx, v_block) \
335 mir_foreach_instr_in_block(v_block, v)
337 #define mir_foreach_instr_global_safe(ctx, v) \
338 mir_foreach_block(ctx, v_block) \
339 mir_foreach_instr_in_block_safe(v_block, v)
343 static inline midgard_instruction
*
344 mir_last_in_block(struct midgard_block
*block
)
346 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
349 static inline midgard_block
*
350 mir_get_block(compiler_context
*ctx
, int idx
)
352 struct list_head
*lst
= &ctx
->blocks
;
357 return (struct midgard_block
*) lst
;
361 mir_is_alu_bundle(midgard_bundle
*bundle
)
363 return IS_ALU(bundle
->tag
);
366 /* MIR manipulation */
368 void mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new);
369 void mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new);
370 void mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new);
371 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
375 void mir_print_instruction(midgard_instruction
*ins
);
376 void mir_print_bundle(midgard_bundle
*ctx
);
377 void mir_print_block(midgard_block
*block
);
378 void mir_print_shader(compiler_context
*ctx
);
382 static const midgard_vector_alu_src blank_alu_src
= {
383 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
386 static const midgard_vector_alu_src blank_alu_src_xxxx
= {
387 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
390 static const midgard_scalar_alu_src blank_scalar_alu_src
= {
394 /* Used for encoding the unused source of 1-op instructions */
395 static const midgard_vector_alu_src zero_alu_src
= { 0 };
397 /* 'Intrinsic' move for aliasing */
399 static inline midgard_instruction
400 v_mov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
402 midgard_instruction ins
= {
406 .src0
= SSA_UNUSED_1
,
411 .op
= midgard_alu_op_imov
,
412 .reg_mode
= midgard_reg_mode_32
,
413 .dest_override
= midgard_dest_override_none
,
414 .outmod
= midgard_outmod_int_wrap
,
415 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
416 .src2
= vector_alu_srco_unsigned(mod
)
424 mir_has_arg(midgard_instruction
*ins
, unsigned arg
)
426 if (ins
->ssa_args
.src0
== arg
)
429 if (ins
->ssa_args
.src1
== arg
&& !ins
->ssa_args
.inline_constant
)
437 void schedule_program(compiler_context
*ctx
);
439 /* Register allocation */
443 struct ra_graph
* allocate_registers(compiler_context
*ctx
, bool *spilled
);
444 void install_registers(compiler_context
*ctx
, struct ra_graph
*g
);
445 bool mir_is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
);
446 bool mir_has_multiple_writes(compiler_context
*ctx
, int src
);
448 void mir_create_pipeline_registers(compiler_context
*ctx
);
451 midgard_promote_uniforms(compiler_context
*ctx
, unsigned pressure
);
455 compiler_context
*ctx
,
458 nir_src
*indirect_offset
,
464 void emit_binary_bundle(
465 compiler_context
*ctx
,
466 midgard_bundle
*bundle
,
467 struct util_dynarray
*emission
,
470 /* NIR stuff. TODO: Move? Share? Something? */
473 nir_undef_to_zero(nir_shader
*shader
);
476 nir_clamp_psiz(nir_shader
*shader
, float min_size
, float max_size
);