2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef _MDG_COMPILER_H
25 #define _MDG_COMPILER_H
29 #include "midgard_compile.h"
31 #include "util/hash_table.h"
32 #include "util/u_dynarray.h"
34 #include "util/list.h"
36 #include "main/mtypes.h"
37 #include "compiler/nir_types.h"
38 #include "compiler/nir/nir.h"
43 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
44 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
45 * instruction is actually a discard op. */
48 #define TARGET_BREAK 1
49 #define TARGET_CONTINUE 2
50 #define TARGET_DISCARD 3
52 typedef struct midgard_branch
{
53 /* If conditional, the condition is specified in r31.w */
56 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
57 bool invert_conditional
;
59 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
62 /* The actual target */
70 /* Instruction arguments represented as block-local SSA indices, rather than
71 * registers. Negative values mean unused. */
80 /* Generic in-memory data type repesenting a single logical instruction, rather
81 * than a single instruction group. This is the preferred form for code gen.
82 * Multiple midgard_insturctions will later be combined during scheduling,
83 * though this is not represented in this structure. Its format bridges
84 * the low-level binary representation with the higher level semantic meaning.
86 * Notably, it allows registers to be specified as block local SSA, for code
87 * emitted before the register allocation pass.
90 typedef struct midgard_instruction
{
91 /* Must be first for casting */
92 struct list_head link
;
94 unsigned type
; /* ALU, load/store, texture */
96 /* If the register allocator has not run yet... */
99 /* Special fields for an ALU instruction */
100 midgard_reg_info registers
;
102 /* I.e. (1 << alu_bit) */
105 /* When emitting bundle, should this instruction have a break forced
106 * before it? Used for r31 writes which are valid only within a single
107 * bundle and *need* to happen as early as possible... this is a hack,
108 * TODO remove when we have a scheduler */
113 uint16_t inline_constant
;
114 bool has_blend_constant
;
118 bool prepacked_branch
;
120 /* Kind of a hack, but hint against aggressive DCE */
123 /* Masks in a saneish format. One bit per channel, not packed fancy.
124 * Use this instead of the op specific ones, and switch over at emit
129 /* For ALU ops only: set to true to invert (bitwise NOT) the
130 * destination of an integer-out op. Not imeplemented in hardware but
131 * allows more optimizations */
135 /* Hint for the register allocator not to spill the destination written
136 * from this instruction (because it is a spill/unspill node itself) */
140 /* Generic hint for intra-pass use */
144 midgard_load_store_word load_store
;
145 midgard_vector_alu alu
;
146 midgard_texture_word texture
;
147 midgard_branch_extended branch_extended
;
150 /* General branch, rather than packed br_compact. Higher level
151 * than the other components */
152 midgard_branch branch
;
154 } midgard_instruction
;
156 typedef struct midgard_block
{
157 /* Link to next block. Must be first for mir_get_block */
158 struct list_head link
;
160 /* List of midgard_instructions emitted for the current block */
161 struct list_head instructions
;
165 /* List of midgard_bundles emitted (after the scheduler has run) */
166 struct util_dynarray bundles
;
168 /* Number of quadwords _actually_ emitted, as determined after scheduling */
169 unsigned quadword_count
;
171 /* Succeeding blocks. The compiler should not necessarily rely on
172 * source-order traversal */
173 struct midgard_block
*successors
[4];
174 unsigned nr_successors
;
176 /* The successors pointer form a graph, and in the case of
177 * complex control flow, this graph has a cycles. To aid
178 * traversal during liveness analysis, we have a visited?
179 * boolean for passes to use as they see fit, provided they
184 typedef struct midgard_bundle
{
185 /* Tag for the overall bundle */
188 /* Instructions contained by the bundle */
189 int instruction_count
;
190 midgard_instruction
*instructions
[5];
192 /* Bundle-wide ALU configuration */
195 bool has_embedded_constants
;
197 bool has_blend_constant
;
200 typedef struct compiler_context
{
202 gl_shader_stage stage
;
204 /* The screen we correspond to */
205 struct midgard_screen
*screen
;
207 /* Is internally a blend shader? Depends on stage == FRAGMENT */
210 /* Tracking for blend constant patching */
211 int blend_constant_offset
;
213 /* Number of bytes used for Thread Local Storage */
216 /* Count of spills and fills for shaderdb */
220 /* Current NIR function */
223 /* Allocated compiler temporary counter */
226 /* Unordered list of midgard_blocks */
228 struct list_head blocks
;
230 /* List of midgard_instructions emitted for the current block */
231 midgard_block
*current_block
;
233 /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
234 midgard_block
*after_block
;
236 /* The current "depth" of the loop, for disambiguating breaks/continues
237 * when using nested loops */
238 int current_loop_depth
;
240 /* Total number of loops for shader-db */
243 /* Constants which have been loaded, for later inlining */
244 struct hash_table_u64
*ssa_constants
;
246 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
247 struct hash_table_u64
*hash_to_temp
;
251 /* Just the count of the max register used. Higher count => higher
252 * register pressure */
255 /* Used for cont/last hinting. Increase when a tex op is added.
256 * Decrease when a tex op is removed. */
257 int texture_op_count
;
259 /* Mapping of texture register -> SSA index for unaliasing */
260 int texture_index
[2];
262 /* The number of uniforms allowable for the fast path */
265 /* Count of instructions emitted from NIR overall, across all blocks */
266 int instruction_count
;
268 /* Alpha ref value passed in */
271 /* The mapping of sysvals to uniforms, the count, and the off-by-one inverse */
272 unsigned sysvals
[MAX_SYSVAL_COUNT
];
273 unsigned sysval_count
;
274 struct hash_table_u64
*sysval_to_id
;
277 /* Helpers for manipulating the above structures (forming the driver IR) */
279 /* Append instruction to end of current block */
281 static inline midgard_instruction
*
282 mir_upload_ins(struct midgard_instruction ins
)
284 midgard_instruction
*heap
= malloc(sizeof(ins
));
285 memcpy(heap
, &ins
, sizeof(ins
));
289 static inline midgard_instruction
*
290 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
292 midgard_instruction
*u
= mir_upload_ins(ins
);
293 list_addtail(&u
->link
, &ctx
->current_block
->instructions
);
297 static inline struct midgard_instruction
*
298 mir_insert_instruction_before(struct midgard_instruction
*tag
, struct midgard_instruction ins
)
300 struct midgard_instruction
*u
= mir_upload_ins(ins
);
301 list_addtail(&u
->link
, &tag
->link
);
306 mir_remove_instruction(struct midgard_instruction
*ins
)
308 list_del(&ins
->link
);
311 static inline midgard_instruction
*
312 mir_prev_op(struct midgard_instruction
*ins
)
314 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
317 static inline midgard_instruction
*
318 mir_next_op(struct midgard_instruction
*ins
)
320 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
323 #define mir_foreach_block(ctx, v) \
324 list_for_each_entry(struct midgard_block, v, &ctx->blocks, link)
326 #define mir_foreach_block_from(ctx, from, v) \
327 list_for_each_entry_from(struct midgard_block, v, from, &ctx->blocks, link)
329 #define mir_foreach_instr(ctx, v) \
330 list_for_each_entry(struct midgard_instruction, v, &ctx->current_block->instructions, link)
332 #define mir_foreach_instr_safe(ctx, v) \
333 list_for_each_entry_safe(struct midgard_instruction, v, &ctx->current_block->instructions, link)
335 #define mir_foreach_instr_in_block(block, v) \
336 list_for_each_entry(struct midgard_instruction, v, &block->instructions, link)
338 #define mir_foreach_instr_in_block_safe(block, v) \
339 list_for_each_entry_safe(struct midgard_instruction, v, &block->instructions, link)
341 #define mir_foreach_instr_in_block_safe_rev(block, v) \
342 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->instructions, link)
344 #define mir_foreach_instr_in_block_from(block, v, from) \
345 list_for_each_entry_from(struct midgard_instruction, v, from, &block->instructions, link)
347 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
348 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->instructions, link)
350 #define mir_foreach_bundle_in_block(block, v) \
351 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
353 #define mir_foreach_instr_global(ctx, v) \
354 mir_foreach_block(ctx, v_block) \
355 mir_foreach_instr_in_block(v_block, v)
357 #define mir_foreach_instr_global_safe(ctx, v) \
358 mir_foreach_block(ctx, v_block) \
359 mir_foreach_instr_in_block_safe(v_block, v)
361 static inline midgard_instruction
*
362 mir_last_in_block(struct midgard_block
*block
)
364 return list_last_entry(&block
->instructions
, struct midgard_instruction
, link
);
367 static inline midgard_block
*
368 mir_get_block(compiler_context
*ctx
, int idx
)
370 struct list_head
*lst
= &ctx
->blocks
;
375 return (struct midgard_block
*) lst
;
379 mir_is_alu_bundle(midgard_bundle
*bundle
)
381 return IS_ALU(bundle
->tag
);
384 /* Registers/SSA are distinguish in the backend by the bottom-most bit */
388 static inline unsigned
389 make_compiler_temp(compiler_context
*ctx
)
391 return (ctx
->func
->impl
->ssa_alloc
+ ctx
->temp_alloc
++) << 1;
394 static inline unsigned
395 make_compiler_temp_reg(compiler_context
*ctx
)
397 return ((ctx
->func
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | IS_REG
;
400 static inline unsigned
401 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
404 return (src
->ssa
->index
<< 1) | 0;
406 assert(!src
->reg
.indirect
);
407 return (src
->reg
.reg
->index
<< 1) | IS_REG
;
411 static inline unsigned
412 nir_alu_src_index(compiler_context
*ctx
, nir_alu_src
*src
)
414 return nir_src_index(ctx
, &src
->src
);
417 static inline unsigned
418 nir_dest_index(compiler_context
*ctx
, nir_dest
*dst
)
421 return (dst
->ssa
.index
<< 1) | 0;
423 assert(!dst
->reg
.indirect
);
424 return (dst
->reg
.reg
->index
<< 1) | IS_REG
;
430 /* MIR manipulation */
432 void mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new);
433 void mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new);
434 void mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new);
435 void mir_rewrite_index_dst_tag(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned tag
);
436 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
437 void mir_rewrite_index_src_tag(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned tag
);
438 void mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned swizzle
);
439 bool mir_single_use(compiler_context
*ctx
, unsigned value
);
440 bool mir_special_index(compiler_context
*ctx
, unsigned idx
);
441 unsigned mir_use_count(compiler_context
*ctx
, unsigned value
);
442 bool mir_is_written_before(compiler_context
*ctx
, midgard_instruction
*ins
, unsigned node
);
443 unsigned mir_mask_of_read_components(midgard_instruction
*ins
, unsigned node
);
444 unsigned mir_ubo_shift(midgard_load_store_op op
);
448 void mir_print_instruction(midgard_instruction
*ins
);
449 void mir_print_bundle(midgard_bundle
*ctx
);
450 void mir_print_block(midgard_block
*block
);
451 void mir_print_shader(compiler_context
*ctx
);
452 bool mir_nontrivial_source2_mod(midgard_instruction
*ins
);
453 bool mir_nontrivial_source2_mod_simple(midgard_instruction
*ins
);
454 bool mir_nontrivial_mod(midgard_vector_alu_src src
, bool is_int
, unsigned mask
);
455 bool mir_nontrivial_outmod(midgard_instruction
*ins
);
459 static const midgard_vector_alu_src blank_alu_src
= {
460 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_Y
, COMPONENT_Z
, COMPONENT_W
),
463 static const midgard_vector_alu_src blank_alu_src_xxxx
= {
464 .swizzle
= SWIZZLE(COMPONENT_X
, COMPONENT_X
, COMPONENT_X
, COMPONENT_X
),
467 static const midgard_scalar_alu_src blank_scalar_alu_src
= {
471 /* Used for encoding the unused source of 1-op instructions */
472 static const midgard_vector_alu_src zero_alu_src
= { 0 };
474 /* 'Intrinsic' move for aliasing */
476 static inline midgard_instruction
477 v_mov(unsigned src
, midgard_vector_alu_src mod
, unsigned dest
)
479 midgard_instruction ins
= {
483 .src
= { SSA_UNUSED_1
, src
, -1 },
487 .op
= midgard_alu_op_imov
,
488 .reg_mode
= midgard_reg_mode_32
,
489 .dest_override
= midgard_dest_override_none
,
490 .outmod
= midgard_outmod_int_wrap
,
491 .src1
= vector_alu_srco_unsigned(zero_alu_src
),
492 .src2
= vector_alu_srco_unsigned(mod
)
500 mir_has_arg(midgard_instruction
*ins
, unsigned arg
)
502 for (unsigned i
= 0; i
< ARRAY_SIZE(ins
->ssa_args
.src
); ++i
) {
503 if (ins
->ssa_args
.src
[i
] == arg
)
512 void schedule_program(compiler_context
*ctx
);
514 /* Register allocation */
518 /* Broad types of register classes so we can handle special
521 #define NR_REG_CLASSES 5
523 #define REG_CLASS_WORK 0
524 #define REG_CLASS_LDST 1
525 #define REG_CLASS_LDST27 2
526 #define REG_CLASS_TEXR 3
527 #define REG_CLASS_TEXW 4
529 void mir_lower_special_reads(compiler_context
*ctx
);
530 struct ra_graph
* allocate_registers(compiler_context
*ctx
, bool *spilled
);
531 void install_registers(compiler_context
*ctx
, struct ra_graph
*g
);
532 bool mir_is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
);
533 bool mir_has_multiple_writes(compiler_context
*ctx
, int src
);
535 void mir_create_pipeline_registers(compiler_context
*ctx
);
538 midgard_promote_uniforms(compiler_context
*ctx
, unsigned promoted_count
);
540 midgard_instruction
*
542 compiler_context
*ctx
,
546 nir_src
*indirect_offset
,
550 emit_sysval_read(compiler_context
*ctx
, nir_instr
*instr
, signed dest_override
, unsigned nr_components
);
553 midgard_emit_derivatives(compiler_context
*ctx
, nir_alu_instr
*instr
);
556 midgard_lower_derivatives(compiler_context
*ctx
, midgard_block
*block
);
558 bool mir_op_computes_derivatives(unsigned op
);
562 void emit_binary_bundle(
563 compiler_context
*ctx
,
564 midgard_bundle
*bundle
,
565 struct util_dynarray
*emission
,
568 /* NIR stuff. TODO: Move? Share? Something? */
571 nir_undef_to_zero(nir_shader
*shader
);
574 nir_clamp_psiz(nir_shader
*shader
, float min_size
, float max_size
);
578 bool midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
);
579 bool midgard_opt_combine_projection(compiler_context
*ctx
, midgard_block
*block
);
580 bool midgard_opt_varying_projection(compiler_context
*ctx
, midgard_block
*block
);
581 bool midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
);
582 bool midgard_opt_dead_move_eliminate(compiler_context
*ctx
, midgard_block
*block
);
583 void midgard_opt_post_move_eliminate(compiler_context
*ctx
, midgard_block
*block
, struct ra_graph
*g
);
585 void midgard_lower_invert(compiler_context
*ctx
, midgard_block
*block
);
586 bool midgard_opt_not_propagate(compiler_context
*ctx
, midgard_block
*block
);
587 bool midgard_opt_fuse_src_invert(compiler_context
*ctx
, midgard_block
*block
);
588 bool midgard_opt_fuse_dest_invert(compiler_context
*ctx
, midgard_block
*block
);