2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef _MDG_COMPILER_H
25 #define _MDG_COMPILER_H
29 #include "midgard_compile.h"
30 #include "midgard_ops.h"
32 #include "util/hash_table.h"
33 #include "util/u_dynarray.h"
35 #include "util/list.h"
37 #include "main/mtypes.h"
38 #include "compiler/nir_types.h"
39 #include "compiler/nir/nir.h"
40 #include "panfrost/util/pan_ir.h"
41 #include "panfrost/util/lcra.h"
46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
47 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
48 * instruction is actually a discard op. */
51 #define TARGET_BREAK 1
52 #define TARGET_CONTINUE 2
53 #define TARGET_DISCARD 3
55 typedef struct midgard_branch
{
56 /* If conditional, the condition is specified in r31.w */
59 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
60 bool invert_conditional
;
62 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
65 /* The actual target */
73 /* Generic in-memory data type repesenting a single logical instruction, rather
74 * than a single instruction group. This is the preferred form for code gen.
75 * Multiple midgard_insturctions will later be combined during scheduling,
76 * though this is not represented in this structure. Its format bridges
77 * the low-level binary representation with the higher level semantic meaning.
79 * Notably, it allows registers to be specified as block local SSA, for code
80 * emitted before the register allocation pass.
83 #define MIR_SRC_COUNT 4
84 #define MIR_VEC_COMPONENTS 16
86 typedef struct midgard_instruction
{
87 /* Must be first for casting */
88 struct list_head link
;
90 unsigned type
; /* ALU, load/store, texture */
92 /* Instruction arguments represented as block-local SSA
93 * indices, rather than registers. ~0 means unused. */
94 unsigned src
[MIR_SRC_COUNT
];
97 /* vec16 swizzle, unpacked, per source */
98 unsigned swizzle
[MIR_SRC_COUNT
][MIR_VEC_COMPONENTS
];
101 nir_alu_type src_types
[MIR_SRC_COUNT
];
102 nir_alu_type dest_type
;
104 /* Modifiers, depending on type */
107 bool src_abs
[MIR_SRC_COUNT
];
108 bool src_neg
[MIR_SRC_COUNT
];
112 bool src_shift
[MIR_SRC_COUNT
];
116 /* Out of the union for csel (could maybe be fixed..) */
117 bool src_invert
[MIR_SRC_COUNT
];
119 /* Special fields for an ALU instruction */
120 midgard_reg_info registers
;
122 /* For textures: should helpers execute this instruction (instead of
123 * just helping with derivatives)? Should helpers terminate after? */
124 bool helper_terminate
;
127 /* I.e. (1 << alu_bit) */
131 midgard_constants constants
;
132 uint16_t inline_constant
;
133 bool has_blend_constant
;
134 bool has_inline_constant
;
139 bool writeout_stencil
;
142 /* Masks in a saneish format. One bit per channel, not packed fancy.
143 * Use this instead of the op specific ones, and switch over at emit
148 /* Hint for the register allocator not to spill the destination written
149 * from this instruction (because it is a spill/unspill node itself).
150 * Bitmask of spilled classes */
154 /* Generic hint for intra-pass use */
157 /* During scheduling, the backwards dependency graph
158 * (DAG). nr_dependencies is the number of unscheduled
159 * instructions that must still be scheduled after
160 * (before) this instruction. dependents are which
161 * instructions need to be scheduled before (after) this
164 unsigned nr_dependencies
;
165 BITSET_WORD
*dependents
;
167 /* For load/store ops.. force 64-bit destination */
171 midgard_load_store_word load_store
;
172 midgard_vector_alu alu
;
173 midgard_texture_word texture
;
174 midgard_branch_extended branch_extended
;
177 /* General branch, rather than packed br_compact. Higher level
178 * than the other components */
179 midgard_branch branch
;
181 } midgard_instruction
;
183 typedef struct midgard_block
{
188 /* List of midgard_bundles emitted (after the scheduler has run) */
189 struct util_dynarray bundles
;
191 /* Number of quadwords _actually_ emitted, as determined after scheduling */
192 unsigned quadword_count
;
194 /* Indicates this is a fixed-function fragment epilogue block */
197 /* Are helper invocations required by this block? */
201 typedef struct midgard_bundle
{
202 /* Tag for the overall bundle */
205 /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
206 * sadd, vadd, smul, vlut, branch) */
207 int instruction_count
;
208 midgard_instruction
*instructions
[6];
210 /* Bundle-wide ALU configuration */
213 bool has_embedded_constants
;
214 midgard_constants constants
;
215 bool has_blend_constant
;
228 typedef struct compiler_context
{
230 gl_shader_stage stage
;
232 /* Is internally a blend shader? Depends on stage == FRAGMENT */
235 /* Render target number for a keyed blend shader. Depends on is_blend */
238 /* Tracking for blend constant patching */
239 int blend_constant_offset
;
241 /* Number of bytes used for Thread Local Storage */
244 /* Count of spills and fills for shaderdb */
248 /* Current NIR function */
251 /* Allocated compiler temporary counter */
254 /* Unordered list of midgard_blocks */
256 struct list_head blocks
;
258 /* TODO merge with block_count? */
259 unsigned block_source_count
;
261 /* List of midgard_instructions emitted for the current block */
262 midgard_block
*current_block
;
264 /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
265 midgard_block
*after_block
;
267 /* The current "depth" of the loop, for disambiguating breaks/continues
268 * when using nested loops */
269 int current_loop_depth
;
271 /* Total number of loops for shader-db */
274 /* Constants which have been loaded, for later inlining */
275 struct hash_table_u64
*ssa_constants
;
277 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
278 struct hash_table_u64
*hash_to_temp
;
282 /* Set of NIR indices that were already emitted as outmods */
283 BITSET_WORD
*already_emitted
;
285 /* Just the count of the max register used. Higher count => higher
286 * register pressure */
289 /* The number of uniforms allowable for the fast path */
292 /* Count of instructions emitted from NIR overall, across all blocks */
293 int instruction_count
;
295 /* Alpha ref value passed in */
298 unsigned quadword_count
;
300 /* Bitmask of valid metadata */
303 /* Model-specific quirk set */
306 /* Writeout instructions for each render target */
307 midgard_instruction
*writeout_branch
[MIDGARD_NUM_RTS
];
309 struct panfrost_sysvals sysvals
;
312 /* Per-block live_in/live_out */
313 #define MIDGARD_METADATA_LIVENESS (1 << 0)
315 /* Helpers for manipulating the above structures (forming the driver IR) */
317 /* Append instruction to end of current block */
319 static inline midgard_instruction
*
320 mir_upload_ins(struct compiler_context
*ctx
, struct midgard_instruction ins
)
322 midgard_instruction
*heap
= ralloc(ctx
, struct midgard_instruction
);
323 memcpy(heap
, &ins
, sizeof(ins
));
327 static inline midgard_instruction
*
328 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
330 midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
331 list_addtail(&u
->link
, &ctx
->current_block
->base
.instructions
);
335 static inline struct midgard_instruction
*
336 mir_insert_instruction_before(struct compiler_context
*ctx
,
337 struct midgard_instruction
*tag
,
338 struct midgard_instruction ins
)
340 struct midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
341 list_addtail(&u
->link
, &tag
->link
);
346 mir_remove_instruction(struct midgard_instruction
*ins
)
348 list_del(&ins
->link
);
351 static inline midgard_instruction
*
352 mir_prev_op(struct midgard_instruction
*ins
)
354 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
357 static inline midgard_instruction
*
358 mir_next_op(struct midgard_instruction
*ins
)
360 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
363 #define mir_foreach_block(ctx, v) \
364 list_for_each_entry(pan_block, v, &ctx->blocks, link)
366 #define mir_foreach_block_from(ctx, from, v) \
367 list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
369 #define mir_foreach_instr_in_block(block, v) \
370 list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
371 #define mir_foreach_instr_in_block_rev(block, v) \
372 list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
374 #define mir_foreach_instr_in_block_safe(block, v) \
375 list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
377 #define mir_foreach_instr_in_block_safe_rev(block, v) \
378 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
380 #define mir_foreach_instr_in_block_from(block, v, from) \
381 list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
383 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
384 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
386 #define mir_foreach_bundle_in_block(block, v) \
387 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
389 #define mir_foreach_bundle_in_block_rev(block, v) \
390 util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
392 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
393 midgard_instruction* v; \
395 mir_foreach_bundle_in_block_rev(block, _bundle) \
396 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
398 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
400 #define mir_foreach_instr_global(ctx, v) \
401 mir_foreach_block(ctx, v_block) \
402 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
404 #define mir_foreach_instr_global_safe(ctx, v) \
405 mir_foreach_block(ctx, v_block) \
406 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
408 /* Based on set_foreach, expanded with automatic type casts */
410 #define mir_foreach_predecessor(blk, v) \
411 struct set_entry *_entry_##v; \
412 struct midgard_block *v; \
413 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
414 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL); \
415 _entry_##v != NULL; \
416 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
417 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
419 #define mir_foreach_src(ins, v) \
420 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
422 static inline midgard_instruction
*
423 mir_last_in_block(struct midgard_block
*block
)
425 return list_last_entry(&block
->base
.instructions
, struct midgard_instruction
, link
);
428 static inline midgard_block
*
429 mir_get_block(compiler_context
*ctx
, int idx
)
431 struct list_head
*lst
= &ctx
->blocks
;
436 return (struct midgard_block
*) lst
;
440 mir_is_alu_bundle(midgard_bundle
*bundle
)
442 return IS_ALU(bundle
->tag
);
445 static inline unsigned
446 make_compiler_temp(compiler_context
*ctx
)
448 return (ctx
->func
->impl
->ssa_alloc
+ ctx
->temp_alloc
++) << 1;
451 static inline unsigned
452 make_compiler_temp_reg(compiler_context
*ctx
)
454 return ((ctx
->func
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | PAN_IS_REG
;
457 static inline unsigned
458 nir_ssa_index(nir_ssa_def
*ssa
)
460 return (ssa
->index
<< 1) | 0;
463 static inline unsigned
464 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
467 return nir_ssa_index(src
->ssa
);
469 assert(!src
->reg
.indirect
);
470 return (src
->reg
.reg
->index
<< 1) | PAN_IS_REG
;
474 static inline unsigned
475 nir_dest_index(nir_dest
*dst
)
478 return (dst
->ssa
.index
<< 1) | 0;
480 assert(!dst
->reg
.indirect
);
481 return (dst
->reg
.reg
->index
<< 1) | PAN_IS_REG
;
487 /* MIR manipulation */
489 void mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new);
490 void mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new);
491 void mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new);
492 void mir_rewrite_index_dst_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
493 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
494 void mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned *swizzle
);
495 bool mir_single_use(compiler_context
*ctx
, unsigned value
);
496 unsigned mir_use_count(compiler_context
*ctx
, unsigned value
);
497 uint16_t mir_bytemask_of_read_components(midgard_instruction
*ins
, unsigned node
);
498 uint16_t mir_bytemask_of_read_components_index(midgard_instruction
*ins
, unsigned i
);
499 uint16_t mir_from_bytemask(uint16_t bytemask
, unsigned bits
);
500 uint16_t mir_bytemask(midgard_instruction
*ins
);
501 uint16_t mir_round_bytemask_up(uint16_t mask
, unsigned bits
);
502 void mir_set_bytemask(midgard_instruction
*ins
, uint16_t bytemask
);
503 signed mir_upper_override(midgard_instruction
*ins
, unsigned inst_size
);
507 void mir_print_instruction(midgard_instruction
*ins
);
508 void mir_print_bundle(midgard_bundle
*ctx
);
509 void mir_print_block(midgard_block
*block
);
510 void mir_print_shader(compiler_context
*ctx
);
511 bool mir_nontrivial_mod(midgard_instruction
*ins
, unsigned i
, bool check_swizzle
);
512 bool mir_nontrivial_outmod(midgard_instruction
*ins
);
514 void mir_insert_instruction_before_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
515 void mir_insert_instruction_after_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
516 void mir_flip(midgard_instruction
*ins
);
517 void mir_compute_temp_count(compiler_context
*ctx
);
519 void mir_set_offset(compiler_context
*ctx
, midgard_instruction
*ins
, nir_src
*offset
, bool is_shared
);
521 /* 'Intrinsic' move for aliasing */
523 static inline midgard_instruction
524 v_mov(unsigned src
, unsigned dest
)
526 midgard_instruction ins
= {
529 .src
= { ~0, src
, ~0, ~0 },
530 .src_types
= { 0, nir_type_uint32
},
531 .swizzle
= SWIZZLE_IDENTITY
,
533 .dest_type
= nir_type_uint32
,
535 .op
= midgard_alu_op_imov
,
536 .reg_mode
= midgard_reg_mode_32
,
537 .outmod
= midgard_outmod_int_wrap
544 /* Broad types of register classes so we can handle special
547 #define REG_CLASS_WORK 0
548 #define REG_CLASS_LDST 1
549 #define REG_CLASS_TEXR 3
550 #define REG_CLASS_TEXW 4
552 /* Like a move, but to thread local storage! */
554 static inline midgard_instruction
555 v_load_store_scratch(
561 /* We index by 32-bit vec4s */
562 unsigned byte
= (index
* 4 * 4);
564 midgard_instruction ins
= {
565 .type
= TAG_LOAD_STORE_4
,
567 .dest_type
= nir_type_uint32
,
569 .src
= { ~0, ~0, ~0, ~0 },
570 .swizzle
= SWIZZLE_IDENTITY_4
,
572 .op
= is_store
? midgard_op_st_int4
: midgard_op_ld_int4
,
574 /* For register spilling - to thread local storage */
579 /* If we spill an unspill, RA goes into an infinite loop */
580 .no_spill
= (1 << REG_CLASS_WORK
)
583 ins
.constants
.u32
[0] = byte
;
586 ins
.src
[0] = srcdest
;
587 ins
.src_types
[0] = nir_type_uint32
;
589 /* Ensure we are tightly swizzled so liveness analysis is
592 for (unsigned i
= 0; i
< 4; ++i
) {
593 if (!(mask
& (1 << i
)))
594 ins
.swizzle
[0][i
] = COMPONENT_X
;
603 mir_has_arg(midgard_instruction
*ins
, unsigned arg
)
608 mir_foreach_src(ins
, i
) {
609 if (ins
->src
[i
] == arg
)
618 void midgard_schedule_program(compiler_context
*ctx
);
620 void mir_ra(compiler_context
*ctx
);
621 void mir_squeeze_index(compiler_context
*ctx
);
622 void mir_lower_special_reads(compiler_context
*ctx
);
623 void mir_liveness_ins_update(uint16_t *live
, midgard_instruction
*ins
, unsigned max
);
624 void mir_compute_liveness(compiler_context
*ctx
);
625 void mir_invalidate_liveness(compiler_context
*ctx
);
626 bool mir_is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
);
628 void mir_create_pipeline_registers(compiler_context
*ctx
);
629 void midgard_promote_uniforms(compiler_context
*ctx
);
632 midgard_emit_derivatives(compiler_context
*ctx
, nir_alu_instr
*instr
);
635 midgard_lower_derivatives(compiler_context
*ctx
, midgard_block
*block
);
637 bool mir_op_computes_derivatives(gl_shader_stage stage
, unsigned op
);
639 void mir_analyze_helper_terminate(compiler_context
*ctx
);
640 void mir_analyze_helper_requirements(compiler_context
*ctx
);
644 void emit_binary_bundle(
645 compiler_context
*ctx
,
646 midgard_bundle
*bundle
,
647 struct util_dynarray
*emission
,
651 nir_undef_to_zero(nir_shader
*shader
);
653 void midgard_nir_lod_errata(nir_shader
*shader
);
657 bool midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
);
658 bool midgard_opt_combine_projection(compiler_context
*ctx
, midgard_block
*block
);
659 bool midgard_opt_varying_projection(compiler_context
*ctx
, midgard_block
*block
);
660 bool midgard_opt_dead_code_eliminate(compiler_context
*ctx
);
661 bool midgard_opt_dead_move_eliminate(compiler_context
*ctx
, midgard_block
*block
);