2 * Copyright (C) 2019 Alyssa Rosenzweig <alyssa@rosenzweig.io>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 #ifndef _MDG_COMPILER_H
25 #define _MDG_COMPILER_H
29 #include "midgard_compile.h"
30 #include "midgard_ops.h"
32 #include "util/hash_table.h"
33 #include "util/u_dynarray.h"
35 #include "util/list.h"
37 #include "main/mtypes.h"
38 #include "compiler/nir_types.h"
39 #include "compiler/nir/nir.h"
40 #include "panfrost/util/pan_ir.h"
41 #include "panfrost/util/lcra.h"
46 /* Target types. Defaults to TARGET_GOTO (the type corresponding directly to
47 * the hardware), hence why that must be zero. TARGET_DISCARD signals this
48 * instruction is actually a discard op. */
51 #define TARGET_BREAK 1
52 #define TARGET_CONTINUE 2
53 #define TARGET_DISCARD 3
55 typedef struct midgard_branch
{
56 /* If conditional, the condition is specified in r31.w */
59 /* For conditionals, if this is true, we branch on FALSE. If false, we branch on TRUE. */
60 bool invert_conditional
;
62 /* Branch targets: the start of a block, the start of a loop (continue), the end of a loop (break). Value is one of TARGET_ */
65 /* The actual target */
73 /* Generic in-memory data type repesenting a single logical instruction, rather
74 * than a single instruction group. This is the preferred form for code gen.
75 * Multiple midgard_insturctions will later be combined during scheduling,
76 * though this is not represented in this structure. Its format bridges
77 * the low-level binary representation with the higher level semantic meaning.
79 * Notably, it allows registers to be specified as block local SSA, for code
80 * emitted before the register allocation pass.
83 #define MIR_SRC_COUNT 4
84 #define MIR_VEC_COMPONENTS 16
86 typedef struct midgard_instruction
{
87 /* Must be first for casting */
88 struct list_head link
;
90 unsigned type
; /* ALU, load/store, texture */
92 /* Instruction arguments represented as block-local SSA
93 * indices, rather than registers. ~0 means unused. */
94 unsigned src
[MIR_SRC_COUNT
];
97 /* vec16 swizzle, unpacked, per source */
98 unsigned swizzle
[MIR_SRC_COUNT
][MIR_VEC_COMPONENTS
];
101 nir_alu_type src_types
[MIR_SRC_COUNT
];
102 nir_alu_type dest_type
;
104 /* Special fields for an ALU instruction */
105 midgard_reg_info registers
;
107 /* For textures: should helpers execute this instruction (instead of
108 * just helping with derivatives)? Should helpers terminate after? */
109 bool helper_terminate
;
112 /* I.e. (1 << alu_bit) */
116 midgard_constants constants
;
117 uint16_t inline_constant
;
118 bool has_blend_constant
;
119 bool has_inline_constant
;
124 bool writeout_stencil
;
127 /* Masks in a saneish format. One bit per channel, not packed fancy.
128 * Use this instead of the op specific ones, and switch over at emit
133 /* For ALU ops only: set to true to invert (bitwise NOT) the
134 * destination of an integer-out op. Not implemented in hardware but
135 * allows more optimizations */
139 /* Hint for the register allocator not to spill the destination written
140 * from this instruction (because it is a spill/unspill node itself).
141 * Bitmask of spilled classes */
145 /* Generic hint for intra-pass use */
148 /* During scheduling, the backwards dependency graph
149 * (DAG). nr_dependencies is the number of unscheduled
150 * instructions that must still be scheduled after
151 * (before) this instruction. dependents are which
152 * instructions need to be scheduled before (after) this
155 unsigned nr_dependencies
;
156 BITSET_WORD
*dependents
;
158 /* For load/store ops.. force 64-bit destination */
162 midgard_load_store_word load_store
;
163 midgard_vector_alu alu
;
164 midgard_texture_word texture
;
165 midgard_branch_extended branch_extended
;
168 /* General branch, rather than packed br_compact. Higher level
169 * than the other components */
170 midgard_branch branch
;
172 } midgard_instruction
;
174 typedef struct midgard_block
{
179 /* List of midgard_bundles emitted (after the scheduler has run) */
180 struct util_dynarray bundles
;
182 /* Number of quadwords _actually_ emitted, as determined after scheduling */
183 unsigned quadword_count
;
185 /* Indicates this is a fixed-function fragment epilogue block */
188 /* Are helper invocations required by this block? */
192 typedef struct midgard_bundle
{
193 /* Tag for the overall bundle */
196 /* Instructions contained by the bundle. instruction_count <= 6 (vmul,
197 * sadd, vadd, smul, vlut, branch) */
198 int instruction_count
;
199 midgard_instruction
*instructions
[6];
201 /* Bundle-wide ALU configuration */
204 bool has_embedded_constants
;
205 midgard_constants constants
;
206 bool has_blend_constant
;
219 typedef struct compiler_context
{
221 gl_shader_stage stage
;
223 /* Is internally a blend shader? Depends on stage == FRAGMENT */
226 /* Render target number for a keyed blend shader. Depends on is_blend */
229 /* Tracking for blend constant patching */
230 int blend_constant_offset
;
232 /* Number of bytes used for Thread Local Storage */
235 /* Count of spills and fills for shaderdb */
239 /* Current NIR function */
242 /* Allocated compiler temporary counter */
245 /* Unordered list of midgard_blocks */
247 struct list_head blocks
;
249 /* TODO merge with block_count? */
250 unsigned block_source_count
;
252 /* List of midgard_instructions emitted for the current block */
253 midgard_block
*current_block
;
255 /* If there is a preset after block, use this, otherwise emit_block will create one if NULL */
256 midgard_block
*after_block
;
258 /* The current "depth" of the loop, for disambiguating breaks/continues
259 * when using nested loops */
260 int current_loop_depth
;
262 /* Total number of loops for shader-db */
265 /* Constants which have been loaded, for later inlining */
266 struct hash_table_u64
*ssa_constants
;
268 /* Mapping of hashes computed from NIR indices to the sequential temp indices ultimately used in MIR */
269 struct hash_table_u64
*hash_to_temp
;
273 /* Just the count of the max register used. Higher count => higher
274 * register pressure */
277 /* Used for cont/last hinting. Increase when a tex op is added.
278 * Decrease when a tex op is removed. */
279 int texture_op_count
;
281 /* The number of uniforms allowable for the fast path */
284 /* Count of instructions emitted from NIR overall, across all blocks */
285 int instruction_count
;
287 /* Alpha ref value passed in */
290 unsigned quadword_count
;
292 /* Bitmask of valid metadata */
295 /* Model-specific quirk set */
298 /* Writeout instructions for each render target */
299 midgard_instruction
*writeout_branch
[MIDGARD_NUM_RTS
];
301 struct panfrost_sysvals sysvals
;
304 /* Per-block live_in/live_out */
305 #define MIDGARD_METADATA_LIVENESS (1 << 0)
307 /* Helpers for manipulating the above structures (forming the driver IR) */
309 /* Append instruction to end of current block */
311 static inline midgard_instruction
*
312 mir_upload_ins(struct compiler_context
*ctx
, struct midgard_instruction ins
)
314 midgard_instruction
*heap
= ralloc(ctx
, struct midgard_instruction
);
315 memcpy(heap
, &ins
, sizeof(ins
));
319 static inline midgard_instruction
*
320 emit_mir_instruction(struct compiler_context
*ctx
, struct midgard_instruction ins
)
322 midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
323 list_addtail(&u
->link
, &ctx
->current_block
->base
.instructions
);
327 static inline struct midgard_instruction
*
328 mir_insert_instruction_before(struct compiler_context
*ctx
,
329 struct midgard_instruction
*tag
,
330 struct midgard_instruction ins
)
332 struct midgard_instruction
*u
= mir_upload_ins(ctx
, ins
);
333 list_addtail(&u
->link
, &tag
->link
);
338 mir_remove_instruction(struct midgard_instruction
*ins
)
340 list_del(&ins
->link
);
343 static inline midgard_instruction
*
344 mir_prev_op(struct midgard_instruction
*ins
)
346 return list_last_entry(&(ins
->link
), midgard_instruction
, link
);
349 static inline midgard_instruction
*
350 mir_next_op(struct midgard_instruction
*ins
)
352 return list_first_entry(&(ins
->link
), midgard_instruction
, link
);
355 #define mir_foreach_block(ctx, v) \
356 list_for_each_entry(pan_block, v, &ctx->blocks, link)
358 #define mir_foreach_block_from(ctx, from, v) \
359 list_for_each_entry_from(pan_block, v, &from->base, &ctx->blocks, link)
361 #define mir_foreach_instr_in_block(block, v) \
362 list_for_each_entry(struct midgard_instruction, v, &block->base.instructions, link)
363 #define mir_foreach_instr_in_block_rev(block, v) \
364 list_for_each_entry_rev(struct midgard_instruction, v, &block->base.instructions, link)
366 #define mir_foreach_instr_in_block_safe(block, v) \
367 list_for_each_entry_safe(struct midgard_instruction, v, &block->base.instructions, link)
369 #define mir_foreach_instr_in_block_safe_rev(block, v) \
370 list_for_each_entry_safe_rev(struct midgard_instruction, v, &block->base.instructions, link)
372 #define mir_foreach_instr_in_block_from(block, v, from) \
373 list_for_each_entry_from(struct midgard_instruction, v, from, &block->base.instructions, link)
375 #define mir_foreach_instr_in_block_from_rev(block, v, from) \
376 list_for_each_entry_from_rev(struct midgard_instruction, v, from, &block->base.instructions, link)
378 #define mir_foreach_bundle_in_block(block, v) \
379 util_dynarray_foreach(&block->bundles, midgard_bundle, v)
381 #define mir_foreach_bundle_in_block_rev(block, v) \
382 util_dynarray_foreach_reverse(&block->bundles, midgard_bundle, v)
384 #define mir_foreach_instr_in_block_scheduled_rev(block, v) \
385 midgard_instruction* v; \
387 mir_foreach_bundle_in_block_rev(block, _bundle) \
388 for (i = (_bundle->instruction_count - 1), v = _bundle->instructions[i]; \
390 --i, v = (i >= 0) ? _bundle->instructions[i] : NULL) \
392 #define mir_foreach_instr_global(ctx, v) \
393 mir_foreach_block(ctx, v_block) \
394 mir_foreach_instr_in_block(((midgard_block *) v_block), v)
396 #define mir_foreach_instr_global_safe(ctx, v) \
397 mir_foreach_block(ctx, v_block) \
398 mir_foreach_instr_in_block_safe(((midgard_block *) v_block), v)
400 /* Based on set_foreach, expanded with automatic type casts */
402 #define mir_foreach_predecessor(blk, v) \
403 struct set_entry *_entry_##v; \
404 struct midgard_block *v; \
405 for (_entry_##v = _mesa_set_next_entry(blk->base.predecessors, NULL), \
406 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL); \
407 _entry_##v != NULL; \
408 _entry_##v = _mesa_set_next_entry(blk->base.predecessors, _entry_##v), \
409 v = (struct midgard_block *) (_entry_##v ? _entry_##v->key : NULL))
411 #define mir_foreach_src(ins, v) \
412 for (unsigned v = 0; v < ARRAY_SIZE(ins->src); ++v)
414 static inline midgard_instruction
*
415 mir_last_in_block(struct midgard_block
*block
)
417 return list_last_entry(&block
->base
.instructions
, struct midgard_instruction
, link
);
420 static inline midgard_block
*
421 mir_get_block(compiler_context
*ctx
, int idx
)
423 struct list_head
*lst
= &ctx
->blocks
;
428 return (struct midgard_block
*) lst
;
432 mir_is_alu_bundle(midgard_bundle
*bundle
)
434 return IS_ALU(bundle
->tag
);
437 static inline unsigned
438 make_compiler_temp(compiler_context
*ctx
)
440 return (ctx
->func
->impl
->ssa_alloc
+ ctx
->temp_alloc
++) << 1;
443 static inline unsigned
444 make_compiler_temp_reg(compiler_context
*ctx
)
446 return ((ctx
->func
->impl
->reg_alloc
+ ctx
->temp_alloc
++) << 1) | PAN_IS_REG
;
449 static inline unsigned
450 nir_ssa_index(nir_ssa_def
*ssa
)
452 return (ssa
->index
<< 1) | 0;
455 static inline unsigned
456 nir_src_index(compiler_context
*ctx
, nir_src
*src
)
459 return nir_ssa_index(src
->ssa
);
461 assert(!src
->reg
.indirect
);
462 return (src
->reg
.reg
->index
<< 1) | PAN_IS_REG
;
466 static inline unsigned
467 nir_dest_index(nir_dest
*dst
)
470 return (dst
->ssa
.index
<< 1) | 0;
472 assert(!dst
->reg
.indirect
);
473 return (dst
->reg
.reg
->index
<< 1) | PAN_IS_REG
;
479 /* MIR manipulation */
481 void mir_rewrite_index(compiler_context
*ctx
, unsigned old
, unsigned new);
482 void mir_rewrite_index_src(compiler_context
*ctx
, unsigned old
, unsigned new);
483 void mir_rewrite_index_dst(compiler_context
*ctx
, unsigned old
, unsigned new);
484 void mir_rewrite_index_dst_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
485 void mir_rewrite_index_src_single(midgard_instruction
*ins
, unsigned old
, unsigned new);
486 void mir_rewrite_index_src_swizzle(compiler_context
*ctx
, unsigned old
, unsigned new, unsigned *swizzle
);
487 bool mir_single_use(compiler_context
*ctx
, unsigned value
);
488 bool mir_special_index(compiler_context
*ctx
, unsigned idx
);
489 unsigned mir_use_count(compiler_context
*ctx
, unsigned value
);
490 bool mir_is_written_before(compiler_context
*ctx
, midgard_instruction
*ins
, unsigned node
);
491 uint16_t mir_bytemask_of_read_components(midgard_instruction
*ins
, unsigned node
);
492 uint16_t mir_bytemask_of_read_components_index(midgard_instruction
*ins
, unsigned i
);
493 midgard_reg_mode
mir_typesize(midgard_instruction
*ins
);
494 midgard_reg_mode
mir_srcsize(midgard_instruction
*ins
, unsigned i
);
495 unsigned mir_bytes_for_mode(midgard_reg_mode mode
);
496 midgard_reg_mode
mir_mode_for_destsize(unsigned size
);
497 uint16_t mir_from_bytemask(uint16_t bytemask
, midgard_reg_mode mode
);
498 uint16_t mir_bytemask(midgard_instruction
*ins
);
499 uint16_t mir_round_bytemask_up(uint16_t mask
, midgard_reg_mode mode
);
500 void mir_set_bytemask(midgard_instruction
*ins
, uint16_t bytemask
);
501 unsigned mir_upper_override(midgard_instruction
*ins
);
505 void mir_print_instruction(midgard_instruction
*ins
);
506 void mir_print_bundle(midgard_bundle
*ctx
);
507 void mir_print_block(midgard_block
*block
);
508 void mir_print_shader(compiler_context
*ctx
);
509 bool mir_nontrivial_source2_mod(midgard_instruction
*ins
);
510 bool mir_nontrivial_source2_mod_simple(midgard_instruction
*ins
);
511 bool mir_nontrivial_outmod(midgard_instruction
*ins
);
513 void mir_insert_instruction_before_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
514 void mir_insert_instruction_after_scheduled(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*tag
, midgard_instruction ins
);
515 void mir_flip(midgard_instruction
*ins
);
516 void mir_compute_temp_count(compiler_context
*ctx
);
518 void mir_set_offset(compiler_context
*ctx
, midgard_instruction
*ins
, nir_src
*offset
, bool is_shared
);
520 /* 'Intrinsic' move for aliasing */
522 static inline midgard_instruction
523 v_mov(unsigned src
, unsigned dest
)
525 midgard_instruction ins
= {
528 .src
= { ~0, src
, ~0, ~0 },
529 .src_types
= { 0, nir_type_uint32
},
530 .swizzle
= SWIZZLE_IDENTITY
,
532 .dest_type
= nir_type_uint32
,
534 .op
= midgard_alu_op_imov
,
535 .reg_mode
= midgard_reg_mode_32
,
536 .dest_override
= midgard_dest_override_none
,
537 .outmod
= midgard_outmod_int_wrap
544 /* Broad types of register classes so we can handle special
547 #define REG_CLASS_WORK 0
548 #define REG_CLASS_LDST 1
549 #define REG_CLASS_TEXR 3
550 #define REG_CLASS_TEXW 4
552 /* Like a move, but to thread local storage! */
554 static inline midgard_instruction
555 v_load_store_scratch(
561 /* We index by 32-bit vec4s */
562 unsigned byte
= (index
* 4 * 4);
564 midgard_instruction ins
= {
565 .type
= TAG_LOAD_STORE_4
,
568 .src
= { ~0, ~0, ~0, ~0 },
569 .swizzle
= SWIZZLE_IDENTITY_4
,
571 .op
= is_store
? midgard_op_st_int4
: midgard_op_ld_int4
,
573 /* For register spilling - to thread local storage */
578 /* If we spill an unspill, RA goes into an infinite loop */
579 .no_spill
= (1 << REG_CLASS_WORK
)
582 ins
.constants
.u32
[0] = byte
;
585 ins
.src
[0] = srcdest
;
587 /* Ensure we are tightly swizzled so liveness analysis is
590 for (unsigned i
= 0; i
< 4; ++i
) {
591 if (!(mask
& (1 << i
)))
592 ins
.swizzle
[0][i
] = COMPONENT_X
;
601 mir_has_arg(midgard_instruction
*ins
, unsigned arg
)
606 mir_foreach_src(ins
, i
) {
607 if (ins
->src
[i
] == arg
)
616 void midgard_schedule_program(compiler_context
*ctx
);
618 void mir_ra(compiler_context
*ctx
);
619 void mir_squeeze_index(compiler_context
*ctx
);
620 void mir_lower_special_reads(compiler_context
*ctx
);
621 void mir_liveness_ins_update(uint16_t *live
, midgard_instruction
*ins
, unsigned max
);
622 void mir_compute_liveness(compiler_context
*ctx
);
623 void mir_invalidate_liveness(compiler_context
*ctx
);
624 bool mir_is_live_after(compiler_context
*ctx
, midgard_block
*block
, midgard_instruction
*start
, int src
);
626 void mir_create_pipeline_registers(compiler_context
*ctx
);
627 void midgard_promote_uniforms(compiler_context
*ctx
);
630 midgard_emit_derivatives(compiler_context
*ctx
, nir_alu_instr
*instr
);
633 midgard_lower_derivatives(compiler_context
*ctx
, midgard_block
*block
);
635 bool mir_op_computes_derivatives(gl_shader_stage stage
, unsigned op
);
637 void mir_analyze_helper_terminate(compiler_context
*ctx
);
638 void mir_analyze_helper_requirements(compiler_context
*ctx
);
642 void emit_binary_bundle(
643 compiler_context
*ctx
,
644 midgard_bundle
*bundle
,
645 struct util_dynarray
*emission
,
649 nir_undef_to_zero(nir_shader
*shader
);
651 void midgard_nir_lod_errata(nir_shader
*shader
);
655 bool midgard_opt_copy_prop(compiler_context
*ctx
, midgard_block
*block
);
656 bool midgard_opt_combine_projection(compiler_context
*ctx
, midgard_block
*block
);
657 bool midgard_opt_varying_projection(compiler_context
*ctx
, midgard_block
*block
);
658 bool midgard_opt_dead_code_eliminate(compiler_context
*ctx
, midgard_block
*block
);
659 bool midgard_opt_dead_move_eliminate(compiler_context
*ctx
, midgard_block
*block
);
661 void midgard_lower_invert(compiler_context
*ctx
, midgard_block
*block
);
662 bool midgard_opt_not_propagate(compiler_context
*ctx
, midgard_block
*block
);
663 bool midgard_opt_fuse_src_invert(compiler_context
*ctx
, midgard_block
*block
);
664 bool midgard_opt_fuse_dest_invert(compiler_context
*ctx
, midgard_block
*block
);
665 bool midgard_opt_csel_invert(compiler_context
*ctx
, midgard_block
*block
);
666 bool midgard_opt_promote_fmov(compiler_context
*ctx
, midgard_block
*block
);
667 bool midgard_opt_drop_cmp_invert(compiler_context
*ctx
, midgard_block
*block
);
668 bool midgard_opt_invert_branch(compiler_context
*ctx
, midgard_block
*block
);